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GET /api/patches/110487/?format=api
{ "id": 110487, "url": "http://patchwork.ozlabs.org/api/patches/110487/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1313629178-31669-1-git-send-email-agnel.joel@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1313629178-31669-1-git-send-email-agnel.joel@gmail.com>", "list_archive_url": null, "date": "2011-08-18T00:59:38", "name": "[U-Boot,v4] OMAP3: Add DSS driver for OMAP3", "commit_ref": null, "pull_url": null, "state": "awaiting-upstream", "archived": false, "hash": "cc1543b7b8e31f719ac62c3e4ff79887d650a8d4", "submitter": { "id": 8387, "url": "http://patchwork.ozlabs.org/api/people/8387/?format=api", "name": "Joel Fernandes", "email": "agnel.joel@gmail.com" }, "delegate": { "id": 1713, "url": "http://patchwork.ozlabs.org/api/users/1713/?format=api", "username": "spaulraj", "first_name": "Sandeep", "last_name": "Paulraj", "email": "s-paulraj@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1313629178-31669-1-git-send-email-agnel.joel@gmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/110487/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/110487/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id A357CB6FA0\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 18 Aug 2011 11:00:02 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id A6EF728085;\n\tThu, 18 Aug 2011 03:00:00 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ZoV1Z+I8wpcI; Thu, 18 Aug 2011 03:00:00 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 7293E2807E;\n\tThu, 18 Aug 2011 02:59:58 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 4AC8D2807E\n\tfor <u-boot@lists.denx.de>; Thu, 18 Aug 2011 02:59:56 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id oY1ZTZr8omJ3 for <u-boot@lists.denx.de>;\n\tThu, 18 Aug 2011 02:59:54 +0200 (CEST)", "from mail-gy0-f172.google.com (mail-gy0-f172.google.com\n\t[209.85.160.172])\n\tby theia.denx.de (Postfix) with ESMTPS id 750E12807C\n\tfor <u-boot@lists.denx.de>; Thu, 18 Aug 2011 02:59:52 +0200 (CEST)", "by gyf3 with SMTP id 3so1068315gyf.3\n\tfor <u-boot@lists.denx.de>; Wed, 17 Aug 2011 17:59:51 -0700 (PDT)", "by 10.236.185.228 with SMTP id u64mr97875yhm.91.1313629191378;\n\tWed, 17 Aug 2011 17:59:51 -0700 (PDT)", "from localhost.localdomain (cpe-76-184-244-226.tx.res.rr.com\n\t[76.184.244.226])\n\tby mx.google.com with ESMTPS id f4sm250865yhn.83.2011.08.17.17.59.49\n\t(version=TLSv1/SSLv3 cipher=OTHER);\n\tWed, 17 Aug 2011 17:59:50 -0700 (PDT)" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Joel A Fernandes <agnel.joel@gmail.com>", "To": "u-boot@lists.denx.de", "Date": "Wed, 17 Aug 2011 19:59:38 -0500", "Message-Id": "<1313629178-31669-1-git-send-email-agnel.joel@gmail.com>", "X-Mailer": "git-send-email 1.7.1", "Cc": "Syed Mohammed Khasim <khasim@ti.com>, k-kooi@ti.com, jdk@ti.com", "Subject": "[U-Boot] [PATCH v4] OMAP3: Add DSS driver for OMAP3", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.9", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "From: Syed Mohammed Khasim <khasim@ti.com>\n\n* Supports dynamic panel configuration\n* Supports dynamic tv standard selection\n* Adds support for DSS register access through generic APIs\n* Incorporated DSS register access using structures.\n* DSS makefile update\n\nPrevious discussions are here:\nhttp://www.mail-archive.com/u-boot@lists.denx.de/msg27150.html\n---\nv2 updates:\n * Enable panel output for BeagleBoard\n * BeagleBoard: Update DVI-D orange screen frequencies for xM\n\nv3 updates:\n * Remove non-platform (OMAP3) updates\n\nv4 updates:\n * Addressing fixes for attribution in header:\n http://lists.denx.de/pipermail/u-boot/2011-August/097976.html\n\nSigned-off-by: Syed Mohammed Khasim <khasim@ti.com>\nSigned-off-by: Jason Kridner <jkridner@beagleboard.org>\nSigned-off-by: Joel A Fernandes <agnel.joel@gmail.com>\n---\n arch/arm/include/asm/arch-omap3/dss.h | 174 +++++++++++++++++++++++++++++++++\n drivers/video/Makefile | 2 +\n drivers/video/omap3_dss.c | 131 +++++++++++++++++++++++++\n 3 files changed, 307 insertions(+), 0 deletions(-)\n create mode 100644 arch/arm/include/asm/arch-omap3/dss.h\n create mode 100644 drivers/video/omap3_dss.c", "diff": "diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h\nnew file mode 100644\nindex 0000000..c09ded8\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-omap3/dss.h\n@@ -0,0 +1,174 @@\n+/*\n+ * (C) Copyright 2010\n+ * Texas Instruments, <www.ti.com>\n+ * Syed Mohammed Khasim <khasim@ti.com>\n+ *\n+ * Referred to Linux Kernel DSS driver files for OMAP3 by \n+ * Tomi Valkeinen from drivers/video/omap2/dss/ \n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation's version 2 and any\n+ * later version the License.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n+ * MA 02111-1307 USA\n+ */\n+\n+#ifndef DSS_H\n+#define DSS_H\n+\n+/*\n+ * DSS Base Registers\n+ */\n+#define OMAP3_DSS_BASE\t\t0x48050040\n+#define OMAP3_DISPC_BASE\t0x48050440\n+#define OMAP3_VENC_BASE\t\t0x48050C00\n+\n+/* DSS Registers */\n+struct dss_regs {\n+\tu32 control;\t\t\t\t/* 0x40 */\n+\tu32 sdi_control;\t\t\t/* 0x44 */\n+\tu32 pll_control;\t\t\t/* 0x48 */\n+};\n+\n+/* DISPC Registers */\n+struct dispc_regs {\n+\tu32 control;\t\t\t\t/* 0x40 */\n+\tu32 config;\t\t\t\t/* 0x44 */\n+\tu32 reserve_2;\t\t\t\t/* 0x48 */\n+\tu32 default_color0;\t\t\t/* 0x4C */\n+\tu32 default_color1;\t\t\t/* 0x50 */\n+\tu32 trans_color0;\t\t\t/* 0x54 */\n+\tu32 trans_color1;\t\t\t/* 0x58 */\n+\tu32 line_status;\t\t\t/* 0x5C */\n+\tu32 line_number;\t\t\t/* 0x60 */\n+\tu32 timing_h;\t\t\t\t/* 0x64 */\n+\tu32 timing_v;\t\t\t\t/* 0x68 */\n+\tu32 pol_freq;\t\t\t\t/* 0x6C */\n+\tu32 divisor;\t\t\t\t/* 0x70 */\n+\tu32 global_alpha;\t\t\t/* 0x74 */\n+\tu32 size_dig;\t\t\t\t/* 0x78 */\n+\tu32 size_lcd;\t\t\t\t/* 0x7C */\n+};\n+\n+/* VENC Registers */\n+struct venc_regs {\n+\tu32 rev_id;\t\t\t\t/* 0x00 */\n+\tu32 status;\t\t\t\t/* 0x04 */\n+\tu32 f_control;\t\t\t\t/* 0x08 */\n+\tu32 reserve_1;\t\t\t\t/* 0x0C */\n+\tu32 vidout_ctrl;\t\t\t/* 0x10 */\n+\tu32 sync_ctrl;\t\t\t\t/* 0x14 */\n+\tu32 reserve_2;\t\t\t\t/* 0x18 */\n+\tu32 llen;\t\t\t\t/* 0x1C */\n+\tu32 flens;\t\t\t\t/* 0x20 */\n+\tu32 hfltr_ctrl;\t\t\t\t/* 0x24 */\n+\tu32 cc_carr_wss_carr;\t\t\t/* 0x28 */\n+\tu32 c_phase;\t\t\t\t/* 0x2C */\n+\tu32 gain_u;\t\t\t\t/* 0x30 */\n+\tu32 gain_v;\t\t\t\t/* 0x34 */\n+\tu32 gain_y;\t\t\t\t/* 0x38 */\n+\tu32 black_level;\t\t\t/* 0x3C */\n+\tu32 blank_level;\t\t\t/* 0x40 */\n+\tu32 x_color;\t\t\t\t/* 0x44 */\n+\tu32 m_control;\t\t\t\t/* 0x48 */\n+\tu32 bstamp_wss_data;\t\t\t/* 0x4C */\n+\tu32 s_carr;\t\t\t\t/* 0x50 */\n+\tu32 line21;\t\t\t\t/* 0x54 */\n+\tu32 ln_sel;\t\t\t\t/* 0x58 */\n+\tu32 l21__wc_ctl;\t\t\t/* 0x5C */\n+\tu32 htrigger_vtrigger;\t\t\t/* 0x60 */\n+\tu32 savid__eavid;\t\t\t/* 0x64 */\n+\tu32 flen__fal;\t\t\t\t/* 0x68 */\n+\tu32 lal__phase_reset;\t\t\t/* 0x6C */\n+\tu32 hs_int_start_stop_x;\t\t/* 0x70 */\n+\tu32 hs_ext_start_stop_x;\t\t/* 0x74 */\n+\tu32 vs_int_start_x;\t\t\t/* 0x78 */\n+\tu32 vs_int_stop_x__vs_int_start_y;\t/* 0x7C */\n+\tu32 vs_int_stop_y__vs_ext_start_x;\t/* 0x80 */\n+\tu32 vs_ext_stop_x__vs_ext_start_y;\t/* 0x84 */\n+\tu32 vs_ext_stop_y;\t\t\t/* 0x88 */\n+\tu32 reserve_3;\t\t\t\t/* 0x8C */\n+\tu32 avid_start_stop_x;\t\t\t/* 0x90 */\n+\tu32 avid_start_stop_y;\t\t\t/* 0x94 */\n+\tu32 reserve_4;\t\t\t\t/* 0x98 */\n+\tu32 reserve_5;\t\t\t\t/* 0x9C */\n+\tu32 fid_int_start_x__fid_int_start_y;\t/* 0xA0 */\n+\tu32 fid_int_offset_y__fid_ext_start_x;\t/* 0xA4 */\n+\tu32 fid_ext_start_y__fid_ext_offset_y;\t/* 0xA8 */\n+\tu32 reserve_6;\t\t\t\t/* 0xAC */\n+\tu32 tvdetgp_int_start_stop_x;\t\t/* 0xB0 */\n+\tu32 tvdetgp_int_start_stop_y;\t\t/* 0xB4 */\n+\tu32 gen_ctrl;\t\t\t\t/* 0xB8 */\n+\tu32 reserve_7;\t\t\t\t/* 0xBC */\n+\tu32 reserve_8;\t\t\t\t/* 0xC0 */\n+\tu32 output_control;\t\t\t/* 0xC4 */\n+\tu32 dac_b__dac_c;\t\t\t/* 0xC8 */\n+\tu32 height_width;\t\t\t/* 0xCC */\n+};\n+\n+/* Few Register Offsets */\n+#define FRAME_MODE_SHIFT\t\t\t1\n+#define TFTSTN_SHIFT\t\t\t\t3\n+#define DATALINES_SHIFT\t\t\t\t8\n+\n+/* Enabling Display controller */\n+#define LCD_ENABLE\t\t\t\t1\n+#define DIG_ENABLE\t\t\t\t(1 << 1)\n+#define GO_LCD\t\t\t\t\t(1 << 5)\n+#define GO_DIG\t\t\t\t\t(1 << 6)\n+#define GP_OUT0\t\t\t\t\t(1 << 15)\n+#define GP_OUT1\t\t\t\t\t(1 << 16)\n+\n+#define DISPC_ENABLE\t\t\t\t(LCD_ENABLE | \\\n+\t\t\t\t\t\t DIG_ENABLE | \\\n+\t\t\t\t\t\t GO_LCD | \\\n+\t\t\t\t\t\t GO_DIG | \\\n+\t\t\t\t\t\t GP_OUT0| \\\n+\t\t\t\t\t\t GP_OUT1)\n+\n+/* Configure VENC DSS Params */\n+#define VENC_CLK_ENABLE\t\t\t\t(1 << 3)\n+#define DAC_DEMEN\t\t\t\t(1 << 4)\n+#define DAC_POWERDN\t\t\t\t(1 << 5)\n+#define VENC_OUT_SEL\t\t\t\t(1 << 6)\n+#define DIG_LPP_SHIFT\t\t\t\t16\n+#define VENC_DSS_CONFIG\t\t\t\t(VENC_CLK_ENABLE | \\\n+\t\t\t\t\t\t DAC_DEMEN | \\\n+\t\t\t\t\t\t DAC_POWERDN | \\\n+\t\t\t\t\t\t VENC_OUT_SEL)\n+/*\n+ * Panel Configuration\n+ */\n+struct panel_config {\n+\tu32 timing_h;\n+\tu32 timing_v;\n+\tu32 pol_freq;\n+\tu32 divisor;\n+\tu32 lcd_size;\n+\tu32 panel_type;\n+\tu32 data_lines;\n+\tu32 load_mode;\n+\tu32 panel_color;\n+};\n+\n+/*\n+ * Generic DSS Functions\n+ */\n+void omap3_dss_venc_config(const struct venc_regs *venc_cfg,\n+\t\t\tu32 height, u32 width);\n+void omap3_dss_panel_config(const struct panel_config *panel_cfg);\n+void omap3_dss_enable(void);\n+\n+#endif /* DSS_H */\ndiff --git a/drivers/video/Makefile b/drivers/video/Makefile\nindex 086dc05..226684a 100644\n--- a/drivers/video/Makefile\n+++ b/drivers/video/Makefile\n@@ -41,6 +41,8 @@ COBJS-$(CONFIG_SED156X) += sed156x.o\n COBJS-$(CONFIG_VIDEO_SM501) += sm501.o\n COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o\n COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o\n+COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o\n+COBJS-y += videomodes.o\n \n COBJS\t:= $(COBJS-y)\n SRCS\t:= $(COBJS:.o=.c)\ndiff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c\nnew file mode 100644\nindex 0000000..6c743d2\n--- /dev/null\n+++ b/drivers/video/omap3_dss.c\n@@ -0,0 +1,131 @@\n+/*\n+ * (C) Copyright 2010\n+ * Texas Instruments, <www.ti.com>\n+ * Syed Mohammed Khasim <khasim@ti.com>\n+ *\n+ * Referred to Linux Kernel DSS driver files for OMAP3 by \n+ * Tomi Valkeinen from drivers/video/omap2/dss/ \n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation's version 2 and any\n+ * later version the License.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n+ * MA 02111-1307 USA\n+ */\n+\n+#include <common.h>\n+#include <asm/io.h>\n+#include <asm/arch/dss.h>\n+\n+/*\n+ * Configure VENC for a given Mode (NTSC / PAL)\n+ */\n+void omap3_dss_venc_config(const struct venc_regs *venc_cfg,\n+\t\t\t\tu32 height, u32 width)\n+{\n+\tstruct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE;\n+\tstruct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;\n+\tstruct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;\n+\n+\twritel(venc_cfg->status, &venc->status);\n+\twritel(venc_cfg->f_control, &venc->f_control);\n+\twritel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl);\n+\twritel(venc_cfg->sync_ctrl, &venc->sync_ctrl);\n+\twritel(venc_cfg->llen, &venc->llen);\n+\twritel(venc_cfg->flens, &venc->flens);\n+\twritel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl);\n+\twritel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr);\n+\twritel(venc_cfg->c_phase, &venc->c_phase);\n+\twritel(venc_cfg->gain_u, &venc->gain_u);\n+\twritel(venc_cfg->gain_v, &venc->gain_v);\n+\twritel(venc_cfg->gain_y, &venc->gain_y);\n+\twritel(venc_cfg->black_level, &venc->black_level);\n+\twritel(venc_cfg->blank_level, &venc->blank_level);\n+\twritel(venc_cfg->x_color, &venc->x_color);\n+\twritel(venc_cfg->m_control, &venc->m_control);\n+\twritel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data);\n+\twritel(venc_cfg->s_carr, &venc->s_carr);\n+\twritel(venc_cfg->line21, &venc->line21);\n+\twritel(venc_cfg->ln_sel, &venc->ln_sel);\n+\twritel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl);\n+\twritel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger);\n+\twritel(venc_cfg->savid__eavid, &venc->savid__eavid);\n+\twritel(venc_cfg->flen__fal, &venc->flen__fal);\n+\twritel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);\n+\twritel(venc_cfg->hs_int_start_stop_x,\n+\t\t\t\t&venc->hs_int_start_stop_x);\n+\twritel(venc_cfg->hs_ext_start_stop_x,\n+\t\t\t\t&venc->hs_ext_start_stop_x);\n+\twritel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);\n+\twritel(venc_cfg->vs_int_stop_x__vs_int_start_y,\n+\t\t\t&venc->vs_int_stop_x__vs_int_start_y);\n+\twritel(venc_cfg->vs_int_stop_y__vs_ext_start_x,\n+\t\t\t&venc->vs_int_stop_y__vs_ext_start_x);\n+\twritel(venc_cfg->vs_ext_stop_x__vs_ext_start_y,\n+\t\t\t&venc->vs_ext_stop_x__vs_ext_start_y);\n+\twritel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y);\n+\twritel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x);\n+\twritel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y);\n+\twritel(venc_cfg->fid_int_start_x__fid_int_start_y,\n+\t\t\t\t&venc->fid_int_start_x__fid_int_start_y);\n+\twritel(venc_cfg->fid_int_offset_y__fid_ext_start_x,\n+\t\t\t\t&venc->fid_int_offset_y__fid_ext_start_x);\n+\twritel(venc_cfg->fid_ext_start_y__fid_ext_offset_y,\n+\t\t\t\t&venc->fid_ext_start_y__fid_ext_offset_y);\n+\twritel(venc_cfg->tvdetgp_int_start_stop_x,\n+\t\t\t\t&venc->tvdetgp_int_start_stop_x);\n+\twritel(venc_cfg->tvdetgp_int_start_stop_y,\n+\t\t\t\t&venc->tvdetgp_int_start_stop_y);\n+\twritel(venc_cfg->gen_ctrl, &venc->gen_ctrl);\n+\twritel(venc_cfg->output_control, &venc->output_control);\n+\twritel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);\n+\n+\t/* Configure DSS for VENC Settings */\n+\twritel(VENC_DSS_CONFIG, &dss->control);\n+\n+\t/* Configure height and width for Digital out */\n+\twritel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig);\n+}\n+\n+/*\n+ * Configure Panel Specific Parameters\n+ */\n+void omap3_dss_panel_config(const struct panel_config *panel_cfg)\n+{\n+\tstruct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;\n+\n+\twritel(panel_cfg->timing_h, &dispc->timing_h);\n+\twritel(panel_cfg->timing_v, &dispc->timing_v);\n+\twritel(panel_cfg->pol_freq, &dispc->pol_freq);\n+\twritel(panel_cfg->divisor, &dispc->divisor);\n+\twritel(panel_cfg->lcd_size, &dispc->size_lcd);\n+\twritel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config);\n+\twritel(((panel_cfg->panel_type << TFTSTN_SHIFT) |\n+\t\t(panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control);\n+\twritel(panel_cfg->panel_color, &dispc->default_color0);\n+}\n+\n+/*\n+ * Enable LCD and DIGITAL OUT in DSS\n+ */\n+void omap3_dss_enable(void)\n+{\n+\tstruct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;\n+\tu32 l = 0;\n+\n+\tl = readl(&dispc->control);\n+\tl |= DISPC_ENABLE;\n+\twritel(l, &dispc->control);\n+}\n", "prefixes": [ "U-Boot", "v4" ] }