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GET /api/patches/1104082/?format=api
{ "id": 1104082, "url": "http://patchwork.ozlabs.org/api/patches/1104082/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190523122327.37264-7-Zhiqiang.Hou@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190523122327.37264-7-Zhiqiang.Hou@nxp.com>", "list_archive_url": null, "date": "2019-05-23T12:22:23", "name": "[U-Boot,PATCHv2,6/8] dm: pci: add Freescale PowerPC PCIe driver", "commit_ref": null, "pull_url": null, "state": "awaiting-upstream", "archived": false, "hash": "442751a54e189b28308a3b49f6fa80e104c91b98", "submitter": { "id": 67929, "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api", "name": "Z.Q. Hou", "email": "zhiqiang.hou@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190523122327.37264-7-Zhiqiang.Hou@nxp.com/mbox/", "series": [ { "id": 109483, "url": "http://patchwork.ozlabs.org/api/series/109483/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=109483", "date": "2019-05-23T12:21:57", "name": "dm: pci: add Freescale PowerPC PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/109483/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1104082/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1104082/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"S/38uOOF\";\n\tdkim-atps=neutral", "spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; " ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 458pbp5F0Xz9s55\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 23 May 2019 22:24:54 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid E8313C21EF1; Thu, 23 May 2019 12:23:13 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id A0846C21E50;\n\tThu, 23 May 2019 12:22:36 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid BE27BC21E3E; Thu, 23 May 2019 12:22:28 +0000 (UTC)", "from EUR03-DB5-obe.outbound.protection.outlook.com\n\t(mail-eopbgr40060.outbound.protection.outlook.com [40.107.4.60])\n\tby lists.denx.de (Postfix) with ESMTPS id AB974C21EC8\n\tfor <u-boot@lists.denx.de>; Thu, 23 May 2019 12:22:24 +0000 (UTC)", "from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.3.19) by\n\tAM6PR04MB5701.eurprd04.prod.outlook.com (20.179.1.75) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1922.16; Thu, 23 May 2019 12:22:23 +0000", "from AM6PR04MB5781.eurprd04.prod.outlook.com\n\t([fe80::6491:59e7:6b25:2993]) by\n\tAM6PR04MB5781.eurprd04.prod.outlook.com\n\t([fe80::6491:59e7:6b25:2993%7]) with mapi id 15.20.1922.013;\n\tThu, 23 May 2019 12:22:23 +0000" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=SPF_HELO_PASS, T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=h8LNhdBCcMXrZ+4EjhB7xpm39/3rzI/ryZ0Sd4I1/0k=;\n\tb=S/38uOOF8RZlHHOB86AMuoxEl4bV/0o6phGd70JsQHccvJuoY1I03+iZUGd0VD/JIgF8a6N9LEhPFCL3facHa1q9nqWg5i4uNlxkJprtlaydzdgLNVeMjuge8Vgo+SqO585S4gC22I+DSMleT4Gd455JeJ1Aht7c7eEL/mU+LGc=", "From": "\"Z.q. Hou\" <zhiqiang.hou@nxp.com>", "To": "\"u-boot@lists.denx.de\" <u-boot@lists.denx.de>, Prabhakar Kushwaha\n\t<prabhakar.kushwaha@nxp.com>, \"wd@denx.de\" <wd@denx.de>, Shengzhou Liu\n\t<shengzhou.liu@nxp.com>, \"bmeng.cn@gmail.com\" <bmeng.cn@gmail.com>,\n\tJagdish\n\tGediya <jagdish.gediya@nxp.com>, \"sjg@chromium.org\" <sjg@chromium.org>,\n\t\"ley.foon.tan@intel.com\" <ley.foon.tan@intel.com>,\n\t\"sr@denx.de\" <sr@denx.de>", "Thread-Topic": "[PATCHv2 6/8] dm: pci: add Freescale PowerPC PCIe driver", "Thread-Index": "AQHVEWIsAU8kYZd3DUeQll6M25Pbxw==", "Date": "Thu, 23 May 2019 12:22:23 +0000", "Message-ID": "<20190523122327.37264-7-Zhiqiang.Hou@nxp.com>", "References": "<20190523122327.37264-1-Zhiqiang.Hou@nxp.com>", "In-Reply-To": "<20190523122327.37264-1-Zhiqiang.Hou@nxp.com>", "Accept-Language": "zh-CN, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "HK2PR06CA0017.apcprd06.prod.outlook.com\n\t(2603:1096:202:2e::29) To AM6PR04MB5781.eurprd04.prod.outlook.com\n\t(2603:10a6:20b:ad::19)", "authentication-results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"S/38uOOF\";\n\tdkim-atps=neutral", "spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; " ], "x-ms-exchange-messagesentrepresentingtype": "1", "x-mailer": "git-send-email 2.17.1", "x-originating-ip": "[119.31.174.73]", "x-ms-publictraffictype": "Email", "x-ms-office365-filtering-correlation-id": "5b9c2ef6-7d23-4193-c480-08d6df794ef0", "x-ms-office365-filtering-ht": "Tenant", "x-microsoft-antispam": "BCL:0; PCL:0;\n\tRULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600141)(711020)(4605104)(4618075)(2017052603328)(7193020);\n\tSRVR:AM6PR04MB5701; ", "x-ms-traffictypediagnostic": "AM6PR04MB5701:", "x-microsoft-antispam-prvs": "<AM6PR04MB5701A6B73E880B47A462AB2B84010@AM6PR04MB5701.eurprd04.prod.outlook.com>", "x-ms-oob-tlc-oobclassifiers": "OLM:40;", "x-forefront-prvs": "00462943DE", "x-forefront-antispam-report": "SFV:NSPM;\n\tSFS:(10009020)(39860400002)(396003)(346002)(376002)(366004)(136003)(199004)(189003)(256004)(478600001)(486006)(305945005)(446003)(66446008)(66556008)(64756008)(66476007)(1076003)(66946007)(73956011)(6506007)(386003)(36756003)(14454004)(476003)(2616005)(11346002)(7736002)(52116002)(76176011)(186003)(68736007)(102836004)(30864003)(5660300002)(71200400001)(71190400001)(316002)(6512007)(6486002)(6436002)(53946003)(26005)(2501003)(3846002)(6116002)(53936002)(110136005)(25786009)(2201001)(54906003)(66066001)(99286004)(8676002)(8936002)(50226002)(81156014)(81166006)(14444005)(2906002)(86362001)(4326008)(579004);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5701;\n\tH:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; A:1; MX:1; ", "received-spf": "None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)", "x-ms-exchange-senderadcheck": "1", "x-microsoft-antispam-message-info": "TA85KZdBHlzhzoiZ6Z9l1DhLbG37cqhd/KzBpZnTPvx5FhZssjZ/StHzUmfEGyKDejnXsE0fw5TF77gOQXS92CPfoa55QqAAVfAmUDj0jVjPhQsdPOWbYIsB9ZOmtCDIxHjkxS/ItoLL/gHWyhC92w3E4M+4fIG5Hh8IKGt6DazDKHM4xnyP6Lu0jq1unF1P+vreCN/Y/EehJItg3CExzwKg49Hmcc4yNZAOxJ6l3+AWcUiGgw0D+D9CPne6K3PvmpeePflXz8Mu0yfnXDO495QaJpXYVBLdrRr9uoS17t2RUVMpfLYrxhMF/wIA1Pf1vWf1T6dGHmQ3DIbU/1F5s1jwiMfVW3umOeTP5r26NgFdvUEYtHWpcd8Psuv4/8Y48hC8Nh7fsKc0f40W1s7iTnzkX37TyQO7fT/fjSwjM/0=", "MIME-Version": "1.0", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "5b9c2ef6-7d23-4193-c480-08d6df794ef0", "X-MS-Exchange-CrossTenant-originalarrivaltime": "23 May 2019 12:22:23.1320\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "zhiqiang.hou@nxp.com", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM6PR04MB5701", "Cc": "\"Z.q. Hou\" <zhiqiang.hou@nxp.com>, Xiaowei Bao <xiaowei.bao@nxp.com>", "Subject": "[U-Boot] [PATCHv2 6/8] dm: pci: add Freescale PowerPC PCIe driver", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nAdd PCIe DM driver for Freescale PowerPC PCIe controllers.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n---\nV2:\n - Add more detail in the PCIE_FSL help info.\n - Sort the included header files.\n - Romve key word 'inline' from fsl_pcie_link_up().\n - Add comments for some members of structure fsl_pcie.\n - Change to determine erratums by IS_ENABLED().\n - Romve unnecessary header file including from pcie_fsl.h.\n - Add info when can't find the DT node to fixup.\n - To avoid compile error, add a null function pci_of_setup()\n when CONFIG_OF_BOARD_SETUP is not enabled. \n\n drivers/pci/Kconfig | 8 +\n drivers/pci/Makefile | 1 +\n drivers/pci/pcie_fsl.c | 611 +++++++++++++++++++++++++++++++++++\n drivers/pci/pcie_fsl.h | 57 ++++\n drivers/pci/pcie_fsl_fixup.c | 51 +++\n 5 files changed, 728 insertions(+)\n create mode 100644 drivers/pci/pcie_fsl.c\n create mode 100644 drivers/pci/pcie_fsl.h\n create mode 100644 drivers/pci/pcie_fsl_fixup.c", "diff": "diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig\r\nindex 1521885bde..e679aa1a93 100644\r\n--- a/drivers/pci/Kconfig\r\n+++ b/drivers/pci/Kconfig\r\n@@ -60,6 +60,14 @@ config PCIE_DW_MVEBU\r\n \t Armada-8K SoCs. The PCIe controller on Armada-8K is based on\r\n \t DesignWare hardware.\r\n \r\n+config PCIE_FSL\r\n+\tbool \"FSL PowerPC PCIe support\"\r\n+\tdepends on DM_PCI\r\n+\thelp\r\n+\t Say Y here if you want to enable PCIe controller support on FSL\r\n+\t PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.\r\n+\t This driver does not support SRIO_PCIE_BOOT feature.\r\n+\r\n config PCI_RCAR_GEN2\r\n \tbool \"Renesas RCar Gen2 PCIe driver\"\r\n \tdepends on DM_PCI\r\ndiff --git a/drivers/pci/Makefile b/drivers/pci/Makefile\r\nindex 4923641895..d984848266 100644\r\n--- a/drivers/pci/Makefile\r\n+++ b/drivers/pci/Makefile\r\n@@ -30,6 +30,7 @@ obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o\r\n obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o\r\n obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o\r\n obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o\r\n+obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o\r\n obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o\r\n obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o\r\n obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o\r\ndiff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c\r\nnew file mode 100644\r\nindex 0000000000..bfb207e788\r\n--- /dev/null\r\n+++ b/drivers/pci/pcie_fsl.c\r\n@@ -0,0 +1,611 @@\r\n+// SPDX-License-Identifier: GPL-2.0+ OR X11\r\n+/*\r\n+ * Copyright 2019 NXP\r\n+ * Copyright 2007-2012 Freescale Semiconductor, Inc.\r\n+ *\r\n+ * PCIe DM U-Boot driver for Freescale PowerPC SoCs\r\n+ * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\r\n+ */\r\n+\r\n+#include <common.h>\r\n+#include <dm.h>\r\n+#include <malloc.h>\r\n+#include <mapmem.h>\r\n+#include <pci.h>\r\n+#include <asm/fsl_pci.h>\r\n+#include <asm/fsl_serdes.h>\r\n+#include <asm/io.h>\r\n+#include \"pcie_fsl.h\"\r\n+\r\n+LIST_HEAD(fsl_pcie_list);\r\n+\r\n+static int fsl_pcie_link_up(struct fsl_pcie *pcie);\r\n+\r\n+static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)\r\n+{\r\n+\tstruct udevice *bus = pcie->bus;\r\n+\r\n+\tif (!pcie->enabled)\r\n+\t\treturn -ENXIO;\r\n+\r\n+\tif (PCI_BUS(bdf) < bus->seq)\r\n+\t\treturn -EINVAL;\r\n+\r\n+\tif (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))\r\n+\t\treturn -EINVAL;\r\n+\r\n+\tif (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))\r\n+\t\treturn -EINVAL;\r\n+\r\n+\tif (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))\r\n+\t\treturn -EINVAL;\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf,\r\n+\t\t\t\tuint offset, ulong *valuep,\r\n+\t\t\t\tenum pci_size_t size)\r\n+{\r\n+\tstruct fsl_pcie *pcie = dev_get_priv(bus);\r\n+\tccsr_fsl_pci_t *regs = pcie->regs;\r\n+\tu32 val;\r\n+\r\n+\tif (fsl_pcie_addr_valid(pcie, bdf)) {\r\n+\t\t*valuep = pci_get_ff(size);\r\n+\t\treturn 0;\r\n+\t}\r\n+\r\n+\tbdf = bdf - PCI_BDF(bus->seq, 0, 0);\r\n+\tval = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;\r\n+\tout_be32(®s->cfg_addr, val);\r\n+\r\n+\tsync();\r\n+\r\n+\tswitch (size) {\r\n+\tcase PCI_SIZE_8:\r\n+\t\t*valuep = in_8((u8 *)®s->cfg_data + (offset & 3));\r\n+\t\tbreak;\r\n+\tcase PCI_SIZE_16:\r\n+\t\t*valuep = in_le16((u16 *)((u8 *)®s->cfg_data +\r\n+\t\t\t (offset & 2)));\r\n+\t\tbreak;\r\n+\tcase PCI_SIZE_32:\r\n+\t\t*valuep = in_le32(®s->cfg_data);\r\n+\t\tbreak;\r\n+\t}\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,\r\n+\t\t\t\t uint offset, ulong value,\r\n+\t\t\t\t enum pci_size_t size)\r\n+{\r\n+\tstruct fsl_pcie *pcie = dev_get_priv(bus);\r\n+\tccsr_fsl_pci_t *regs = pcie->regs;\r\n+\tu32 val;\r\n+\tu8 val_8;\r\n+\tu16 val_16;\r\n+\tu32 val_32;\r\n+\r\n+\tif (fsl_pcie_addr_valid(pcie, bdf))\r\n+\t\treturn 0;\r\n+\r\n+\tbdf = bdf - PCI_BDF(bus->seq, 0, 0);\r\n+\tval = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;\r\n+\tout_be32(®s->cfg_addr, val);\r\n+\r\n+\tsync();\r\n+\r\n+\tswitch (size) {\r\n+\tcase PCI_SIZE_8:\r\n+\t\tval_8 = value;\r\n+\t\tout_8((u8 *)®s->cfg_data + (offset & 3), val_8);\r\n+\t\tbreak;\r\n+\tcase PCI_SIZE_16:\r\n+\t\tval_16 = value;\r\n+\t\tout_le16((u16 *)((u8 *)®s->cfg_data + (offset & 2)), val_16);\r\n+\t\tbreak;\r\n+\tcase PCI_SIZE_32:\r\n+\t\tval_32 = value;\r\n+\t\tout_le32(®s->cfg_data, val_32);\r\n+\t\tbreak;\r\n+\t}\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,\r\n+\t\t\t\t ulong *valuep, enum pci_size_t size)\r\n+{\r\n+\tint ret;\r\n+\tstruct udevice *bus = pcie->bus;\r\n+\r\n+\tret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),\r\n+\t\t\t\t offset, valuep, size);\r\n+\r\n+\treturn ret;\r\n+}\r\n+\r\n+static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,\r\n+\t\t\t\t ulong value, enum pci_size_t size)\r\n+{\r\n+\tstruct udevice *bus = pcie->bus;\r\n+\r\n+\treturn fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),\r\n+\t\t\t\t offset, value, size);\r\n+}\r\n+\r\n+static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,\r\n+\t\t\t\t\t u8 *valuep)\r\n+{\r\n+\tulong val;\r\n+\tint ret;\r\n+\r\n+\tret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);\r\n+\t*valuep = val;\r\n+\r\n+\treturn ret;\r\n+}\r\n+\r\n+static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,\r\n+\t\t\t\t\t u16 *valuep)\r\n+{\r\n+\tulong val;\r\n+\tint ret;\r\n+\r\n+\tret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);\r\n+\t*valuep = val;\r\n+\r\n+\treturn ret;\r\n+}\r\n+\r\n+static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,\r\n+\t\t\t\t\t u32 *valuep)\r\n+{\r\n+\tulong val;\r\n+\tint ret;\r\n+\r\n+\tret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);\r\n+\t*valuep = val;\r\n+\r\n+\treturn ret;\r\n+}\r\n+\r\n+static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,\r\n+\t\t\t\t\t u8 value)\r\n+{\r\n+\treturn fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);\r\n+}\r\n+\r\n+static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,\r\n+\t\t\t\t\t u16 value)\r\n+{\r\n+\treturn fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);\r\n+}\r\n+\r\n+static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,\r\n+\t\t\t\t\t u32 value)\r\n+{\r\n+\treturn fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);\r\n+}\r\n+\r\n+static int fsl_pcie_link_up(struct fsl_pcie *pcie)\r\n+{\r\n+\tccsr_fsl_pci_t *regs = pcie->regs;\r\n+\tu16 ltssm;\r\n+\r\n+\tif (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {\r\n+\t\tltssm = (in_be32(®s->pex_csr0)\r\n+\t\t\t& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;\r\n+\t\treturn ltssm == LTSSM_L0_REV3;\r\n+\t}\r\n+\r\n+\tfsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);\r\n+\r\n+\treturn ltssm == LTSSM_L0;\r\n+}\r\n+\r\n+static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)\r\n+{\r\n+\tu8 header_type;\r\n+\r\n+\tfsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);\r\n+\r\n+\treturn (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;\r\n+}\r\n+\r\n+static int fsl_pcie_setup_law(struct fsl_pcie *pcie)\r\n+{\r\n+\tstruct pci_region *io, *mem, *pref;\r\n+\r\n+\tpci_get_regions(pcie->bus, &io, &mem, &pref);\r\n+\r\n+\tif (mem)\r\n+\t\tset_next_law(mem->phys_start,\r\n+\t\t\t law_size_bits(mem->size),\r\n+\t\t\t pcie->law_trgt_if);\r\n+\r\n+\tif (io)\r\n+\t\tset_next_law(io->phys_start,\r\n+\t\t\t law_size_bits(io->size),\r\n+\t\t\t pcie->law_trgt_if);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static void fsl_pcie_config_ready(struct fsl_pcie *pcie)\r\n+{\r\n+\tccsr_fsl_pci_t *regs = pcie->regs;\r\n+\r\n+\tif (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {\r\n+\t\tsetbits_be32(®s->config, FSL_PCIE_V3_CFG_RDY);\r\n+\t\treturn;\r\n+\t}\r\n+\r\n+\tfsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);\r\n+}\r\n+\r\n+static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,\r\n+\t\t\t\t int type, u64 phys, u64 bus_addr,\r\n+\t\t\t\t pci_size_t size)\r\n+{\r\n+\tccsr_fsl_pci_t *regs = pcie->regs;\r\n+\tpot_t *po = ®s->pot[idx];\r\n+\tu32 war, sz;\r\n+\r\n+\tif (idx < 0)\r\n+\t\treturn -EINVAL;\r\n+\r\n+\tout_be32(&po->powbar, phys >> 12);\r\n+\tout_be32(&po->potar, bus_addr >> 12);\r\n+#ifdef CONFIG_SYS_PCI_64BIT\r\n+\tout_be32(&po->potear, bus_addr >> 44);\r\n+#else\r\n+\tout_be32(&po->potear, 0);\r\n+#endif\r\n+\r\n+\tsz = (__ilog2_u64((u64)size) - 1);\r\n+\twar = POWAR_EN | sz;\r\n+\r\n+\tif (type == PCI_REGION_IO)\r\n+\t\twar |= POWAR_IO_READ | POWAR_IO_WRITE;\r\n+\telse\r\n+\t\twar |= POWAR_MEM_READ | POWAR_MEM_WRITE;\r\n+\r\n+\tout_be32(&po->powar, war);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,\r\n+\t\t\t\t bool pf, u64 phys, u64 bus_addr,\r\n+\t\t\t\t pci_size_t size)\r\n+{\r\n+\tccsr_fsl_pci_t *regs = pcie->regs;\r\n+\tpit_t *pi = ®s->pit[idx];\r\n+\tu32 sz = (__ilog2_u64(size) - 1);\r\n+\tu32 flag = PIWAR_LOCAL;\r\n+\r\n+\tif (idx < 0)\r\n+\t\treturn -EINVAL;\r\n+\r\n+\tout_be32(&pi->pitar, phys >> 12);\r\n+\tout_be32(&pi->piwbar, bus_addr >> 12);\r\n+\r\n+#ifdef CONFIG_SYS_PCI_64BIT\r\n+\tout_be32(&pi->piwbear, bus_addr >> 44);\r\n+#else\r\n+\tout_be32(&pi->piwbear, 0);\r\n+#endif\r\n+\r\n+\tif (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434))\r\n+\t\tflag = 0;\r\n+\r\n+\tflag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;\r\n+\tif (pf)\r\n+\t\tflag |= PIWAR_PF;\r\n+\tout_be32(&pi->piwar, flag | sz);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)\r\n+{\r\n+\tstruct pci_region *io, *mem, *pref;\r\n+\tint idx = 1; /* skip 0 */\r\n+\r\n+\tpci_get_regions(pcie->bus, &io, &mem, &pref);\r\n+\r\n+\tif (io)\r\n+\t\t/* ATU : OUTBOUND : IO */\r\n+\t\tfsl_pcie_setup_outbound_win(pcie, idx++,\r\n+\t\t\t\t\t PCI_REGION_IO,\r\n+\t\t\t\t\t io->phys_start,\r\n+\t\t\t\t\t io->bus_start,\r\n+\t\t\t\t\t io->size);\r\n+\r\n+\tif (mem)\r\n+\t\t/* ATU : OUTBOUND : MEM */\r\n+\t\tfsl_pcie_setup_outbound_win(pcie, idx++,\r\n+\t\t\t\t\t PCI_REGION_MEM,\r\n+\t\t\t\t\t mem->phys_start,\r\n+\t\t\t\t\t mem->bus_start,\r\n+\t\t\t\t\t mem->size);\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)\r\n+{\r\n+\tphys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;\r\n+\tpci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;\r\n+\tu64 sz = min((u64)gd->ram_size, (1ull << 32));\r\n+\tpci_size_t pci_sz;\r\n+\tint idx;\r\n+\r\n+\tif (pcie->block_rev >= PEX_IP_BLK_REV_2_2)\r\n+\t\tidx = 2;\r\n+\telse\r\n+\t\tidx = 3;\r\n+\r\n+\tpci_sz = 1ull << __ilog2_u64(sz);\r\n+\r\n+\tdev_dbg(pcie->bus, \"R0 bus_start: %llx phys_start: %llx size: %llx\\n\",\r\n+\t\t(u64)bus_start, (u64)phys_start, (u64)sz);\r\n+\r\n+\t/* if we aren't an exact power of two match, pci_sz is smaller\r\n+\t * round it up to the next power of two. We report the actual\r\n+\t * size to pci region tracking.\r\n+\t */\r\n+\tif (pci_sz != sz)\r\n+\t\tsz = 2ull << __ilog2_u64(sz);\r\n+\r\n+\tfsl_pcie_setup_inbound_win(pcie, idx--, true,\r\n+\t\t\t\t CONFIG_SYS_PCI_MEMORY_PHYS,\r\n+\t\t\t\t CONFIG_SYS_PCI_MEMORY_BUS, sz);\r\n+#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)\r\n+\t/*\r\n+\t * On 64-bit capable systems, set up a mapping for all of DRAM\r\n+\t * in high pci address space.\r\n+\t */\r\n+\tpci_sz = 1ull << __ilog2_u64(gd->ram_size);\r\n+\t/* round up to the next largest power of two */\r\n+\tif (gd->ram_size > pci_sz)\r\n+\t\tpci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);\r\n+\r\n+\tdev_dbg(pcie->bus, \"R64 bus_start: %llx phys_start: %llx size: %llx\\n\",\r\n+\t\t(u64)CONFIG_SYS_PCI64_MEMORY_BUS,\r\n+\t\t(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);\r\n+\r\n+\tfsl_pcie_setup_inbound_win(pcie, idx--, true,\r\n+\t\t\t\t CONFIG_SYS_PCI_MEMORY_PHYS,\r\n+\t\t\t\t CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);\r\n+#endif\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)\r\n+{\r\n+\tfsl_pcie_setup_outbound_wins(pcie);\r\n+\tfsl_pcie_setup_inbound_wins(pcie);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_init_port(struct fsl_pcie *pcie)\r\n+{\r\n+\tccsr_fsl_pci_t *regs = pcie->regs;\r\n+\tu32 val_32;\r\n+\tu16 val_16;\r\n+\r\n+\tfsl_pcie_init_atmu(pcie);\r\n+\r\n+\tif (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) {\r\n+\t\tval_32 = 0;\r\n+\t\tfsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);\r\n+\t\tval_32 &= ~0x03;\r\n+\t\tfsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);\r\n+\t\tudelay(1);\r\n+\t}\r\n+\r\n+\tif (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) {\r\n+\t\tu16 ltssm;\r\n+\t\tint i;\r\n+\r\n+\t\tif (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {\r\n+\t\t\t/* assert PCIe reset */\r\n+\t\t\tsetbits_be32(®s->pdb_stat, 0x08000000);\r\n+\t\t\t(void)in_be32(®s->pdb_stat);\r\n+\t\t\tudelay(1000);\r\n+\t\t\t/* clear PCIe reset */\r\n+\t\t\tclrbits_be32(®s->pdb_stat, 0x08000000);\r\n+\t\t\tasm(\"sync;isync\");\r\n+\t\t\tfor (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)\r\n+\t\t\t\tudelay(1000);\r\n+\t\t} else {\r\n+\t\t\tfsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);\r\n+\t\t\tif (ltssm == 1) {\r\n+\t\t\t\t/* assert PCIe reset */\r\n+\t\t\t\tsetbits_be32(®s->pdb_stat, 0x08000000);\r\n+\t\t\t\t(void)in_be32(®s->pdb_stat);\r\n+\t\t\t\tudelay(100);\r\n+\t\t\t\t/* clear PCIe reset */\r\n+\t\t\t\tclrbits_be32(®s->pdb_stat, 0x08000000);\r\n+\t\t\t\tasm(\"sync;isync\");\r\n+\t\t\t\tfor (i = 0; i < 100 &&\r\n+\t\t\t\t !fsl_pcie_link_up(pcie); i++)\r\n+\t\t\t\t\tudelay(1000);\r\n+\t\t\t}\r\n+\t\t}\r\n+\t}\r\n+\r\n+\tif (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) &&\r\n+\t !fsl_pcie_link_up(pcie)) {\r\n+\t\tserdes_corenet_t *srds_regs;\r\n+\r\n+\t\tsrds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;\r\n+\t\tval_32 = in_be32(&srds_regs->srdspccr0);\r\n+\r\n+\t\tif ((val_32 >> 28) == 3) {\r\n+\t\t\tint i;\r\n+\r\n+\t\t\tout_be32(&srds_regs->srdspccr0, 2 << 28);\r\n+\t\t\tsetbits_be32(®s->pdb_stat, 0x08000000);\r\n+\t\t\tin_be32(®s->pdb_stat);\r\n+\t\t\tudelay(100);\r\n+\t\t\tclrbits_be32(®s->pdb_stat, 0x08000000);\r\n+\t\t\tasm(\"sync;isync\");\r\n+\t\t\tfor (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)\r\n+\t\t\t\tudelay(1000);\r\n+\t\t}\r\n+\t}\r\n+\r\n+\t/*\r\n+\t * The Read-Only Write Enable bit defaults to 1 instead of 0.\r\n+\t * Set to 0 to protect the read-only registers.\r\n+\t */\r\n+\tif (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815))\r\n+\t\tclrbits_be32(®s->dbi_ro_wr_en, 0x01);\r\n+\r\n+\t/*\r\n+\t * Enable All Error Interrupts except\r\n+\t * - Master abort (pci)\r\n+\t * - Master PERR (pci)\r\n+\t * - ICCA (PCIe)\r\n+\t */\r\n+\tout_be32(®s->peer, ~0x20140);\r\n+\r\n+\t/* set URR, FER, NFER (but not CER) */\r\n+\tfsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);\r\n+\tval_32 |= 0xf000e;\r\n+\tfsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);\r\n+\r\n+\t/* Clear all error indications */\r\n+\tout_be32(®s->pme_msg_det, 0xffffffff);\r\n+\tout_be32(®s->pme_msg_int_en, 0xffffffff);\r\n+\tout_be32(®s->pedr, 0xffffffff);\r\n+\r\n+\tfsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);\r\n+\tif (val_16)\r\n+\t\tfsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);\r\n+\r\n+\tfsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);\r\n+\tif (val_16)\r\n+\t\tfsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)\r\n+{\r\n+\tccsr_fsl_pci_t *regs = pcie->regs;\r\n+\tu32 val;\r\n+\r\n+\tsetbits_be32(®s->dbi_ro_wr_en, 0x01);\r\n+\tfsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);\r\n+\tval &= 0xff;\r\n+\tval |= PCI_CLASS_BRIDGE_PCI << 16;\r\n+\tfsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);\r\n+\tclrbits_be32(®s->dbi_ro_wr_en, 0x01);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_init_rc(struct fsl_pcie *pcie)\r\n+{\r\n+\treturn fsl_pcie_fixup_classcode(pcie);\r\n+}\r\n+\r\n+static int fsl_pcie_init_ep(struct fsl_pcie *pcie)\r\n+{\r\n+\tfsl_pcie_config_ready(pcie);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_probe(struct udevice *dev)\r\n+{\r\n+\tstruct fsl_pcie *pcie = dev_get_priv(dev);\r\n+\tccsr_fsl_pci_t *regs = pcie->regs;\r\n+\tu16 val_16;\r\n+\r\n+\tpcie->bus = dev;\r\n+\tpcie->block_rev = in_be32(®s->block_rev1);\r\n+\r\n+\tlist_add(&pcie->list, &fsl_pcie_list);\r\n+\tpcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);\r\n+\tif (!pcie->enabled) {\r\n+\t\tprintf(\"PCIe%d: %s disabled\\n\", pcie->idx, dev->name);\r\n+\t\treturn 0;\r\n+\t}\r\n+\r\n+\tfsl_pcie_setup_law(pcie);\r\n+\r\n+\tpcie->mode = fsl_pcie_is_agent(pcie);\r\n+\r\n+\tfsl_pcie_init_port(pcie);\r\n+\r\n+\tprintf(\"PCIe%d: %s \", pcie->idx, dev->name);\r\n+\r\n+\tif (pcie->mode) {\r\n+\t\tprintf(\"Endpoint\");\r\n+\t\tfsl_pcie_init_ep(pcie);\r\n+\t} else {\r\n+\t\tprintf(\"Root Complex\");\r\n+\t\tfsl_pcie_init_rc(pcie);\r\n+\t}\r\n+\r\n+\tif (!fsl_pcie_link_up(pcie)) {\r\n+\t\tprintf(\": %s\\n\", pcie->mode ? \"undetermined link\" : \"no link\");\r\n+\t\treturn 0;\r\n+\t}\r\n+\r\n+\tfsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);\r\n+\tprintf(\": x%d gen%d\\n\", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)\r\n+{\r\n+\tstruct fsl_pcie *pcie = dev_get_priv(dev);\r\n+\tint ret;\r\n+\r\n+\tpcie->regs = dev_remap_addr(dev);\r\n+\tif (!pcie->regs) {\r\n+\t\tpr_err(\"\\\"reg\\\" resource not found\\n\");\r\n+\t\treturn -EINVAL;\r\n+\t}\r\n+\r\n+\tret = dev_read_u32(dev, \"law_trgt_if\", &pcie->law_trgt_if);\r\n+\tif (ret < 0) {\r\n+\t\tpr_err(\"\\\"law_trgt_if\\\" not found\\n\");\r\n+\t\treturn ret;\r\n+\t}\r\n+\r\n+\tpcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000;\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static const struct dm_pci_ops fsl_pcie_ops = {\r\n+\t.read_config\t= fsl_pcie_read_config,\r\n+\t.write_config\t= fsl_pcie_write_config,\r\n+};\r\n+\r\n+static const struct udevice_id fsl_pcie_ids[] = {\r\n+\t{ .compatible = \"fsl,pcie-t2080\" },\r\n+\t{ }\r\n+};\r\n+\r\n+U_BOOT_DRIVER(fsl_pcie) = {\r\n+\t.name = \"fsl_pcie\",\r\n+\t.id = UCLASS_PCI,\r\n+\t.of_match = fsl_pcie_ids,\r\n+\t.ops = &fsl_pcie_ops,\r\n+\t.ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,\r\n+\t.probe = fsl_pcie_probe,\r\n+\t.priv_auto_alloc_size = sizeof(struct fsl_pcie),\r\n+};\r\ndiff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h\r\nnew file mode 100644\r\nindex 0000000000..ce2b1afb4d\r\n--- /dev/null\r\n+++ b/drivers/pci/pcie_fsl.h\r\n@@ -0,0 +1,57 @@\r\n+/* SPDX-License-Identifier: GPL-2.0+ */\r\n+/*\r\n+ * Copyright 2019 NXP\r\n+ * Copyright 2007-2012 Freescale Semiconductor, Inc.\r\n+ *\r\n+ * PCIe DM U-Boot driver for Freescale PowerPC SoCs\r\n+ * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\r\n+ */\r\n+\r\n+#ifndef _PCIE_FSL_H_\r\n+#define _PCIE_FSL_H_\r\n+\r\n+#ifdef CONFIG_SYS_FSL_PCI_VER_3_X\r\n+#define FSL_PCIE_CAP_ID\t\t\t0x70\r\n+#else\r\n+#define FSL_PCIE_CAP_ID\t\t\t0x4c\r\n+#endif\r\n+/* PCIe Device Control Register */\r\n+#define PCI_DCR\t\t\t\t(FSL_PCIE_CAP_ID + 0x08)\r\n+/* PCIe Device Status Register */\r\n+#define PCI_DSR\t\t\t\t(FSL_PCIE_CAP_ID + 0x0a)\r\n+/* PCIe Link Control Register */\r\n+#define PCI_LCR\t\t\t\t(FSL_PCIE_CAP_ID + 0x10)\r\n+/* PCIe Link Status Register */\r\n+#define PCI_LSR\t\t\t\t(FSL_PCIE_CAP_ID + 0x12)\r\n+\r\n+#ifndef CONFIG_SYS_PCI_MEMORY_BUS\r\n+#define CONFIG_SYS_PCI_MEMORY_BUS\t0\r\n+#endif\r\n+\r\n+#ifndef CONFIG_SYS_PCI_MEMORY_PHYS\r\n+#define CONFIG_SYS_PCI_MEMORY_PHYS\t0\r\n+#endif\r\n+\r\n+#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)\r\n+#define CONFIG_SYS_PCI64_MEMORY_BUS\t(64ull * 1024 * 1024 * 1024)\r\n+#endif\r\n+\r\n+#define PEX_CSR0_LTSSM_MASK\t\t0xFC\r\n+#define PEX_CSR0_LTSSM_SHIFT\t\t2\r\n+#define LTSSM_L0_REV3\t\t\t0x11\r\n+#define LTSSM_L0\t\t\t0x16\r\n+\r\n+struct fsl_pcie {\r\n+\tint idx;\r\n+\tstruct udevice *bus;\r\n+\tvoid __iomem *regs;\r\n+\tu32 law_trgt_if;\t\t/* LAW target ID */\r\n+\tu32 block_rev;\t\t\t/* IP block revision */\r\n+\tbool mode;\t\t\t/* RC&EP mode flag */\r\n+\tbool enabled;\t\t\t/* Enable status */\r\n+\tstruct list_head list;\r\n+};\r\n+\r\n+extern struct list_head fsl_pcie_list;\r\n+\r\n+#endif /* _PCIE_FSL_H_ */\r\ndiff --git a/drivers/pci/pcie_fsl_fixup.c b/drivers/pci/pcie_fsl_fixup.c\r\nnew file mode 100644\r\nindex 0000000000..1a17436ac0\r\n--- /dev/null\r\n+++ b/drivers/pci/pcie_fsl_fixup.c\r\n@@ -0,0 +1,51 @@\r\n+// SPDX-License-Identifier: GPL-2.0+ OR X11\r\n+/*\r\n+ * Copyright 2019 NXP\r\n+ * Copyright 2007-2012 Freescale Semiconductor, Inc.\r\n+ *\r\n+ * PCIe Kernel DT fixup of DM U-Boot driver for Freescale PowerPC SoCs\r\n+ * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\r\n+ */\r\n+\r\n+#include <common.h>\r\n+#ifdef CONFIG_OF_BOARD_SETUP\r\n+#include <dm.h>\r\n+#include <fdt_support.h>\r\n+#include <asm/fsl_pci.h>\r\n+#include <linux/libfdt.h>\r\n+#include \"pcie_fsl.h\"\r\n+\r\n+static void ft_fsl_pcie_setup(void *blob, struct fsl_pcie *pcie)\r\n+{\r\n+\tstruct pci_controller *hose = dev_get_uclass_priv(pcie->bus);\r\n+\tfdt_addr_t regs_addr;\r\n+\tint off;\r\n+\r\n+\tregs_addr = dev_read_addr(pcie->bus);\r\n+\toff = fdt_node_offset_by_compat_reg(blob, FSL_PCIE_COMPAT, regs_addr);\r\n+\tif (off < 0) {\r\n+\t\tprintf(\"%s: Fail to find PCIe node@0x%pa\\n\",\r\n+\t\t FSL_PCIE_COMPAT, ®s_addr);\r\n+\t\treturn;\r\n+\t}\r\n+\r\n+\tif (!hose || !pcie->enabled)\r\n+\t\tfdt_del_node(blob, off);\r\n+\telse\r\n+\t\tfdt_pci_dma_ranges(blob, off, hose);\r\n+}\r\n+\r\n+/* Fixup Kernel DT for PCIe */\r\n+void pci_of_setup(void *blob, bd_t *bd)\r\n+{\r\n+\tstruct fsl_pcie *pcie;\r\n+\r\n+\tlist_for_each_entry(pcie, &fsl_pcie_list, list)\r\n+\t\tft_fsl_pcie_setup(blob, pcie);\r\n+}\r\n+\r\n+#else\r\n+void pci_of_setup(void *blob, bd_t *bd)\r\n+{\r\n+}\r\n+#endif\r\n", "prefixes": [ "U-Boot", "PATCHv2", "6/8" ] }