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GET /api/patches/110188/?format=api
{ "id": 110188, "url": "http://patchwork.ozlabs.org/api/patches/110188/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1313505185-21514-1-git-send-email-aneesh@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1313505185-21514-1-git-send-email-aneesh@ti.com>", "list_archive_url": null, "date": "2011-08-16T14:33:05", "name": "[U-Boot,v4,1/4] arm: do not force d-cache enable on all boards", "commit_ref": "cba4b1809f043bf85c806e5a4e342f62bd5ded45", "pull_url": null, "state": "accepted", "archived": false, "hash": "79e493c8e493af6d68818c49241e570ef67004d6", "submitter": { "id": 6298, "url": "http://patchwork.ozlabs.org/api/people/6298/?format=api", "name": "Aneesh V", "email": "aneesh@ti.com" }, "delegate": { "id": 1694, "url": "http://patchwork.ozlabs.org/api/users/1694/?format=api", "username": "aaribaud", "first_name": "Albert", "last_name": "ARIBAUD", "email": "albert.aribaud@free.fr" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1313505185-21514-1-git-send-email-aneesh@ti.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/110188/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/110188/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 334B8B6F82\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 17 Aug 2011 00:38:41 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 91C1128082;\n\tTue, 16 Aug 2011 16:38:39 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id cRZg6nr3yjff; Tue, 16 Aug 2011 16:38:39 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id CD0A22807C;\n\tTue, 16 Aug 2011 16:38:35 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id A787D2807C\n\tfor <u-boot@lists.denx.de>; Tue, 16 Aug 2011 16:38:33 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id xv0EYu+u+a3Y for <u-boot@lists.denx.de>;\n\tTue, 16 Aug 2011 16:38:31 +0200 (CEST)", "from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41])\n\tby theia.denx.de (Postfix) with ESMTPS id 6152A28078\n\tfor <u-boot@lists.denx.de>; Tue, 16 Aug 2011 16:38:30 +0200 (CEST)", "from dbdp20.itg.ti.com ([172.24.170.38])\n\tby bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id p7GEcIlC010682\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO);\n\tTue, 16 Aug 2011 09:38:20 -0500", "from dbde70.ent.ti.com (localhost [127.0.0.1])\n\tby dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7GEcFRf019313;\n\tTue, 16 Aug 2011 20:08:16 +0530 (IST)", "from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com\n\t(172.24.170.148) with Microsoft SMTP Server id 8.3.106.1;\n\tTue, 16 Aug 2011 20:08:15 +0530", "from localhost (a0393566pc.apr.dhcp.ti.com [172.24.137.55])\tby\n\tdbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7GEc783020534;\n\tTue, 16 Aug 2011 20:08:13 +0530 (IST)" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Aneesh V <aneesh@ti.com>", "To": "<u-boot@lists.denx.de>", "Date": "Tue, 16 Aug 2011 20:03:05 +0530", "Message-ID": "<1313505185-21514-1-git-send-email-aneesh@ti.com>", "X-Mailer": "git-send-email 1.7.0.4", "In-Reply-To": "<1313073345-29773-2-git-send-email-aneesh@ti.com>", "References": "<1313073345-29773-2-git-send-email-aneesh@ti.com>", "MIME-Version": "1.0", "Cc": "santosh.shilimkar@ti.com", "Subject": "[U-Boot] [PATCH v4 1/4] arm: do not force d-cache enable on all\n\tboards", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.9", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable()\nto board_init_r(). This enables d-cache for all ARM boards.\nAs a result some of the arm boards that are not cache-ready\nare broken. Revert this change and allow platform code to\ntake the decision on d-cache enabling.\n\nAlso add some documentation for cache usage in ARM.\n\nSigned-off-by: Aneesh V <aneesh@ti.com>\n---\nV2:\n* Updated with additional guidelines in the README.\n\nV3:\n* No change\n\nV4:\n* Fix typo in README\n---\n arch/arm/lib/board.c | 8 ++----\n arch/arm/lib/cache.c | 12 +++++++++++\n doc/README.arm-caches | 51 +++++++++++++++++++++++++++++++++++++++++++++++++\n include/common.h | 1 +\n 4 files changed, 67 insertions(+), 5 deletions(-)\n create mode 100644 doc/README.arm-caches", "diff": "diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c\nindex 14a56f6..38a31d8 100644\n--- a/arch/arm/lib/board.c\n+++ b/arch/arm/lib/board.c\n@@ -451,11 +451,9 @@ void board_init_r(gd_t *id, ulong dest_addr)\n \tgd->flags |= GD_FLG_RELOC;\t/* tell others: relocation done */\n \n \tmonitor_flash_len = _end_ofs;\n-\t/*\n-\t * Enable D$:\n-\t * I$, if needed, must be already enabled in start.S\n-\t */\n-\tdcache_enable();\n+\n+\t/* Enable caches */\n+\tenable_caches();\n \n \tdebug(\"monitor flash len: %08lX\\n\", monitor_flash_len);\n \tboard_init();\t/* Setup chipselects */\ndiff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c\nindex 92b61a2..b545fb7 100644\n--- a/arch/arm/lib/cache.c\n+++ b/arch/arm/lib/cache.c\n@@ -53,3 +53,15 @@ void\t__flush_dcache_all(void)\n }\n void\tflush_dcache_all(void)\n \t__attribute__((weak, alias(\"__flush_dcache_all\")));\n+\n+\n+/*\n+ * Default implementation of enable_caches()\n+ * Real implementation should be in platform code\n+ */\n+void __enable_caches(void)\n+{\n+\tputs(\"WARNING: Caches not enabled\\n\");\n+}\n+void enable_caches(void)\n+\t__attribute__((weak, alias(\"__enable_caches\")));\ndiff --git a/doc/README.arm-caches b/doc/README.arm-caches\nnew file mode 100644\nindex 0000000..cd2b458\n--- /dev/null\n+++ b/doc/README.arm-caches\n@@ -0,0 +1,51 @@\n+Disabling I-cache:\n+- Set CONFIG_SYS_ICACHE_OFF\n+\n+Disabling D-cache:\n+- Set CONFIG_SYS_DCACHE_OFF\n+\n+Enabling I-cache:\n+- Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable().\n+\n+Enabling D-cache:\n+- Make sure CONFIG_SYS_DCACHE_OFF is not set and call dcache_enable().\n+\n+Enabling Caches at System Startup:\n+- Implement enable_caches() for your platform and enable the I-cache and\n+ D-cache from this function. This function is called immediately\n+ after relocation.\n+\n+Guidelines for Working with D-cache:\n+\n+Memory to Peripheral DMA:\n+- Flush the buffer after the MPU writes the data and before the DMA is\n+ initiated.\n+\n+Peripheral to Memory DMA:\n+- Invalidate the buffer before starting the DMA. In case there are any dirty\n+ lines from the DMA buffer in the cache, subsequent cache-line replacements\n+ may corrupt the buffer in memory while the DMA is still going on. Cache-line\n+ replacement can happen if the CPU tries to bring some other memory locations\n+ into the cache while the DMA is going on.\n+- Invalidate the buffer after the DMA is complete and before the MPU reads\n+ it. This may be needed in addition to the invalidation before the DMA\n+ mentioned above, because in some processors memory contents can spontaneously\n+ come to the cache due to speculative memory access by the CPU. If this\n+ happens with the DMA buffer while DMA is going on we have a coherency problem.\n+\n+Buffer Requirements:\n+- Any buffer that is invalidated(that is, typically the peripheral to\n+ memory DMA buffer) should be aligned to cache-line boundary both at\n+ at the beginning and at the end of the buffer.\n+- If the buffer is not cache-line aligned invalidation will be restricted\n+ to the aligned part. That is, one cache-line at the respective boundary\n+ may be left out while doing invalidation.\n+\n+Cleanup Before Linux:\n+- cleanup_before_linux() should flush the D-cache, invalidate I-cache, and\n+ disable MMU and caches.\n+- The following sequence is advisable while disabling d-cache:\n+ 1. disable_dcache() - flushes and disables d-cache\n+ 2. invalidate_dcache_all() - invalid any entry that came to the cache\n+\tin the short period after the cache was flushed but before the\n+\tcache got disabled.\ndiff --git a/include/common.h b/include/common.h\nindex 12a1074..bd10f31 100644\n--- a/include/common.h\n+++ b/include/common.h\n@@ -616,6 +616,7 @@ ulong\tlcd_setmem (ulong);\n ulong\tvideo_setmem (ulong);\n \n /* arch/$(ARCH)/lib/cache.c */\n+void\tenable_caches(void);\n void\tflush_cache (unsigned long, unsigned long);\n void\tflush_dcache_all(void);\n void\tflush_dcache_range(unsigned long start, unsigned long stop);\n", "prefixes": [ "U-Boot", "v4", "1/4" ] }