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GET /api/patches/109618/?format=api
{ "id": 109618, "url": "http://patchwork.ozlabs.org/api/patches/109618/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1313073345-29773-5-git-send-email-aneesh@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1313073345-29773-5-git-send-email-aneesh@ti.com>", "list_archive_url": null, "date": "2011-08-11T14:35:45", "name": "[U-Boot,v3,4/4] armv7: cache: remove flush on un-aligned invalidate", "commit_ref": "cabe2878a8201441a8aa4c482acb568f9ca137f0", "pull_url": null, "state": "accepted", "archived": false, "hash": "36e8d7ff7a6bd23ef65848ba4931646869ac353b", "submitter": { "id": 6298, "url": "http://patchwork.ozlabs.org/api/people/6298/?format=api", "name": "Aneesh V", "email": "aneesh@ti.com" }, "delegate": { "id": 1694, "url": "http://patchwork.ozlabs.org/api/users/1694/?format=api", "username": "aaribaud", "first_name": "Albert", "last_name": "ARIBAUD", "email": "albert.aribaud@free.fr" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1313073345-29773-5-git-send-email-aneesh@ti.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/109618/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/109618/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id B94FBB6F80\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 12 Aug 2011 00:41:15 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id CBAD2281EF;\n\tThu, 11 Aug 2011 16:41:09 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id WX04QAtpu1kI; Thu, 11 Aug 2011 16:41:09 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id B8FBC281FB;\n\tThu, 11 Aug 2011 16:40:58 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id B4CDD2819B\n\tfor <u-boot@lists.denx.de>; Thu, 11 Aug 2011 16:40:49 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id pfBziCE9TA21 for <u-boot@lists.denx.de>;\n\tThu, 11 Aug 2011 16:40:49 +0200 (CEST)", "from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40])\n\tby theia.denx.de (Postfix) with ESMTPS id 01A6D281B9\n\tfor <u-boot@lists.denx.de>; Thu, 11 Aug 2011 16:40:45 +0200 (CEST)", "from dbdp20.itg.ti.com ([172.24.170.38])\n\tby arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p7BEeXtT013775\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO);\n\tThu, 11 Aug 2011 09:40:35 -0500", "from dbde71.ent.ti.com (localhost [127.0.0.1])\n\tby dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7BEeVK8027043;\n\tThu, 11 Aug 2011 20:10:32 +0530 (IST)", "from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com\n\t(172.24.170.149) with Microsoft SMTP Server id 8.3.106.1;\n\tThu, 11 Aug 2011 20:10:31 +0530", "from localhost (a0393566pc.apr.dhcp.ti.com [172.24.137.55])\tby\n\tdbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7BEeVHC016170;\n\tThu, 11 Aug 2011 20:10:31 +0530 (IST)" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Aneesh V <aneesh@ti.com>", "To": "<u-boot@lists.denx.de>", "Date": "Thu, 11 Aug 2011 20:05:45 +0530", "Message-ID": "<1313073345-29773-5-git-send-email-aneesh@ti.com>", "X-Mailer": "git-send-email 1.7.0.4", "In-Reply-To": "<1312197486-31712-2-git-send-email-aneesh@ti.com>", "References": "<1312197486-31712-2-git-send-email-aneesh@ti.com>", "MIME-Version": "1.0", "Cc": "santosh.shilimkar@ti.com", "Subject": "[U-Boot] [PATCH v3 4/4] armv7: cache: remove flush on un-aligned\n\tinvalidate", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.9", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "Remove the flush of boundary cache-lines done as part\nof invalidate on a non cache-line boundary aligned\nbuffer\n\nAlso, print a warning when this situation is recognized.\n\nSigned-off-by: Aneesh V <aneesh@ti.com>\n---\nV2:\n* New in V2\nV3:\n* error notification instead of warning on un-aligned invalidate\n---\n arch/arm/cpu/armv7/cache_v7.c | 14 ++++++++------\n arch/arm/lib/cache-pl310.c | 15 +++++++++------\n 2 files changed, 17 insertions(+), 12 deletions(-)", "diff": "diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c\nindex 665f025..1b4e808 100644\n--- a/arch/arm/cpu/armv7/cache_v7.c\n+++ b/arch/arm/cpu/armv7/cache_v7.c\n@@ -181,21 +181,23 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)\n \tu32 mva;\n \n \t/*\n-\t * If start address is not aligned to cache-line flush the first\n-\t * line to prevent affecting somebody else's buffer\n+\t * If start address is not aligned to cache-line do not\n+\t * invalidate the first cache-line\n \t */\n \tif (start & (line_len - 1)) {\n-\t\tv7_dcache_clean_inval_range(start, start + 1, line_len);\n+\t\tprintf(\"ERROR: %s - start address is not aligned - 0x%08x\\n\",\n+\t\t\t__func__, start);\n \t\t/* move to next cache line */\n \t\tstart = (start + line_len - 1) & ~(line_len - 1);\n \t}\n \n \t/*\n-\t * If stop address is not aligned to cache-line flush the last\n-\t * line to prevent affecting somebody else's buffer\n+\t * If stop address is not aligned to cache-line do not\n+\t * invalidate the last cache-line\n \t */\n \tif (stop & (line_len - 1)) {\n-\t\tv7_dcache_clean_inval_range(stop, stop + 1, line_len);\n+\t\tprintf(\"ERROR: %s - stop address is not aligned - 0x%08x\\n\",\n+\t\t\t__func__, stop);\n \t\t/* align to the beginning of this cache line */\n \t\tstop &= ~(line_len - 1);\n \t}\ndiff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c\nindex 36c629c..21d13f7 100644\n--- a/arch/arm/lib/cache-pl310.c\n+++ b/arch/arm/lib/cache-pl310.c\n@@ -26,6 +26,7 @@\n #include <asm/armv7.h>\n #include <asm/pl310.h>\n #include <config.h>\n+#include <common.h>\n \n struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;\n \n@@ -89,21 +90,23 @@ void v7_outer_cache_inval_range(u32 start, u32 stop)\n \tu32 pa, line_size = 32;\n \n \t/*\n-\t * If start address is not aligned to cache-line flush the first\n-\t * line to prevent affecting somebody else's buffer\n+\t * If start address is not aligned to cache-line do not\n+\t * invalidate the first cache-line\n \t */\n \tif (start & (line_size - 1)) {\n-\t\tv7_outer_cache_flush_range(start, start + 1);\n+\t\tprintf(\"ERROR: %s - start address is not aligned - 0x%08x\\n\",\n+\t\t\t__func__, start);\n \t\t/* move to next cache line */\n \t\tstart = (start + line_size - 1) & ~(line_size - 1);\n \t}\n \n \t/*\n-\t * If stop address is not aligned to cache-line flush the last\n-\t * line to prevent affecting somebody else's buffer\n+\t * If stop address is not aligned to cache-line do not\n+\t * invalidate the last cache-line\n \t */\n \tif (stop & (line_size - 1)) {\n-\t\tv7_outer_cache_flush_range(stop, stop + 1);\n+\t\tprintf(\"ERROR: %s - stop address is not aligned - 0x%08x\\n\",\n+\t\t\t__func__, stop);\n \t\t/* align to the beginning of this cache line */\n \t\tstop &= ~(line_size - 1);\n \t}\n", "prefixes": [ "U-Boot", "v3", "4/4" ] }