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GET /api/patches/1087279/?format=api
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{
    "id": 1087279,
    "url": "http://patchwork.ozlabs.org/api/patches/1087279/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190417221737.11460-4-alice.michael@intel.com/",
    "project": {
        "id": 46,
        "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api",
        "name": "Intel Wired Ethernet development",
        "link_name": "intel-wired-lan",
        "list_id": "intel-wired-lan.osuosl.org",
        "list_email": "intel-wired-lan@osuosl.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20190417221737.11460-4-alice.michael@intel.com>",
    "list_archive_url": null,
    "date": "2019-04-17T22:17:32",
    "name": "[next,S4,iavf,4/9] iavf: replace i40e variables with iavf",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "cc39fe5e1bda943c410059ef550a5b5850332e6f",
    "submitter": {
        "id": 71123,
        "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api",
        "name": "Michael, Alice",
        "email": "alice.michael@intel.com"
    },
    "delegate": {
        "id": 68,
        "url": "http://patchwork.ozlabs.org/api/users/68/?format=api",
        "username": "jtkirshe",
        "first_name": "Jeff",
        "last_name": "Kirsher",
        "email": "jeffrey.t.kirsher@intel.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190417221737.11460-4-alice.michael@intel.com/mbox/",
    "series": [
        {
            "id": 103397,
            "url": "http://patchwork.ozlabs.org/api/series/103397/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=103397",
            "date": "2019-04-17T22:17:29",
            "name": "[next,S4,iavf,1/9] iavf: Rename i40e_adminq* files to iavf_adminq*",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/103397/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1087279/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1087279/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<intel-wired-lan-bounces@osuosl.org>",
        "X-Original-To": [
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            "intel-wired-lan@lists.osuosl.org"
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        "Delivered-To": [
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            "intel-wired-lan@lists.osuosl.org"
        ],
        "Authentication-Results": [
            "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)",
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            "from orsmga006.jf.intel.com ([10.7.209.51])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t17 Apr 2019 15:19:40 -0700",
            "from alicemic-2.jf.intel.com ([10.166.16.121])\n\tby orsmga006.jf.intel.com with ESMTP; 17 Apr 2019 15:19:40 -0700"
        ],
        "X-Virus-Scanned": [
            "amavisd-new at osuosl.org",
            "amavisd-new at osuosl.org"
        ],
        "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6",
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.60,363,1549958400\"; d=\"scan'208\";a=\"136697245\"",
        "From": "Alice Michael <alice.michael@intel.com>",
        "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org",
        "Date": "Wed, 17 Apr 2019 15:17:32 -0700",
        "Message-Id": "<20190417221737.11460-4-alice.michael@intel.com>",
        "X-Mailer": "git-send-email 2.19.2",
        "In-Reply-To": "<20190417221737.11460-1-alice.michael@intel.com>",
        "References": "<20190417221737.11460-1-alice.michael@intel.com>",
        "MIME-Version": "1.0",
        "Subject": "[Intel-wired-lan] [next PATCH S4 iavf 4/9] iavf: replace i40e\n\tvariables with iavf",
        "X-BeenThere": "intel-wired-lan@osuosl.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>",
        "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>",
        "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>",
        "List-Post": "<mailto:intel-wired-lan@osuosl.org>",
        "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>",
        "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>",
        "Content-Type": "text/plain; charset=\"us-ascii\"",
        "Content-Transfer-Encoding": "7bit",
        "Errors-To": "intel-wired-lan-bounces@osuosl.org",
        "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>"
    },
    "content": "Update the old variables and flags marked as i40e to match\nthe iavf name of the driver.\n\nSigned-off-by: Alice Michael <alice.michael@intel.com>\n---\n drivers/net/ethernet/intel/iavf/iavf_adminq.c |  80 +--\n drivers/net/ethernet/intel/iavf/iavf_adminq.h |  72 +-\n .../net/ethernet/intel/iavf/iavf_adminq_cmd.h | 656 +++++++++---------\n drivers/net/ethernet/intel/iavf/iavf_common.c | 182 ++---\n .../net/ethernet/intel/iavf/iavf_ethtool.c    |  12 +-\n drivers/net/ethernet/intel/iavf/iavf_main.c   |  18 +-\n .../net/ethernet/intel/iavf/iavf_prototype.h  |  14 +-\n drivers/net/ethernet/intel/iavf/iavf_txrx.c   |  12 +-\n drivers/net/ethernet/intel/iavf/iavf_type.h   |   2 +-\n .../net/ethernet/intel/iavf/iavf_virtchnl.c   |  16 +-\n 10 files changed, 532 insertions(+), 532 deletions(-)",
    "diff": "diff --git a/drivers/net/ethernet/intel/iavf/iavf_adminq.c b/drivers/net/ethernet/intel/iavf/iavf_adminq.c\nindex 59025172f3fa..56172e2974bb 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_adminq.c\n+++ b/drivers/net/ethernet/intel/iavf/iavf_adminq.c\n@@ -37,16 +37,16 @@ static enum iavf_status i40e_alloc_adminq_asq_ring(struct iavf_hw *hw)\n \tenum iavf_status ret_code;\n \n \tret_code = iavf_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,\n-\t\t\t\t\t i40e_mem_atq_ring,\n+\t\t\t\t\t iavf_mem_atq_ring,\n \t\t\t\t\t (hw->aq.num_asq_entries *\n-\t\t\t\t\t sizeof(struct i40e_aq_desc)),\n+\t\t\t\t\t sizeof(struct iavf_aq_desc)),\n \t\t\t\t\t IAVF_ADMINQ_DESC_ALIGNMENT);\n \tif (ret_code)\n \t\treturn ret_code;\n \n \tret_code = iavf_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,\n \t\t\t\t\t  (hw->aq.num_asq_entries *\n-\t\t\t\t\t  sizeof(struct i40e_asq_cmd_details)));\n+\t\t\t\t\t  sizeof(struct iavf_asq_cmd_details)));\n \tif (ret_code) {\n \t\tiavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);\n \t\treturn ret_code;\n@@ -64,9 +64,9 @@ static enum iavf_status i40e_alloc_adminq_arq_ring(struct iavf_hw *hw)\n \tenum iavf_status ret_code;\n \n \tret_code = iavf_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,\n-\t\t\t\t\t i40e_mem_arq_ring,\n+\t\t\t\t\t iavf_mem_arq_ring,\n \t\t\t\t\t (hw->aq.num_arq_entries *\n-\t\t\t\t\t sizeof(struct i40e_aq_desc)),\n+\t\t\t\t\t sizeof(struct iavf_aq_desc)),\n \t\t\t\t\t IAVF_ADMINQ_DESC_ALIGNMENT);\n \n \treturn ret_code;\n@@ -102,7 +102,7 @@ static void i40e_free_adminq_arq(struct iavf_hw *hw)\n  **/\n static enum iavf_status i40e_alloc_arq_bufs(struct iavf_hw *hw)\n {\n-\tstruct i40e_aq_desc *desc;\n+\tstruct iavf_aq_desc *desc;\n \tstruct iavf_dma_mem *bi;\n \tenum iavf_status ret_code;\n \tint i;\n@@ -123,7 +123,7 @@ static enum iavf_status i40e_alloc_arq_bufs(struct iavf_hw *hw)\n \tfor (i = 0; i < hw->aq.num_arq_entries; i++) {\n \t\tbi = &hw->aq.arq.r.arq_bi[i];\n \t\tret_code = iavf_allocate_dma_mem(hw, bi,\n-\t\t\t\t\t\t i40e_mem_arq_buf,\n+\t\t\t\t\t\t iavf_mem_arq_buf,\n \t\t\t\t\t\t hw->aq.arq_buf_size,\n \t\t\t\t\t\t IAVF_ADMINQ_DESC_ALIGNMENT);\n \t\tif (ret_code)\n@@ -132,9 +132,9 @@ static enum iavf_status i40e_alloc_arq_bufs(struct iavf_hw *hw)\n \t\t/* now configure the descriptors for use */\n \t\tdesc = IAVF_ADMINQ_DESC(hw->aq.arq, i);\n \n-\t\tdesc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);\n-\t\tif (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)\n-\t\t\tdesc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);\n+\t\tdesc->flags = cpu_to_le16(IAVF_AQ_FLAG_BUF);\n+\t\tif (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF)\n+\t\t\tdesc->flags |= cpu_to_le16(IAVF_AQ_FLAG_LB);\n \t\tdesc->opcode = 0;\n \t\t/* This is in accordance with Admin queue design, there is no\n \t\t * register for buffer size configuration\n@@ -186,7 +186,7 @@ static enum iavf_status i40e_alloc_asq_bufs(struct iavf_hw *hw)\n \tfor (i = 0; i < hw->aq.num_asq_entries; i++) {\n \t\tbi = &hw->aq.asq.r.asq_bi[i];\n \t\tret_code = iavf_allocate_dma_mem(hw, bi,\n-\t\t\t\t\t\t i40e_mem_asq_buf,\n+\t\t\t\t\t\t iavf_mem_asq_buf,\n \t\t\t\t\t\t hw->aq.asq_buf_size,\n \t\t\t\t\t\t IAVF_ADMINQ_DESC_ALIGNMENT);\n \t\tif (ret_code)\n@@ -522,7 +522,7 @@ enum iavf_status iavf_init_adminq(struct iavf_hw *hw)\n \tiavf_adminq_init_regs(hw);\n \n \t/* setup ASQ command write back timeout */\n-\thw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;\n+\thw->aq.asq_cmd_timeout = IAVF_ASQ_CMD_TIMEOUT;\n \n \t/* allocate the ASQ */\n \tret_code = i40e_init_asq(hw);\n@@ -571,13 +571,13 @@ enum iavf_status iavf_shutdown_adminq(struct iavf_hw *hw)\n static u16 i40e_clean_asq(struct iavf_hw *hw)\n {\n \tstruct iavf_adminq_ring *asq = &hw->aq.asq;\n-\tstruct i40e_asq_cmd_details *details;\n+\tstruct iavf_asq_cmd_details *details;\n \tu16 ntc = asq->next_to_clean;\n-\tstruct i40e_aq_desc desc_cb;\n-\tstruct i40e_aq_desc *desc;\n+\tstruct iavf_aq_desc desc_cb;\n+\tstruct iavf_aq_desc *desc;\n \n \tdesc = IAVF_ADMINQ_DESC(*asq, ntc);\n-\tdetails = I40E_ADMINQ_DETAILS(*asq, ntc);\n+\tdetails = IAVF_ADMINQ_DETAILS(*asq, ntc);\n \twhile (rd32(hw, hw->aq.asq.head) != ntc) {\n \t\tiavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,\n \t\t\t   \"ntc %d head %d.\\n\", ntc, rd32(hw, hw->aq.asq.head));\n@@ -588,14 +588,14 @@ static u16 i40e_clean_asq(struct iavf_hw *hw)\n \t\t\tdesc_cb = *desc;\n \t\t\tcb_func(hw, &desc_cb);\n \t\t}\n-\t\tmemset((void *)desc, 0, sizeof(struct i40e_aq_desc));\n+\t\tmemset((void *)desc, 0, sizeof(struct iavf_aq_desc));\n \t\tmemset((void *)details, 0,\n-\t\t       sizeof(struct i40e_asq_cmd_details));\n+\t\t       sizeof(struct iavf_asq_cmd_details));\n \t\tntc++;\n \t\tif (ntc == asq->count)\n \t\t\tntc = 0;\n \t\tdesc = IAVF_ADMINQ_DESC(*asq, ntc);\n-\t\tdetails = I40E_ADMINQ_DETAILS(*asq, ntc);\n+\t\tdetails = IAVF_ADMINQ_DETAILS(*asq, ntc);\n \t}\n \n \tasq->next_to_clean = ntc;\n@@ -630,14 +630,14 @@ bool iavf_asq_done(struct iavf_hw *hw)\n  *  queue.  It runs the queue, cleans the queue, etc\n  **/\n enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,\n-\t\t\t\t       struct i40e_aq_desc *desc,\n+\t\t\t\t       struct iavf_aq_desc *desc,\n \t\t\t\t       void *buff, /* can be NULL */\n \t\t\t\t       u16  buff_size,\n-\t\t\t\t       struct i40e_asq_cmd_details *cmd_details)\n+\t\t\t\t       struct iavf_asq_cmd_details *cmd_details)\n {\n \tstruct iavf_dma_mem *dma_buff = NULL;\n-\tstruct i40e_asq_cmd_details *details;\n-\tstruct i40e_aq_desc *desc_on_ring;\n+\tstruct iavf_asq_cmd_details *details;\n+\tstruct iavf_aq_desc *desc_on_ring;\n \tbool cmd_completed = false;\n \tenum iavf_status status = 0;\n \tu16  retval = 0;\n@@ -652,7 +652,7 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,\n \t\tgoto asq_send_command_error;\n \t}\n \n-\thw->aq.asq_last_status = I40E_AQ_RC_OK;\n+\thw->aq.asq_last_status = IAVF_AQ_RC_OK;\n \n \tval = rd32(hw, hw->aq.asq.head);\n \tif (val >= hw->aq.num_asq_entries) {\n@@ -662,7 +662,7 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,\n \t\tgoto asq_send_command_error;\n \t}\n \n-\tdetails = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);\n+\tdetails = IAVF_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);\n \tif (cmd_details) {\n \t\t*details = *cmd_details;\n \n@@ -677,7 +677,7 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,\n \t\t\t\tcpu_to_le32(lower_32_bits(details->cookie));\n \t\t}\n \t} else {\n-\t\tmemset(details, 0, sizeof(struct i40e_asq_cmd_details));\n+\t\tmemset(details, 0, sizeof(struct iavf_asq_cmd_details));\n \t}\n \n \t/* clear requested flags and then set additional flags if defined */\n@@ -781,13 +781,13 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,\n \t\t\tretval &= 0xff;\n \t\t}\n \t\tcmd_completed = true;\n-\t\tif ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)\n+\t\tif ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_OK)\n \t\t\tstatus = 0;\n-\t\telse if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_EBUSY)\n+\t\telse if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_EBUSY)\n \t\t\tstatus = I40E_ERR_NOT_READY;\n \t\telse\n \t\t\tstatus = I40E_ERR_ADMIN_QUEUE_ERROR;\n-\t\thw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;\n+\t\thw->aq.asq_last_status = (enum iavf_admin_queue_err)retval;\n \t}\n \n \tiavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,\n@@ -824,12 +824,12 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,\n  *\n  *  Fill the desc with default values\n  **/\n-void iavf_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, u16 opcode)\n+void iavf_fill_default_direct_cmd_desc(struct iavf_aq_desc *desc, u16 opcode)\n {\n \t/* zero out the desc */\n-\tmemset((void *)desc, 0, sizeof(struct i40e_aq_desc));\n+\tmemset((void *)desc, 0, sizeof(struct iavf_aq_desc));\n \tdesc->opcode = cpu_to_le16(opcode);\n-\tdesc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);\n+\tdesc->flags = cpu_to_le16(IAVF_AQ_FLAG_SI);\n }\n \n /**\n@@ -843,11 +843,11 @@ void iavf_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, u16 opcode)\n  *  left to process through 'pending'\n  **/\n enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,\n-\t\t\t\t\tstruct i40e_arq_event_info *e,\n+\t\t\t\t\tstruct iavf_arq_event_info *e,\n \t\t\t\t\tu16 *pending)\n {\n \tu16 ntc = hw->aq.arq.next_to_clean;\n-\tstruct i40e_aq_desc *desc;\n+\tstruct iavf_aq_desc *desc;\n \tenum iavf_status ret_code = 0;\n \tstruct iavf_dma_mem *bi;\n \tu16 desc_idx;\n@@ -881,9 +881,9 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,\n \tdesc_idx = ntc;\n \n \thw->aq.arq_last_status =\n-\t\t(enum i40e_admin_queue_err)le16_to_cpu(desc->retval);\n+\t\t(enum iavf_admin_queue_err)le16_to_cpu(desc->retval);\n \tflags = le16_to_cpu(desc->flags);\n-\tif (flags & I40E_AQ_FLAG_ERR) {\n+\tif (flags & IAVF_AQ_FLAG_ERR) {\n \t\tret_code = I40E_ERR_ADMIN_QUEUE_ERROR;\n \t\tiavf_debug(hw,\n \t\t\t   IAVF_DEBUG_AQ_MESSAGE,\n@@ -907,11 +907,11 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,\n \t * size\n \t */\n \tbi = &hw->aq.arq.r.arq_bi[ntc];\n-\tmemset((void *)desc, 0, sizeof(struct i40e_aq_desc));\n+\tmemset((void *)desc, 0, sizeof(struct iavf_aq_desc));\n \n-\tdesc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);\n-\tif (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)\n-\t\tdesc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);\n+\tdesc->flags = cpu_to_le16(IAVF_AQ_FLAG_BUF);\n+\tif (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF)\n+\t\tdesc->flags |= cpu_to_le16(IAVF_AQ_FLAG_LB);\n \tdesc->datalen = cpu_to_le16((u16)bi->size);\n \tdesc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));\n \tdesc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_adminq.h b/drivers/net/ethernet/intel/iavf/iavf_adminq.h\nindex 7c06752c0fea..60a6a41d21a0 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_adminq.h\n+++ b/drivers/net/ethernet/intel/iavf/iavf_adminq.h\n@@ -9,7 +9,7 @@\n #include \"iavf_adminq_cmd.h\"\n \n #define IAVF_ADMINQ_DESC(R, i)   \\\n-\t(&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))\n+\t(&(((struct iavf_aq_desc *)((R).desc_buf.va))[i]))\n \n #define IAVF_ADMINQ_DESC_ALIGNMENT 4096\n \n@@ -39,22 +39,22 @@ struct iavf_adminq_ring {\n };\n \n /* ASQ transaction details */\n-struct i40e_asq_cmd_details {\n-\tvoid *callback; /* cast from type I40E_ADMINQ_CALLBACK */\n+struct iavf_asq_cmd_details {\n+\tvoid *callback; /* cast from type IAVF_ADMINQ_CALLBACK */\n \tu64 cookie;\n \tu16 flags_ena;\n \tu16 flags_dis;\n \tbool async;\n \tbool postpone;\n-\tstruct i40e_aq_desc *wb_desc;\n+\tstruct iavf_aq_desc *wb_desc;\n };\n \n-#define I40E_ADMINQ_DETAILS(R, i)   \\\n-\t(&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))\n+#define IAVF_ADMINQ_DETAILS(R, i)   \\\n+\t(&(((struct iavf_asq_cmd_details *)((R).cmd_buf.va))[i]))\n \n /* ARQ event information */\n-struct i40e_arq_event_info {\n-\tstruct i40e_aq_desc desc;\n+struct iavf_arq_event_info {\n+\tstruct iavf_aq_desc desc;\n \tu16 msg_len;\n \tu16 buf_len;\n \tu8 *msg_buf;\n@@ -79,8 +79,8 @@ struct iavf_adminq_info {\n \tstruct mutex arq_mutex; /* Receive queue lock */\n \n \t/* last status values on send and receive queues */\n-\tenum i40e_admin_queue_err asq_last_status;\n-\tenum i40e_admin_queue_err arq_last_status;\n+\tenum iavf_admin_queue_err asq_last_status;\n+\tenum iavf_admin_queue_err arq_last_status;\n };\n \n /**\n@@ -91,29 +91,29 @@ struct iavf_adminq_info {\n static inline int i40e_aq_rc_to_posix(int aq_ret, int aq_rc)\n {\n \tint aq_to_posix[] = {\n-\t\t0,           /* I40E_AQ_RC_OK */\n-\t\t-EPERM,      /* I40E_AQ_RC_EPERM */\n-\t\t-ENOENT,     /* I40E_AQ_RC_ENOENT */\n-\t\t-ESRCH,      /* I40E_AQ_RC_ESRCH */\n-\t\t-EINTR,      /* I40E_AQ_RC_EINTR */\n-\t\t-EIO,        /* I40E_AQ_RC_EIO */\n-\t\t-ENXIO,      /* I40E_AQ_RC_ENXIO */\n-\t\t-E2BIG,      /* I40E_AQ_RC_E2BIG */\n-\t\t-EAGAIN,     /* I40E_AQ_RC_EAGAIN */\n-\t\t-ENOMEM,     /* I40E_AQ_RC_ENOMEM */\n-\t\t-EACCES,     /* I40E_AQ_RC_EACCES */\n-\t\t-EFAULT,     /* I40E_AQ_RC_EFAULT */\n-\t\t-EBUSY,      /* I40E_AQ_RC_EBUSY */\n-\t\t-EEXIST,     /* I40E_AQ_RC_EEXIST */\n-\t\t-EINVAL,     /* I40E_AQ_RC_EINVAL */\n-\t\t-ENOTTY,     /* I40E_AQ_RC_ENOTTY */\n-\t\t-ENOSPC,     /* I40E_AQ_RC_ENOSPC */\n-\t\t-ENOSYS,     /* I40E_AQ_RC_ENOSYS */\n-\t\t-ERANGE,     /* I40E_AQ_RC_ERANGE */\n-\t\t-EPIPE,      /* I40E_AQ_RC_EFLUSHED */\n-\t\t-ESPIPE,     /* I40E_AQ_RC_BAD_ADDR */\n-\t\t-EROFS,      /* I40E_AQ_RC_EMODE */\n-\t\t-EFBIG,      /* I40E_AQ_RC_EFBIG */\n+\t\t0,           /* IAVF_AQ_RC_OK */\n+\t\t-EPERM,      /* IAVF_AQ_RC_EPERM */\n+\t\t-ENOENT,     /* IAVF_AQ_RC_ENOENT */\n+\t\t-ESRCH,      /* IAVF_AQ_RC_ESRCH */\n+\t\t-EINTR,      /* IAVF_AQ_RC_EINTR */\n+\t\t-EIO,        /* IAVF_AQ_RC_EIO */\n+\t\t-ENXIO,      /* IAVF_AQ_RC_ENXIO */\n+\t\t-E2BIG,      /* IAVF_AQ_RC_E2BIG */\n+\t\t-EAGAIN,     /* IAVF_AQ_RC_EAGAIN */\n+\t\t-ENOMEM,     /* IAVF_AQ_RC_ENOMEM */\n+\t\t-EACCES,     /* IAVF_AQ_RC_EACCES */\n+\t\t-EFAULT,     /* IAVF_AQ_RC_EFAULT */\n+\t\t-EBUSY,      /* IAVF_AQ_RC_EBUSY */\n+\t\t-EEXIST,     /* IAVF_AQ_RC_EEXIST */\n+\t\t-EINVAL,     /* IAVF_AQ_RC_EINVAL */\n+\t\t-ENOTTY,     /* IAVF_AQ_RC_ENOTTY */\n+\t\t-ENOSPC,     /* IAVF_AQ_RC_ENOSPC */\n+\t\t-ENOSYS,     /* IAVF_AQ_RC_ENOSYS */\n+\t\t-ERANGE,     /* IAVF_AQ_RC_ERANGE */\n+\t\t-EPIPE,      /* IAVF_AQ_RC_EFLUSHED */\n+\t\t-ESPIPE,     /* IAVF_AQ_RC_BAD_ADDR */\n+\t\t-EROFS,      /* IAVF_AQ_RC_EMODE */\n+\t\t-EFBIG,      /* IAVF_AQ_RC_EFBIG */\n \t};\n \n \t/* aq_rc is invalid if AQ timed out */\n@@ -127,9 +127,9 @@ static inline int i40e_aq_rc_to_posix(int aq_ret, int aq_rc)\n }\n \n /* general information */\n-#define I40E_AQ_LARGE_BUF\t512\n-#define I40E_ASQ_CMD_TIMEOUT\t250000  /* usecs */\n+#define IAVF_AQ_LARGE_BUF\t512\n+#define IAVF_ASQ_CMD_TIMEOUT\t250000  /* usecs */\n \n-void iavf_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, u16 opcode);\n+void iavf_fill_default_direct_cmd_desc(struct iavf_aq_desc *desc, u16 opcode);\n \n #endif /* _IAVF_ADMINQ_H_ */\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h b/drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h\nindex e5ae4a1c0cff..d088557fa56c 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h\n@@ -1,29 +1,29 @@\n /* SPDX-License-Identifier: GPL-2.0 */\n /* Copyright(c) 2013 - 2018 Intel Corporation. */\n \n-#ifndef _I40E_ADMINQ_CMD_H_\n-#define _I40E_ADMINQ_CMD_H_\n+#ifndef _IAVF_ADMINQ_CMD_H_\n+#define _IAVF_ADMINQ_CMD_H_\n \n-/* This header file defines the i40e Admin Queue commands and is shared between\n- * i40e Firmware and Software.  Do not change the names in this file to IAVF\n- * because this file should be diff-able against the i40e version, even\n+/* This header file defines the iavf Admin Queue commands and is shared between\n+ * iavf Firmware and Software.  Do not change the names in this file to IAVF\n+ * because this file should be diff-able against the iavf version, even\n  * though many parts have been removed in this VF version.\n  *\n  * This file needs to comply with the Linux Kernel coding style.\n  */\n \n-#define I40E_FW_API_VERSION_MAJOR\t0x0001\n-#define I40E_FW_API_VERSION_MINOR_X722\t0x0005\n-#define I40E_FW_API_VERSION_MINOR_X710\t0x0008\n+#define IAVF_FW_API_VERSION_MAJOR\t0x0001\n+#define IAVF_FW_API_VERSION_MINOR_X722\t0x0005\n+#define IAVF_FW_API_VERSION_MINOR_X710\t0x0008\n \n-#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \\\n-\t\t\t\t\tI40E_FW_API_VERSION_MINOR_X710 : \\\n-\t\t\t\t\tI40E_FW_API_VERSION_MINOR_X722)\n+#define IAVF_FW_MINOR_VERSION(_h) ((_h)->mac.type == IAVF_MAC_XL710 ? \\\n+\t\t\t\t\tIAVF_FW_API_VERSION_MINOR_X710 : \\\n+\t\t\t\t\tIAVF_FW_API_VERSION_MINOR_X722)\n \n /* API version 1.7 implements additional link and PHY-specific APIs  */\n-#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007\n+#define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007\n \n-struct i40e_aq_desc {\n+struct iavf_aq_desc {\n \t__le16 flags;\n \t__le16 opcode;\n \t__le16 datalen;\n@@ -53,234 +53,234 @@ struct i40e_aq_desc {\n  */\n \n /* command flags and offsets*/\n-#define I40E_AQ_FLAG_DD_SHIFT\t0\n-#define I40E_AQ_FLAG_CMP_SHIFT\t1\n-#define I40E_AQ_FLAG_ERR_SHIFT\t2\n-#define I40E_AQ_FLAG_VFE_SHIFT\t3\n-#define I40E_AQ_FLAG_LB_SHIFT\t9\n-#define I40E_AQ_FLAG_RD_SHIFT\t10\n-#define I40E_AQ_FLAG_VFC_SHIFT\t11\n-#define I40E_AQ_FLAG_BUF_SHIFT\t12\n-#define I40E_AQ_FLAG_SI_SHIFT\t13\n-#define I40E_AQ_FLAG_EI_SHIFT\t14\n-#define I40E_AQ_FLAG_FE_SHIFT\t15\n-\n-#define I40E_AQ_FLAG_DD\t\tBIT(I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */\n-#define I40E_AQ_FLAG_CMP\tBIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */\n-#define I40E_AQ_FLAG_ERR\tBIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */\n-#define I40E_AQ_FLAG_VFE\tBIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */\n-#define I40E_AQ_FLAG_LB\t\tBIT(I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */\n-#define I40E_AQ_FLAG_RD\t\tBIT(I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */\n-#define I40E_AQ_FLAG_VFC\tBIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */\n-#define I40E_AQ_FLAG_BUF\tBIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */\n-#define I40E_AQ_FLAG_SI\t\tBIT(I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */\n-#define I40E_AQ_FLAG_EI\t\tBIT(I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */\n-#define I40E_AQ_FLAG_FE\t\tBIT(I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */\n+#define IAVF_AQ_FLAG_DD_SHIFT\t0\n+#define IAVF_AQ_FLAG_CMP_SHIFT\t1\n+#define IAVF_AQ_FLAG_ERR_SHIFT\t2\n+#define IAVF_AQ_FLAG_VFE_SHIFT\t3\n+#define IAVF_AQ_FLAG_LB_SHIFT\t9\n+#define IAVF_AQ_FLAG_RD_SHIFT\t10\n+#define IAVF_AQ_FLAG_VFC_SHIFT\t11\n+#define IAVF_AQ_FLAG_BUF_SHIFT\t12\n+#define IAVF_AQ_FLAG_SI_SHIFT\t13\n+#define IAVF_AQ_FLAG_EI_SHIFT\t14\n+#define IAVF_AQ_FLAG_FE_SHIFT\t15\n+\n+#define IAVF_AQ_FLAG_DD\t\tBIT(IAVF_AQ_FLAG_DD_SHIFT)  /* 0x1    */\n+#define IAVF_AQ_FLAG_CMP\tBIT(IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2    */\n+#define IAVF_AQ_FLAG_ERR\tBIT(IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4    */\n+#define IAVF_AQ_FLAG_VFE\tBIT(IAVF_AQ_FLAG_VFE_SHIFT) /* 0x8    */\n+#define IAVF_AQ_FLAG_LB\t\tBIT(IAVF_AQ_FLAG_LB_SHIFT)  /* 0x200  */\n+#define IAVF_AQ_FLAG_RD\t\tBIT(IAVF_AQ_FLAG_RD_SHIFT)  /* 0x400  */\n+#define IAVF_AQ_FLAG_VFC\tBIT(IAVF_AQ_FLAG_VFC_SHIFT) /* 0x800  */\n+#define IAVF_AQ_FLAG_BUF\tBIT(IAVF_AQ_FLAG_BUF_SHIFT) /* 0x1000 */\n+#define IAVF_AQ_FLAG_SI\t\tBIT(IAVF_AQ_FLAG_SI_SHIFT)  /* 0x2000 */\n+#define IAVF_AQ_FLAG_EI\t\tBIT(IAVF_AQ_FLAG_EI_SHIFT)  /* 0x4000 */\n+#define IAVF_AQ_FLAG_FE\t\tBIT(IAVF_AQ_FLAG_FE_SHIFT)  /* 0x8000 */\n \n /* error codes */\n-enum i40e_admin_queue_err {\n-\tI40E_AQ_RC_OK\t\t= 0,  /* success */\n-\tI40E_AQ_RC_EPERM\t= 1,  /* Operation not permitted */\n-\tI40E_AQ_RC_ENOENT\t= 2,  /* No such element */\n-\tI40E_AQ_RC_ESRCH\t= 3,  /* Bad opcode */\n-\tI40E_AQ_RC_EINTR\t= 4,  /* operation interrupted */\n-\tI40E_AQ_RC_EIO\t\t= 5,  /* I/O error */\n-\tI40E_AQ_RC_ENXIO\t= 6,  /* No such resource */\n-\tI40E_AQ_RC_E2BIG\t= 7,  /* Arg too long */\n-\tI40E_AQ_RC_EAGAIN\t= 8,  /* Try again */\n-\tI40E_AQ_RC_ENOMEM\t= 9,  /* Out of memory */\n-\tI40E_AQ_RC_EACCES\t= 10, /* Permission denied */\n-\tI40E_AQ_RC_EFAULT\t= 11, /* Bad address */\n-\tI40E_AQ_RC_EBUSY\t= 12, /* Device or resource busy */\n-\tI40E_AQ_RC_EEXIST\t= 13, /* object already exists */\n-\tI40E_AQ_RC_EINVAL\t= 14, /* Invalid argument */\n-\tI40E_AQ_RC_ENOTTY\t= 15, /* Not a typewriter */\n-\tI40E_AQ_RC_ENOSPC\t= 16, /* No space left or alloc failure */\n-\tI40E_AQ_RC_ENOSYS\t= 17, /* Function not implemented */\n-\tI40E_AQ_RC_ERANGE\t= 18, /* Parameter out of range */\n-\tI40E_AQ_RC_EFLUSHED\t= 19, /* Cmd flushed due to prev cmd error */\n-\tI40E_AQ_RC_BAD_ADDR\t= 20, /* Descriptor contains a bad pointer */\n-\tI40E_AQ_RC_EMODE\t= 21, /* Op not allowed in current dev mode */\n-\tI40E_AQ_RC_EFBIG\t= 22, /* File too large */\n+enum iavf_admin_queue_err {\n+\tIAVF_AQ_RC_OK\t\t= 0,  /* success */\n+\tIAVF_AQ_RC_EPERM\t= 1,  /* Operation not permitted */\n+\tIAVF_AQ_RC_ENOENT\t= 2,  /* No such element */\n+\tIAVF_AQ_RC_ESRCH\t= 3,  /* Bad opcode */\n+\tIAVF_AQ_RC_EINTR\t= 4,  /* operation interrupted */\n+\tIAVF_AQ_RC_EIO\t\t= 5,  /* I/O error */\n+\tIAVF_AQ_RC_ENXIO\t= 6,  /* No such resource */\n+\tIAVF_AQ_RC_E2BIG\t= 7,  /* Arg too long */\n+\tIAVF_AQ_RC_EAGAIN\t= 8,  /* Try again */\n+\tIAVF_AQ_RC_ENOMEM\t= 9,  /* Out of memory */\n+\tIAVF_AQ_RC_EACCES\t= 10, /* Permission denied */\n+\tIAVF_AQ_RC_EFAULT\t= 11, /* Bad address */\n+\tIAVF_AQ_RC_EBUSY\t= 12, /* Device or resource busy */\n+\tIAVF_AQ_RC_EEXIST\t= 13, /* object already exists */\n+\tIAVF_AQ_RC_EINVAL\t= 14, /* Invalid argument */\n+\tIAVF_AQ_RC_ENOTTY\t= 15, /* Not a typewriter */\n+\tIAVF_AQ_RC_ENOSPC\t= 16, /* No space left or alloc failure */\n+\tIAVF_AQ_RC_ENOSYS\t= 17, /* Function not implemented */\n+\tIAVF_AQ_RC_ERANGE\t= 18, /* Parameter out of range */\n+\tIAVF_AQ_RC_EFLUSHED\t= 19, /* Cmd flushed due to prev cmd error */\n+\tIAVF_AQ_RC_BAD_ADDR\t= 20, /* Descriptor contains a bad pointer */\n+\tIAVF_AQ_RC_EMODE\t= 21, /* Op not allowed in current dev mode */\n+\tIAVF_AQ_RC_EFBIG\t= 22, /* File too large */\n };\n \n /* Admin Queue command opcodes */\n-enum i40e_admin_queue_opc {\n+enum iavf_admin_queue_opc {\n \t/* aq commands */\n-\ti40e_aqc_opc_get_version\t= 0x0001,\n-\ti40e_aqc_opc_driver_version\t= 0x0002,\n-\ti40e_aqc_opc_queue_shutdown\t= 0x0003,\n-\ti40e_aqc_opc_set_pf_context\t= 0x0004,\n+\tiavf_aqc_opc_get_version\t= 0x0001,\n+\tiavf_aqc_opc_driver_version\t= 0x0002,\n+\tiavf_aqc_opc_queue_shutdown\t= 0x0003,\n+\tiavf_aqc_opc_set_pf_context\t= 0x0004,\n \n \t/* resource ownership */\n-\ti40e_aqc_opc_request_resource\t= 0x0008,\n-\ti40e_aqc_opc_release_resource\t= 0x0009,\n+\tiavf_aqc_opc_request_resource\t= 0x0008,\n+\tiavf_aqc_opc_release_resource\t= 0x0009,\n \n-\ti40e_aqc_opc_list_func_capabilities\t= 0x000A,\n-\ti40e_aqc_opc_list_dev_capabilities\t= 0x000B,\n+\tiavf_aqc_opc_list_func_capabilities\t= 0x000A,\n+\tiavf_aqc_opc_list_dev_capabilities\t= 0x000B,\n \n \t/* Proxy commands */\n-\ti40e_aqc_opc_set_proxy_config\t\t= 0x0104,\n-\ti40e_aqc_opc_set_ns_proxy_table_entry\t= 0x0105,\n+\tiavf_aqc_opc_set_proxy_config\t\t= 0x0104,\n+\tiavf_aqc_opc_set_ns_proxy_table_entry\t= 0x0105,\n \n \t/* LAA */\n-\ti40e_aqc_opc_mac_address_read\t= 0x0107,\n-\ti40e_aqc_opc_mac_address_write\t= 0x0108,\n+\tiavf_aqc_opc_mac_address_read\t= 0x0107,\n+\tiavf_aqc_opc_mac_address_write\t= 0x0108,\n \n \t/* PXE */\n-\ti40e_aqc_opc_clear_pxe_mode\t= 0x0110,\n+\tiavf_aqc_opc_clear_pxe_mode\t= 0x0110,\n \n \t/* WoL commands */\n-\ti40e_aqc_opc_set_wol_filter\t= 0x0120,\n-\ti40e_aqc_opc_get_wake_reason\t= 0x0121,\n+\tiavf_aqc_opc_set_wol_filter\t= 0x0120,\n+\tiavf_aqc_opc_get_wake_reason\t= 0x0121,\n \n \t/* internal switch commands */\n-\ti40e_aqc_opc_get_switch_config\t\t= 0x0200,\n-\ti40e_aqc_opc_add_statistics\t\t= 0x0201,\n-\ti40e_aqc_opc_remove_statistics\t\t= 0x0202,\n-\ti40e_aqc_opc_set_port_parameters\t= 0x0203,\n-\ti40e_aqc_opc_get_switch_resource_alloc\t= 0x0204,\n-\ti40e_aqc_opc_set_switch_config\t\t= 0x0205,\n-\ti40e_aqc_opc_rx_ctl_reg_read\t\t= 0x0206,\n-\ti40e_aqc_opc_rx_ctl_reg_write\t\t= 0x0207,\n-\n-\ti40e_aqc_opc_add_vsi\t\t\t= 0x0210,\n-\ti40e_aqc_opc_update_vsi_parameters\t= 0x0211,\n-\ti40e_aqc_opc_get_vsi_parameters\t\t= 0x0212,\n-\n-\ti40e_aqc_opc_add_pv\t\t\t= 0x0220,\n-\ti40e_aqc_opc_update_pv_parameters\t= 0x0221,\n-\ti40e_aqc_opc_get_pv_parameters\t\t= 0x0222,\n-\n-\ti40e_aqc_opc_add_veb\t\t\t= 0x0230,\n-\ti40e_aqc_opc_update_veb_parameters\t= 0x0231,\n-\ti40e_aqc_opc_get_veb_parameters\t\t= 0x0232,\n-\n-\ti40e_aqc_opc_delete_element\t\t= 0x0243,\n-\n-\ti40e_aqc_opc_add_macvlan\t\t= 0x0250,\n-\ti40e_aqc_opc_remove_macvlan\t\t= 0x0251,\n-\ti40e_aqc_opc_add_vlan\t\t\t= 0x0252,\n-\ti40e_aqc_opc_remove_vlan\t\t= 0x0253,\n-\ti40e_aqc_opc_set_vsi_promiscuous_modes\t= 0x0254,\n-\ti40e_aqc_opc_add_tag\t\t\t= 0x0255,\n-\ti40e_aqc_opc_remove_tag\t\t\t= 0x0256,\n-\ti40e_aqc_opc_add_multicast_etag\t\t= 0x0257,\n-\ti40e_aqc_opc_remove_multicast_etag\t= 0x0258,\n-\ti40e_aqc_opc_update_tag\t\t\t= 0x0259,\n-\ti40e_aqc_opc_add_control_packet_filter\t= 0x025A,\n-\ti40e_aqc_opc_remove_control_packet_filter\t= 0x025B,\n-\ti40e_aqc_opc_add_cloud_filters\t\t= 0x025C,\n-\ti40e_aqc_opc_remove_cloud_filters\t= 0x025D,\n-\ti40e_aqc_opc_clear_wol_switch_filters\t= 0x025E,\n-\n-\ti40e_aqc_opc_add_mirror_rule\t= 0x0260,\n-\ti40e_aqc_opc_delete_mirror_rule\t= 0x0261,\n+\tiavf_aqc_opc_get_switch_config\t\t= 0x0200,\n+\tiavf_aqc_opc_add_statistics\t\t= 0x0201,\n+\tiavf_aqc_opc_remove_statistics\t\t= 0x0202,\n+\tiavf_aqc_opc_set_port_parameters\t= 0x0203,\n+\tiavf_aqc_opc_get_switch_resource_alloc\t= 0x0204,\n+\tiavf_aqc_opc_set_switch_config\t\t= 0x0205,\n+\tiavf_aqc_opc_rx_ctl_reg_read\t\t= 0x0206,\n+\tiavf_aqc_opc_rx_ctl_reg_write\t\t= 0x0207,\n+\n+\tiavf_aqc_opc_add_vsi\t\t\t= 0x0210,\n+\tiavf_aqc_opc_update_vsi_parameters\t= 0x0211,\n+\tiavf_aqc_opc_get_vsi_parameters\t\t= 0x0212,\n+\n+\tiavf_aqc_opc_add_pv\t\t\t= 0x0220,\n+\tiavf_aqc_opc_update_pv_parameters\t= 0x0221,\n+\tiavf_aqc_opc_get_pv_parameters\t\t= 0x0222,\n+\n+\tiavf_aqc_opc_add_veb\t\t\t= 0x0230,\n+\tiavf_aqc_opc_update_veb_parameters\t= 0x0231,\n+\tiavf_aqc_opc_get_veb_parameters\t\t= 0x0232,\n+\n+\tiavf_aqc_opc_delete_element\t\t= 0x0243,\n+\n+\tiavf_aqc_opc_add_macvlan\t\t= 0x0250,\n+\tiavf_aqc_opc_remove_macvlan\t\t= 0x0251,\n+\tiavf_aqc_opc_add_vlan\t\t\t= 0x0252,\n+\tiavf_aqc_opc_remove_vlan\t\t= 0x0253,\n+\tiavf_aqc_opc_set_vsi_promiscuous_modes\t= 0x0254,\n+\tiavf_aqc_opc_add_tag\t\t\t= 0x0255,\n+\tiavf_aqc_opc_remove_tag\t\t\t= 0x0256,\n+\tiavf_aqc_opc_add_multicast_etag\t\t= 0x0257,\n+\tiavf_aqc_opc_remove_multicast_etag\t= 0x0258,\n+\tiavf_aqc_opc_update_tag\t\t\t= 0x0259,\n+\tiavf_aqc_opc_add_control_packet_filter\t= 0x025A,\n+\tiavf_aqc_opc_remove_control_packet_filter\t= 0x025B,\n+\tiavf_aqc_opc_add_cloud_filters\t\t= 0x025C,\n+\tiavf_aqc_opc_remove_cloud_filters\t= 0x025D,\n+\tiavf_aqc_opc_clear_wol_switch_filters\t= 0x025E,\n+\n+\tiavf_aqc_opc_add_mirror_rule\t= 0x0260,\n+\tiavf_aqc_opc_delete_mirror_rule\t= 0x0261,\n \n \t/* Dynamic Device Personalization */\n-\ti40e_aqc_opc_write_personalization_profile\t= 0x0270,\n-\ti40e_aqc_opc_get_personalization_profile_list\t= 0x0271,\n+\tiavf_aqc_opc_write_personalization_profile\t= 0x0270,\n+\tiavf_aqc_opc_get_personalization_profile_list\t= 0x0271,\n \n \t/* DCB commands */\n-\ti40e_aqc_opc_dcb_ignore_pfc\t= 0x0301,\n-\ti40e_aqc_opc_dcb_updated\t= 0x0302,\n-\ti40e_aqc_opc_set_dcb_parameters = 0x0303,\n+\tiavf_aqc_opc_dcb_ignore_pfc\t= 0x0301,\n+\tiavf_aqc_opc_dcb_updated\t= 0x0302,\n+\tiavf_aqc_opc_set_dcb_parameters = 0x0303,\n \n \t/* TX scheduler */\n-\ti40e_aqc_opc_configure_vsi_bw_limit\t\t= 0x0400,\n-\ti40e_aqc_opc_configure_vsi_ets_sla_bw_limit\t= 0x0406,\n-\ti40e_aqc_opc_configure_vsi_tc_bw\t\t= 0x0407,\n-\ti40e_aqc_opc_query_vsi_bw_config\t\t= 0x0408,\n-\ti40e_aqc_opc_query_vsi_ets_sla_config\t\t= 0x040A,\n-\ti40e_aqc_opc_configure_switching_comp_bw_limit\t= 0x0410,\n-\n-\ti40e_aqc_opc_enable_switching_comp_ets\t\t\t= 0x0413,\n-\ti40e_aqc_opc_modify_switching_comp_ets\t\t\t= 0x0414,\n-\ti40e_aqc_opc_disable_switching_comp_ets\t\t\t= 0x0415,\n-\ti40e_aqc_opc_configure_switching_comp_ets_bw_limit\t= 0x0416,\n-\ti40e_aqc_opc_configure_switching_comp_bw_config\t\t= 0x0417,\n-\ti40e_aqc_opc_query_switching_comp_ets_config\t\t= 0x0418,\n-\ti40e_aqc_opc_query_port_ets_config\t\t\t= 0x0419,\n-\ti40e_aqc_opc_query_switching_comp_bw_config\t\t= 0x041A,\n-\ti40e_aqc_opc_suspend_port_tx\t\t\t\t= 0x041B,\n-\ti40e_aqc_opc_resume_port_tx\t\t\t\t= 0x041C,\n-\ti40e_aqc_opc_configure_partition_bw\t\t\t= 0x041D,\n+\tiavf_aqc_opc_configure_vsi_bw_limit\t\t= 0x0400,\n+\tiavf_aqc_opc_configure_vsi_ets_sla_bw_limit\t= 0x0406,\n+\tiavf_aqc_opc_configure_vsi_tc_bw\t\t= 0x0407,\n+\tiavf_aqc_opc_query_vsi_bw_config\t\t= 0x0408,\n+\tiavf_aqc_opc_query_vsi_ets_sla_config\t\t= 0x040A,\n+\tiavf_aqc_opc_configure_switching_comp_bw_limit\t= 0x0410,\n+\n+\tiavf_aqc_opc_enable_switching_comp_ets\t\t\t= 0x0413,\n+\tiavf_aqc_opc_modify_switching_comp_ets\t\t\t= 0x0414,\n+\tiavf_aqc_opc_disable_switching_comp_ets\t\t\t= 0x0415,\n+\tiavf_aqc_opc_configure_switching_comp_ets_bw_limit\t= 0x0416,\n+\tiavf_aqc_opc_configure_switching_comp_bw_config\t\t= 0x0417,\n+\tiavf_aqc_opc_query_switching_comp_ets_config\t\t= 0x0418,\n+\tiavf_aqc_opc_query_port_ets_config\t\t\t= 0x0419,\n+\tiavf_aqc_opc_query_switching_comp_bw_config\t\t= 0x041A,\n+\tiavf_aqc_opc_suspend_port_tx\t\t\t\t= 0x041B,\n+\tiavf_aqc_opc_resume_port_tx\t\t\t\t= 0x041C,\n+\tiavf_aqc_opc_configure_partition_bw\t\t\t= 0x041D,\n \t/* hmc */\n-\ti40e_aqc_opc_query_hmc_resource_profile\t= 0x0500,\n-\ti40e_aqc_opc_set_hmc_resource_profile\t= 0x0501,\n+\tiavf_aqc_opc_query_hmc_resource_profile\t= 0x0500,\n+\tiavf_aqc_opc_set_hmc_resource_profile\t= 0x0501,\n \n \t/* phy commands*/\n-\ti40e_aqc_opc_get_phy_abilities\t\t= 0x0600,\n-\ti40e_aqc_opc_set_phy_config\t\t= 0x0601,\n-\ti40e_aqc_opc_set_mac_config\t\t= 0x0603,\n-\ti40e_aqc_opc_set_link_restart_an\t= 0x0605,\n-\ti40e_aqc_opc_get_link_status\t\t= 0x0607,\n-\ti40e_aqc_opc_set_phy_int_mask\t\t= 0x0613,\n-\ti40e_aqc_opc_get_local_advt_reg\t\t= 0x0614,\n-\ti40e_aqc_opc_set_local_advt_reg\t\t= 0x0615,\n-\ti40e_aqc_opc_get_partner_advt\t\t= 0x0616,\n-\ti40e_aqc_opc_set_lb_modes\t\t= 0x0618,\n-\ti40e_aqc_opc_get_phy_wol_caps\t\t= 0x0621,\n-\ti40e_aqc_opc_set_phy_debug\t\t= 0x0622,\n-\ti40e_aqc_opc_upload_ext_phy_fm\t\t= 0x0625,\n-\ti40e_aqc_opc_run_phy_activity\t\t= 0x0626,\n-\ti40e_aqc_opc_set_phy_register\t\t= 0x0628,\n-\ti40e_aqc_opc_get_phy_register\t\t= 0x0629,\n+\tiavf_aqc_opc_get_phy_abilities\t\t= 0x0600,\n+\tiavf_aqc_opc_set_phy_config\t\t= 0x0601,\n+\tiavf_aqc_opc_set_mac_config\t\t= 0x0603,\n+\tiavf_aqc_opc_set_link_restart_an\t= 0x0605,\n+\tiavf_aqc_opc_get_link_status\t\t= 0x0607,\n+\tiavf_aqc_opc_set_phy_int_mask\t\t= 0x0613,\n+\tiavf_aqc_opc_get_local_advt_reg\t\t= 0x0614,\n+\tiavf_aqc_opc_set_local_advt_reg\t\t= 0x0615,\n+\tiavf_aqc_opc_get_partner_advt\t\t= 0x0616,\n+\tiavf_aqc_opc_set_lb_modes\t\t= 0x0618,\n+\tiavf_aqc_opc_get_phy_wol_caps\t\t= 0x0621,\n+\tiavf_aqc_opc_set_phy_debug\t\t= 0x0622,\n+\tiavf_aqc_opc_upload_ext_phy_fm\t\t= 0x0625,\n+\tiavf_aqc_opc_run_phy_activity\t\t= 0x0626,\n+\tiavf_aqc_opc_set_phy_register\t\t= 0x0628,\n+\tiavf_aqc_opc_get_phy_register\t\t= 0x0629,\n \n \t/* NVM commands */\n-\ti40e_aqc_opc_nvm_read\t\t\t= 0x0701,\n-\ti40e_aqc_opc_nvm_erase\t\t\t= 0x0702,\n-\ti40e_aqc_opc_nvm_update\t\t\t= 0x0703,\n-\ti40e_aqc_opc_nvm_config_read\t\t= 0x0704,\n-\ti40e_aqc_opc_nvm_config_write\t\t= 0x0705,\n-\ti40e_aqc_opc_oem_post_update\t\t= 0x0720,\n-\ti40e_aqc_opc_thermal_sensor\t\t= 0x0721,\n+\tiavf_aqc_opc_nvm_read\t\t\t= 0x0701,\n+\tiavf_aqc_opc_nvm_erase\t\t\t= 0x0702,\n+\tiavf_aqc_opc_nvm_update\t\t\t= 0x0703,\n+\tiavf_aqc_opc_nvm_config_read\t\t= 0x0704,\n+\tiavf_aqc_opc_nvm_config_write\t\t= 0x0705,\n+\tiavf_aqc_opc_oem_post_update\t\t= 0x0720,\n+\tiavf_aqc_opc_thermal_sensor\t\t= 0x0721,\n \n \t/* virtualization commands */\n-\ti40e_aqc_opc_send_msg_to_pf\t\t= 0x0801,\n-\ti40e_aqc_opc_send_msg_to_vf\t\t= 0x0802,\n-\ti40e_aqc_opc_send_msg_to_peer\t\t= 0x0803,\n+\tiavf_aqc_opc_send_msg_to_pf\t\t= 0x0801,\n+\tiavf_aqc_opc_send_msg_to_vf\t\t= 0x0802,\n+\tiavf_aqc_opc_send_msg_to_peer\t\t= 0x0803,\n \n \t/* alternate structure */\n-\ti40e_aqc_opc_alternate_write\t\t= 0x0900,\n-\ti40e_aqc_opc_alternate_write_indirect\t= 0x0901,\n-\ti40e_aqc_opc_alternate_read\t\t= 0x0902,\n-\ti40e_aqc_opc_alternate_read_indirect\t= 0x0903,\n-\ti40e_aqc_opc_alternate_write_done\t= 0x0904,\n-\ti40e_aqc_opc_alternate_set_mode\t\t= 0x0905,\n-\ti40e_aqc_opc_alternate_clear_port\t= 0x0906,\n+\tiavf_aqc_opc_alternate_write\t\t= 0x0900,\n+\tiavf_aqc_opc_alternate_write_indirect\t= 0x0901,\n+\tiavf_aqc_opc_alternate_read\t\t= 0x0902,\n+\tiavf_aqc_opc_alternate_read_indirect\t= 0x0903,\n+\tiavf_aqc_opc_alternate_write_done\t= 0x0904,\n+\tiavf_aqc_opc_alternate_set_mode\t\t= 0x0905,\n+\tiavf_aqc_opc_alternate_clear_port\t= 0x0906,\n \n \t/* LLDP commands */\n-\ti40e_aqc_opc_lldp_get_mib\t= 0x0A00,\n-\ti40e_aqc_opc_lldp_update_mib\t= 0x0A01,\n-\ti40e_aqc_opc_lldp_add_tlv\t= 0x0A02,\n-\ti40e_aqc_opc_lldp_update_tlv\t= 0x0A03,\n-\ti40e_aqc_opc_lldp_delete_tlv\t= 0x0A04,\n-\ti40e_aqc_opc_lldp_stop\t\t= 0x0A05,\n-\ti40e_aqc_opc_lldp_start\t\t= 0x0A06,\n+\tiavf_aqc_opc_lldp_get_mib\t= 0x0A00,\n+\tiavf_aqc_opc_lldp_update_mib\t= 0x0A01,\n+\tiavf_aqc_opc_lldp_add_tlv\t= 0x0A02,\n+\tiavf_aqc_opc_lldp_update_tlv\t= 0x0A03,\n+\tiavf_aqc_opc_lldp_delete_tlv\t= 0x0A04,\n+\tiavf_aqc_opc_lldp_stop\t\t= 0x0A05,\n+\tiavf_aqc_opc_lldp_start\t\t= 0x0A06,\n \n \t/* Tunnel commands */\n-\ti40e_aqc_opc_add_udp_tunnel\t= 0x0B00,\n-\ti40e_aqc_opc_del_udp_tunnel\t= 0x0B01,\n-\ti40e_aqc_opc_set_rss_key\t= 0x0B02,\n-\ti40e_aqc_opc_set_rss_lut\t= 0x0B03,\n-\ti40e_aqc_opc_get_rss_key\t= 0x0B04,\n-\ti40e_aqc_opc_get_rss_lut\t= 0x0B05,\n+\tiavf_aqc_opc_add_udp_tunnel\t= 0x0B00,\n+\tiavf_aqc_opc_del_udp_tunnel\t= 0x0B01,\n+\tiavf_aqc_opc_set_rss_key\t= 0x0B02,\n+\tiavf_aqc_opc_set_rss_lut\t= 0x0B03,\n+\tiavf_aqc_opc_get_rss_key\t= 0x0B04,\n+\tiavf_aqc_opc_get_rss_lut\t= 0x0B05,\n \n \t/* Async Events */\n-\ti40e_aqc_opc_event_lan_overflow\t\t= 0x1001,\n+\tiavf_aqc_opc_event_lan_overflow\t\t= 0x1001,\n \n \t/* OEM commands */\n-\ti40e_aqc_opc_oem_parameter_change\t= 0xFE00,\n-\ti40e_aqc_opc_oem_device_status_change\t= 0xFE01,\n-\ti40e_aqc_opc_oem_ocsd_initialize\t= 0xFE02,\n-\ti40e_aqc_opc_oem_ocbb_initialize\t= 0xFE03,\n+\tiavf_aqc_opc_oem_parameter_change\t= 0xFE00,\n+\tiavf_aqc_opc_oem_device_status_change\t= 0xFE01,\n+\tiavf_aqc_opc_oem_ocsd_initialize\t= 0xFE02,\n+\tiavf_aqc_opc_oem_ocbb_initialize\t= 0xFE03,\n \n \t/* debug commands */\n-\ti40e_aqc_opc_debug_read_reg\t\t= 0xFF03,\n-\ti40e_aqc_opc_debug_write_reg\t\t= 0xFF04,\n-\ti40e_aqc_opc_debug_modify_reg\t\t= 0xFF07,\n-\ti40e_aqc_opc_debug_dump_internals\t= 0xFF08,\n+\tiavf_aqc_opc_debug_read_reg\t\t= 0xFF03,\n+\tiavf_aqc_opc_debug_write_reg\t\t= 0xFF04,\n+\tiavf_aqc_opc_debug_modify_reg\t\t= 0xFF07,\n+\tiavf_aqc_opc_debug_dump_internals\t= 0xFF08,\n };\n \n /* command structures and indirect data structures */\n@@ -301,131 +301,131 @@ enum i40e_admin_queue_opc {\n  * structure is not of the correct size, otherwise it creates an enum that is\n  * never used.\n  */\n-#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \\\n-\t{ i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }\n+#define IAVF_CHECK_STRUCT_LEN(n, X) enum iavf_static_assert_enum_##X \\\n+\t{ iavf_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }\n \n /* This macro is used extensively to ensure that command structures are 16\n  * bytes in length as they have to map to the raw array of that size.\n  */\n-#define I40E_CHECK_CMD_LENGTH(X)\tI40E_CHECK_STRUCT_LEN(16, X)\n+#define IAVF_CHECK_CMD_LENGTH(X)\tIAVF_CHECK_STRUCT_LEN(16, X)\n \n /* Queue Shutdown (direct 0x0003) */\n-struct i40e_aqc_queue_shutdown {\n+struct iavf_aqc_queue_shutdown {\n \t__le32\tdriver_unloading;\n-#define I40E_AQ_DRIVER_UNLOADING\t0x1\n+#define IAVF_AQ_DRIVER_UNLOADING\t0x1\n \tu8\treserved[12];\n };\n \n-I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);\n+IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown);\n \n-struct i40e_aqc_vsi_properties_data {\n+struct iavf_aqc_vsi_properties_data {\n \t/* first 96 byte are written by SW */\n \t__le16\tvalid_sections;\n-#define I40E_AQ_VSI_PROP_SWITCH_VALID\t\t0x0001\n-#define I40E_AQ_VSI_PROP_SECURITY_VALID\t\t0x0002\n-#define I40E_AQ_VSI_PROP_VLAN_VALID\t\t0x0004\n-#define I40E_AQ_VSI_PROP_CAS_PV_VALID\t\t0x0008\n-#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID\t0x0010\n-#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID\t0x0020\n-#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID\t0x0040\n-#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID\t0x0080\n-#define I40E_AQ_VSI_PROP_OUTER_UP_VALID\t\t0x0100\n-#define I40E_AQ_VSI_PROP_SCHED_VALID\t\t0x0200\n+#define IAVF_AQ_VSI_PROP_SWITCH_VALID\t\t0x0001\n+#define IAVF_AQ_VSI_PROP_SECURITY_VALID\t\t0x0002\n+#define IAVF_AQ_VSI_PROP_VLAN_VALID\t\t0x0004\n+#define IAVF_AQ_VSI_PROP_CAS_PV_VALID\t\t0x0008\n+#define IAVF_AQ_VSI_PROP_INGRESS_UP_VALID\t0x0010\n+#define IAVF_AQ_VSI_PROP_EGRESS_UP_VALID\t0x0020\n+#define IAVF_AQ_VSI_PROP_QUEUE_MAP_VALID\t0x0040\n+#define IAVF_AQ_VSI_PROP_QUEUE_OPT_VALID\t0x0080\n+#define IAVF_AQ_VSI_PROP_OUTER_UP_VALID\t\t0x0100\n+#define IAVF_AQ_VSI_PROP_SCHED_VALID\t\t0x0200\n \t/* switch section */\n \t__le16\tswitch_id; /* 12bit id combined with flags below */\n-#define I40E_AQ_VSI_SW_ID_SHIFT\t\t0x0000\n-#define I40E_AQ_VSI_SW_ID_MASK\t\t(0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)\n-#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG\t0x1000\n-#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB\t0x2000\n-#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB\t0x4000\n+#define IAVF_AQ_VSI_SW_ID_SHIFT\t\t0x0000\n+#define IAVF_AQ_VSI_SW_ID_MASK\t\t(0xFFF << IAVF_AQ_VSI_SW_ID_SHIFT)\n+#define IAVF_AQ_VSI_SW_ID_FLAG_NOT_STAG\t0x1000\n+#define IAVF_AQ_VSI_SW_ID_FLAG_ALLOW_LB\t0x2000\n+#define IAVF_AQ_VSI_SW_ID_FLAG_LOCAL_LB\t0x4000\n \tu8\tsw_reserved[2];\n \t/* security section */\n \tu8\tsec_flags;\n-#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD\t0x01\n-#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK\t0x02\n-#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK\t0x04\n+#define IAVF_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD\t0x01\n+#define IAVF_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK\t0x02\n+#define IAVF_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK\t0x04\n \tu8\tsec_reserved;\n \t/* VLAN section */\n \t__le16\tpvid; /* VLANS include priority bits */\n \t__le16\tfcoe_pvid;\n \tu8\tport_vlan_flags;\n-#define I40E_AQ_VSI_PVLAN_MODE_SHIFT\t0x00\n-#define I40E_AQ_VSI_PVLAN_MODE_MASK\t(0x03 << \\\n-\t\t\t\t\t I40E_AQ_VSI_PVLAN_MODE_SHIFT)\n-#define I40E_AQ_VSI_PVLAN_MODE_TAGGED\t0x01\n-#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED\t0x02\n-#define I40E_AQ_VSI_PVLAN_MODE_ALL\t0x03\n-#define I40E_AQ_VSI_PVLAN_INSERT_PVID\t0x04\n-#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT\t0x03\n-#define I40E_AQ_VSI_PVLAN_EMOD_MASK\t(0x3 << \\\n-\t\t\t\t\t I40E_AQ_VSI_PVLAN_EMOD_SHIFT)\n-#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH\t0x0\n-#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP\t0x08\n-#define I40E_AQ_VSI_PVLAN_EMOD_STR\t0x10\n-#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING\t0x18\n+#define IAVF_AQ_VSI_PVLAN_MODE_SHIFT\t0x00\n+#define IAVF_AQ_VSI_PVLAN_MODE_MASK\t(0x03 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_PVLAN_MODE_SHIFT)\n+#define IAVF_AQ_VSI_PVLAN_MODE_TAGGED\t0x01\n+#define IAVF_AQ_VSI_PVLAN_MODE_UNTAGGED\t0x02\n+#define IAVF_AQ_VSI_PVLAN_MODE_ALL\t0x03\n+#define IAVF_AQ_VSI_PVLAN_INSERT_PVID\t0x04\n+#define IAVF_AQ_VSI_PVLAN_EMOD_SHIFT\t0x03\n+#define IAVF_AQ_VSI_PVLAN_EMOD_MASK\t(0x3 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_PVLAN_EMOD_SHIFT)\n+#define IAVF_AQ_VSI_PVLAN_EMOD_STR_BOTH\t0x0\n+#define IAVF_AQ_VSI_PVLAN_EMOD_STR_UP\t0x08\n+#define IAVF_AQ_VSI_PVLAN_EMOD_STR\t0x10\n+#define IAVF_AQ_VSI_PVLAN_EMOD_NOTHING\t0x18\n \tu8\tpvlan_reserved[3];\n \t/* ingress egress up sections */\n \t__le32\tingress_table; /* bitmap, 3 bits per up */\n-#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT\t0\n-#define I40E_AQ_VSI_UP_TABLE_UP0_MASK\t(0x7 << \\\n-\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT\t3\n-#define I40E_AQ_VSI_UP_TABLE_UP1_MASK\t(0x7 << \\\n-\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT\t6\n-#define I40E_AQ_VSI_UP_TABLE_UP2_MASK\t(0x7 << \\\n-\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT\t9\n-#define I40E_AQ_VSI_UP_TABLE_UP3_MASK\t(0x7 << \\\n-\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT\t12\n-#define I40E_AQ_VSI_UP_TABLE_UP4_MASK\t(0x7 << \\\n-\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT\t15\n-#define I40E_AQ_VSI_UP_TABLE_UP5_MASK\t(0x7 << \\\n-\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT\t18\n-#define I40E_AQ_VSI_UP_TABLE_UP6_MASK\t(0x7 << \\\n-\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT\t21\n-#define I40E_AQ_VSI_UP_TABLE_UP7_MASK\t(0x7 << \\\n-\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)\n+#define IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT\t0\n+#define IAVF_AQ_VSI_UP_TABLE_UP0_MASK\t(0x7 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT)\n+#define IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT\t3\n+#define IAVF_AQ_VSI_UP_TABLE_UP1_MASK\t(0x7 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT)\n+#define IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT\t6\n+#define IAVF_AQ_VSI_UP_TABLE_UP2_MASK\t(0x7 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT)\n+#define IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT\t9\n+#define IAVF_AQ_VSI_UP_TABLE_UP3_MASK\t(0x7 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT)\n+#define IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT\t12\n+#define IAVF_AQ_VSI_UP_TABLE_UP4_MASK\t(0x7 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT)\n+#define IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT\t15\n+#define IAVF_AQ_VSI_UP_TABLE_UP5_MASK\t(0x7 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT)\n+#define IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT\t18\n+#define IAVF_AQ_VSI_UP_TABLE_UP6_MASK\t(0x7 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT)\n+#define IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT\t21\n+#define IAVF_AQ_VSI_UP_TABLE_UP7_MASK\t(0x7 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT)\n \t__le32\tegress_table;   /* same defines as for ingress table */\n \t/* cascaded PV section */\n \t__le16\tcas_pv_tag;\n \tu8\tcas_pv_flags;\n-#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT\t\t0x00\n-#define I40E_AQ_VSI_CAS_PV_TAGX_MASK\t\t(0x03 << \\\n-\t\t\t\t\t\t I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)\n-#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE\t\t0x00\n-#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE\t\t0x01\n-#define I40E_AQ_VSI_CAS_PV_TAGX_COPY\t\t0x02\n-#define I40E_AQ_VSI_CAS_PV_INSERT_TAG\t\t0x10\n-#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE\t\t0x20\n-#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG\t0x40\n+#define IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT\t\t0x00\n+#define IAVF_AQ_VSI_CAS_PV_TAGX_MASK\t\t(0x03 << \\\n+\t\t\t\t\t\t IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT)\n+#define IAVF_AQ_VSI_CAS_PV_TAGX_LEAVE\t\t0x00\n+#define IAVF_AQ_VSI_CAS_PV_TAGX_REMOVE\t\t0x01\n+#define IAVF_AQ_VSI_CAS_PV_TAGX_COPY\t\t0x02\n+#define IAVF_AQ_VSI_CAS_PV_INSERT_TAG\t\t0x10\n+#define IAVF_AQ_VSI_CAS_PV_ETAG_PRUNE\t\t0x20\n+#define IAVF_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG\t0x40\n \tu8\tcas_pv_reserved;\n \t/* queue mapping section */\n \t__le16\tmapping_flags;\n-#define I40E_AQ_VSI_QUE_MAP_CONTIG\t0x0\n-#define I40E_AQ_VSI_QUE_MAP_NONCONTIG\t0x1\n+#define IAVF_AQ_VSI_QUE_MAP_CONTIG\t0x0\n+#define IAVF_AQ_VSI_QUE_MAP_NONCONTIG\t0x1\n \t__le16\tqueue_mapping[16];\n-#define I40E_AQ_VSI_QUEUE_SHIFT\t\t0x0\n-#define I40E_AQ_VSI_QUEUE_MASK\t\t(0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)\n+#define IAVF_AQ_VSI_QUEUE_SHIFT\t\t0x0\n+#define IAVF_AQ_VSI_QUEUE_MASK\t\t(0x7FF << IAVF_AQ_VSI_QUEUE_SHIFT)\n \t__le16\ttc_mapping[8];\n-#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT\t0\n-#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK\t(0x1FF << \\\n-\t\t\t\t\t I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)\n-#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT\t9\n-#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK\t(0x7 << \\\n-\t\t\t\t\t I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)\n+#define IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT\t0\n+#define IAVF_AQ_VSI_TC_QUE_OFFSET_MASK\t(0x1FF << \\\n+\t\t\t\t\t IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT)\n+#define IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT\t9\n+#define IAVF_AQ_VSI_TC_QUE_NUMBER_MASK\t(0x7 << \\\n+\t\t\t\t\t IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT)\n \t/* queueing option section */\n \tu8\tqueueing_opt_flags;\n-#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA\t0x04\n-#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA\t0x08\n-#define I40E_AQ_VSI_QUE_OPT_TCP_ENA\t0x10\n-#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA\t0x20\n-#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF\t0x00\n-#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI\t0x40\n+#define IAVF_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA\t0x04\n+#define IAVF_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA\t0x08\n+#define IAVF_AQ_VSI_QUE_OPT_TCP_ENA\t0x10\n+#define IAVF_AQ_VSI_QUE_OPT_FCOE_ENA\t0x20\n+#define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_PF\t0x00\n+#define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_VSI\t0x40\n \tu8\tqueueing_opt_reserved[3];\n \t/* scheduler section */\n \tu8\tup_enable_bits;\n@@ -435,18 +435,18 @@ struct i40e_aqc_vsi_properties_data {\n \tu8\tcmd_reserved[8];\n \t/* last 32 bytes are written by FW */\n \t__le16\tqs_handle[8];\n-#define I40E_AQ_VSI_QS_HANDLE_INVALID\t0xFFFF\n+#define IAVF_AQ_VSI_QS_HANDLE_INVALID\t0xFFFF\n \t__le16\tstat_counter_idx;\n \t__le16\tsched_id;\n \tu8\tresp_reserved[12];\n };\n \n-I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);\n+IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data);\n \n /* Get VEB Parameters (direct 0x0232)\n- * uses i40e_aqc_switch_seid for the descriptor\n+ * uses iavf_aqc_switch_seid for the descriptor\n  */\n-struct i40e_aqc_get_veb_parameters_completion {\n+struct iavf_aqc_get_veb_parameters_completion {\n \t__le16\tseid;\n \t__le16\tswitch_id;\n \t__le16\tveb_flags; /* only the first/last flags from 0x0230 is valid */\n@@ -456,75 +456,75 @@ struct i40e_aqc_get_veb_parameters_completion {\n \tu8\treserved[4];\n };\n \n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);\n-\n-#define I40E_LINK_SPEED_100MB_SHIFT\t0x1\n-#define I40E_LINK_SPEED_1000MB_SHIFT\t0x2\n-#define I40E_LINK_SPEED_10GB_SHIFT\t0x3\n-#define I40E_LINK_SPEED_40GB_SHIFT\t0x4\n-#define I40E_LINK_SPEED_20GB_SHIFT\t0x5\n-#define I40E_LINK_SPEED_25GB_SHIFT\t0x6\n-\n-enum i40e_aq_link_speed {\n-\tI40E_LINK_SPEED_UNKNOWN\t= 0,\n-\tI40E_LINK_SPEED_100MB\t= BIT(I40E_LINK_SPEED_100MB_SHIFT),\n-\tI40E_LINK_SPEED_1GB\t= BIT(I40E_LINK_SPEED_1000MB_SHIFT),\n-\tI40E_LINK_SPEED_10GB\t= BIT(I40E_LINK_SPEED_10GB_SHIFT),\n-\tI40E_LINK_SPEED_40GB\t= BIT(I40E_LINK_SPEED_40GB_SHIFT),\n-\tI40E_LINK_SPEED_20GB\t= BIT(I40E_LINK_SPEED_20GB_SHIFT),\n-\tI40E_LINK_SPEED_25GB\t= BIT(I40E_LINK_SPEED_25GB_SHIFT),\n+IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion);\n+\n+#define IAVF_LINK_SPEED_100MB_SHIFT\t0x1\n+#define IAVF_LINK_SPEED_1000MB_SHIFT\t0x2\n+#define IAVF_LINK_SPEED_10GB_SHIFT\t0x3\n+#define IAVF_LINK_SPEED_40GB_SHIFT\t0x4\n+#define IAVF_LINK_SPEED_20GB_SHIFT\t0x5\n+#define IAVF_LINK_SPEED_25GB_SHIFT\t0x6\n+\n+enum iavf_aq_link_speed {\n+\tIAVF_LINK_SPEED_UNKNOWN\t= 0,\n+\tIAVF_LINK_SPEED_100MB\t= BIT(IAVF_LINK_SPEED_100MB_SHIFT),\n+\tIAVF_LINK_SPEED_1GB\t= BIT(IAVF_LINK_SPEED_1000MB_SHIFT),\n+\tIAVF_LINK_SPEED_10GB\t= BIT(IAVF_LINK_SPEED_10GB_SHIFT),\n+\tIAVF_LINK_SPEED_40GB\t= BIT(IAVF_LINK_SPEED_40GB_SHIFT),\n+\tIAVF_LINK_SPEED_20GB\t= BIT(IAVF_LINK_SPEED_20GB_SHIFT),\n+\tIAVF_LINK_SPEED_25GB\t= BIT(IAVF_LINK_SPEED_25GB_SHIFT),\n };\n \n /* Send to PF command (indirect 0x0801) id is only used by PF\n  * Send to VF command (indirect 0x0802) id is only used by PF\n  * Send to Peer PF command (indirect 0x0803)\n  */\n-struct i40e_aqc_pf_vf_message {\n+struct iavf_aqc_pf_vf_message {\n \t__le32\tid;\n \tu8\treserved[4];\n \t__le32\taddr_high;\n \t__le32\taddr_low;\n };\n \n-I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);\n+IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);\n \n-struct i40e_aqc_get_set_rss_key {\n-#define I40E_AQC_SET_RSS_KEY_VSI_VALID\t\tBIT(15)\n-#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT\t0\n-#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK\t(0x3FF << \\\n-\t\t\t\t\tI40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)\n+struct iavf_aqc_get_set_rss_key {\n+#define IAVF_AQC_SET_RSS_KEY_VSI_VALID\t\tBIT(15)\n+#define IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT\t0\n+#define IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK\t(0x3FF << \\\n+\t\t\t\t\tIAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT)\n \t__le16\tvsi_id;\n \tu8\treserved[6];\n \t__le32\taddr_high;\n \t__le32\taddr_low;\n };\n \n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);\n+IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_key);\n \n-struct i40e_aqc_get_set_rss_key_data {\n+struct iavf_aqc_get_set_rss_key_data {\n \tu8 standard_rss_key[0x28];\n \tu8 extended_hash_key[0xc];\n };\n \n-I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);\n+IAVF_CHECK_STRUCT_LEN(0x34, iavf_aqc_get_set_rss_key_data);\n \n-struct  i40e_aqc_get_set_rss_lut {\n-#define I40E_AQC_SET_RSS_LUT_VSI_VALID\t\tBIT(15)\n-#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT\t0\n-#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK\t(0x3FF << \\\n-\t\t\t\t\tI40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)\n+struct  iavf_aqc_get_set_rss_lut {\n+#define IAVF_AQC_SET_RSS_LUT_VSI_VALID\t\tBIT(15)\n+#define IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT\t0\n+#define IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK\t(0x3FF << \\\n+\t\t\t\t\tIAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT)\n \t__le16\tvsi_id;\n-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT\t0\n-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \\\n-\t\t\t\tBIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)\n+#define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT\t0\n+#define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \\\n+\t\t\t\tBIT(IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)\n \n-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI\t0\n-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF\t1\n+#define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI\t0\n+#define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF\t1\n \t__le16\tflags;\n \tu8\treserved[4];\n \t__le32\taddr_high;\n \t__le32\taddr_low;\n };\n \n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);\n-#endif /* _I40E_ADMINQ_CMD_H_ */\n+IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut);\n+#endif /* _IAVF_ADMINQ_CMD_H_ */\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_common.c b/drivers/net/ethernet/intel/iavf/iavf_common.c\nindex 44cd15793bb5..137e06c0c4ee 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_common.c\n+++ b/drivers/net/ethernet/intel/iavf/iavf_common.c\n@@ -44,55 +44,55 @@ enum iavf_status iavf_set_mac_type(struct iavf_hw *hw)\n  * @hw: pointer to the HW structure\n  * @aq_err: the AQ error code to convert\n  **/\n-const char *iavf_aq_str(struct iavf_hw *hw, enum i40e_admin_queue_err aq_err)\n+const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err)\n {\n \tswitch (aq_err) {\n-\tcase I40E_AQ_RC_OK:\n+\tcase IAVF_AQ_RC_OK:\n \t\treturn \"OK\";\n-\tcase I40E_AQ_RC_EPERM:\n-\t\treturn \"I40E_AQ_RC_EPERM\";\n-\tcase I40E_AQ_RC_ENOENT:\n-\t\treturn \"I40E_AQ_RC_ENOENT\";\n-\tcase I40E_AQ_RC_ESRCH:\n-\t\treturn \"I40E_AQ_RC_ESRCH\";\n-\tcase I40E_AQ_RC_EINTR:\n-\t\treturn \"I40E_AQ_RC_EINTR\";\n-\tcase I40E_AQ_RC_EIO:\n-\t\treturn \"I40E_AQ_RC_EIO\";\n-\tcase I40E_AQ_RC_ENXIO:\n-\t\treturn \"I40E_AQ_RC_ENXIO\";\n-\tcase I40E_AQ_RC_E2BIG:\n-\t\treturn \"I40E_AQ_RC_E2BIG\";\n-\tcase I40E_AQ_RC_EAGAIN:\n-\t\treturn \"I40E_AQ_RC_EAGAIN\";\n-\tcase I40E_AQ_RC_ENOMEM:\n-\t\treturn \"I40E_AQ_RC_ENOMEM\";\n-\tcase I40E_AQ_RC_EACCES:\n-\t\treturn \"I40E_AQ_RC_EACCES\";\n-\tcase I40E_AQ_RC_EFAULT:\n-\t\treturn \"I40E_AQ_RC_EFAULT\";\n-\tcase I40E_AQ_RC_EBUSY:\n-\t\treturn \"I40E_AQ_RC_EBUSY\";\n-\tcase I40E_AQ_RC_EEXIST:\n-\t\treturn \"I40E_AQ_RC_EEXIST\";\n-\tcase I40E_AQ_RC_EINVAL:\n-\t\treturn \"I40E_AQ_RC_EINVAL\";\n-\tcase I40E_AQ_RC_ENOTTY:\n-\t\treturn \"I40E_AQ_RC_ENOTTY\";\n-\tcase I40E_AQ_RC_ENOSPC:\n-\t\treturn \"I40E_AQ_RC_ENOSPC\";\n-\tcase I40E_AQ_RC_ENOSYS:\n-\t\treturn \"I40E_AQ_RC_ENOSYS\";\n-\tcase I40E_AQ_RC_ERANGE:\n-\t\treturn \"I40E_AQ_RC_ERANGE\";\n-\tcase I40E_AQ_RC_EFLUSHED:\n-\t\treturn \"I40E_AQ_RC_EFLUSHED\";\n-\tcase I40E_AQ_RC_BAD_ADDR:\n-\t\treturn \"I40E_AQ_RC_BAD_ADDR\";\n-\tcase I40E_AQ_RC_EMODE:\n-\t\treturn \"I40E_AQ_RC_EMODE\";\n-\tcase I40E_AQ_RC_EFBIG:\n-\t\treturn \"I40E_AQ_RC_EFBIG\";\n+\tcase IAVF_AQ_RC_EPERM:\n+\t\treturn \"IAVF_AQ_RC_EPERM\";\n+\tcase IAVF_AQ_RC_ENOENT:\n+\t\treturn \"IAVF_AQ_RC_ENOENT\";\n+\tcase IAVF_AQ_RC_ESRCH:\n+\t\treturn \"IAVF_AQ_RC_ESRCH\";\n+\tcase IAVF_AQ_RC_EINTR:\n+\t\treturn \"IAVF_AQ_RC_EINTR\";\n+\tcase IAVF_AQ_RC_EIO:\n+\t\treturn \"IAVF_AQ_RC_EIO\";\n+\tcase IAVF_AQ_RC_ENXIO:\n+\t\treturn \"IAVF_AQ_RC_ENXIO\";\n+\tcase IAVF_AQ_RC_E2BIG:\n+\t\treturn \"IAVF_AQ_RC_E2BIG\";\n+\tcase IAVF_AQ_RC_EAGAIN:\n+\t\treturn \"IAVF_AQ_RC_EAGAIN\";\n+\tcase IAVF_AQ_RC_ENOMEM:\n+\t\treturn \"IAVF_AQ_RC_ENOMEM\";\n+\tcase IAVF_AQ_RC_EACCES:\n+\t\treturn \"IAVF_AQ_RC_EACCES\";\n+\tcase IAVF_AQ_RC_EFAULT:\n+\t\treturn \"IAVF_AQ_RC_EFAULT\";\n+\tcase IAVF_AQ_RC_EBUSY:\n+\t\treturn \"IAVF_AQ_RC_EBUSY\";\n+\tcase IAVF_AQ_RC_EEXIST:\n+\t\treturn \"IAVF_AQ_RC_EEXIST\";\n+\tcase IAVF_AQ_RC_EINVAL:\n+\t\treturn \"IAVF_AQ_RC_EINVAL\";\n+\tcase IAVF_AQ_RC_ENOTTY:\n+\t\treturn \"IAVF_AQ_RC_ENOTTY\";\n+\tcase IAVF_AQ_RC_ENOSPC:\n+\t\treturn \"IAVF_AQ_RC_ENOSPC\";\n+\tcase IAVF_AQ_RC_ENOSYS:\n+\t\treturn \"IAVF_AQ_RC_ENOSYS\";\n+\tcase IAVF_AQ_RC_ERANGE:\n+\t\treturn \"IAVF_AQ_RC_ERANGE\";\n+\tcase IAVF_AQ_RC_EFLUSHED:\n+\t\treturn \"IAVF_AQ_RC_EFLUSHED\";\n+\tcase IAVF_AQ_RC_BAD_ADDR:\n+\t\treturn \"IAVF_AQ_RC_BAD_ADDR\";\n+\tcase IAVF_AQ_RC_EMODE:\n+\t\treturn \"IAVF_AQ_RC_EMODE\";\n+\tcase IAVF_AQ_RC_EFBIG:\n+\t\treturn \"IAVF_AQ_RC_EFBIG\";\n \t}\n \n \tsnprintf(hw->err_str, sizeof(hw->err_str), \"%d\", aq_err);\n@@ -260,7 +260,7 @@ const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status stat_err)\n void iavf_debug_aq(struct iavf_hw *hw, enum iavf_debug_mask mask, void *desc,\n \t\t   void *buffer, u16 buf_len)\n {\n-\tstruct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;\n+\tstruct iavf_aq_desc *aq_desc = (struct iavf_aq_desc *)desc;\n \tu8 *buf = (u8 *)buffer;\n \n \tif ((!(mask & hw->debug_mask)) || !desc)\n@@ -329,15 +329,15 @@ bool iavf_check_asq_alive(struct iavf_hw *hw)\n  **/\n enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw, bool unloading)\n {\n-\tstruct i40e_aq_desc desc;\n-\tstruct i40e_aqc_queue_shutdown *cmd =\n-\t\t(struct i40e_aqc_queue_shutdown *)&desc.params.raw;\n+\tstruct iavf_aq_desc desc;\n+\tstruct iavf_aqc_queue_shutdown *cmd =\n+\t\t(struct iavf_aqc_queue_shutdown *)&desc.params.raw;\n \tenum iavf_status status;\n \n-\tiavf_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_queue_shutdown);\n+\tiavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_queue_shutdown);\n \n \tif (unloading)\n-\t\tcmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);\n+\t\tcmd->driver_unloading = cpu_to_le32(IAVF_AQ_DRIVER_UNLOADING);\n \tstatus = iavf_asq_send_command(hw, &desc, NULL, 0, NULL);\n \n \treturn status;\n@@ -360,37 +360,37 @@ static enum iavf_status iavf_aq_get_set_rss_lut(struct iavf_hw *hw,\n \t\t\t\t\t\tbool set)\n {\n \tenum iavf_status status;\n-\tstruct i40e_aq_desc desc;\n-\tstruct i40e_aqc_get_set_rss_lut *cmd_resp =\n-\t\t   (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;\n+\tstruct iavf_aq_desc desc;\n+\tstruct iavf_aqc_get_set_rss_lut *cmd_resp =\n+\t\t   (struct iavf_aqc_get_set_rss_lut *)&desc.params.raw;\n \n \tif (set)\n \t\tiavf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t\t\t  i40e_aqc_opc_set_rss_lut);\n+\t\t\t\t\t\t  iavf_aqc_opc_set_rss_lut);\n \telse\n \t\tiavf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t\t\t  i40e_aqc_opc_get_rss_lut);\n+\t\t\t\t\t\t  iavf_aqc_opc_get_rss_lut);\n \n \t/* Indirect command */\n-\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);\n-\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);\n+\tdesc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_BUF);\n+\tdesc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_RD);\n \n \tcmd_resp->vsi_id =\n \t\t\tcpu_to_le16((u16)((vsi_id <<\n-\t\t\t\t\t  I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &\n-\t\t\t\t\t  I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));\n-\tcmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);\n+\t\t\t\t\t  IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &\n+\t\t\t\t\t  IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK));\n+\tcmd_resp->vsi_id |= cpu_to_le16((u16)IAVF_AQC_SET_RSS_LUT_VSI_VALID);\n \n \tif (pf_lut)\n \t\tcmd_resp->flags |= cpu_to_le16((u16)\n-\t\t\t\t\t((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<\n-\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &\n-\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));\n+\t\t\t\t\t((IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<\n+\t\t\t\t\tIAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &\n+\t\t\t\t\tIAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));\n \telse\n \t\tcmd_resp->flags |= cpu_to_le16((u16)\n-\t\t\t\t\t((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<\n-\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &\n-\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));\n+\t\t\t\t\t((IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<\n+\t\t\t\t\tIAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &\n+\t\t\t\t\tIAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));\n \n \tstatus = iavf_asq_send_command(hw, &desc, lut, lut_size, NULL);\n \n@@ -441,31 +441,31 @@ enum iavf_status iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 vsi_id,\n  **/\n static enum\n iavf_status iavf_aq_get_set_rss_key(struct iavf_hw *hw, u16 vsi_id,\n-\t\t\t\t    struct i40e_aqc_get_set_rss_key_data *key,\n+\t\t\t\t    struct iavf_aqc_get_set_rss_key_data *key,\n \t\t\t\t    bool set)\n {\n \tenum iavf_status status;\n-\tstruct i40e_aq_desc desc;\n-\tstruct i40e_aqc_get_set_rss_key *cmd_resp =\n-\t\t\t(struct i40e_aqc_get_set_rss_key *)&desc.params.raw;\n-\tu16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);\n+\tstruct iavf_aq_desc desc;\n+\tstruct iavf_aqc_get_set_rss_key *cmd_resp =\n+\t\t\t(struct iavf_aqc_get_set_rss_key *)&desc.params.raw;\n+\tu16 key_size = sizeof(struct iavf_aqc_get_set_rss_key_data);\n \n \tif (set)\n \t\tiavf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t\t\t  i40e_aqc_opc_set_rss_key);\n+\t\t\t\t\t\t  iavf_aqc_opc_set_rss_key);\n \telse\n \t\tiavf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t\t\t  i40e_aqc_opc_get_rss_key);\n+\t\t\t\t\t\t  iavf_aqc_opc_get_rss_key);\n \n \t/* Indirect command */\n-\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);\n-\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);\n+\tdesc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_BUF);\n+\tdesc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_RD);\n \n \tcmd_resp->vsi_id =\n \t\t\tcpu_to_le16((u16)((vsi_id <<\n-\t\t\t\t\t  I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &\n-\t\t\t\t\t  I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));\n-\tcmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);\n+\t\t\t\t\t  IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &\n+\t\t\t\t\t  IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK));\n+\tcmd_resp->vsi_id |= cpu_to_le16((u16)IAVF_AQC_SET_RSS_KEY_VSI_VALID);\n \n \tstatus = iavf_asq_send_command(hw, &desc, key, key_size, NULL);\n \n@@ -480,7 +480,7 @@ iavf_status iavf_aq_get_set_rss_key(struct iavf_hw *hw, u16 vsi_id,\n  *\n  **/\n enum iavf_status iavf_aq_get_rss_key(struct iavf_hw *hw, u16 vsi_id,\n-\t\t\t\t     struct i40e_aqc_get_set_rss_key_data *key)\n+\t\t\t\t     struct iavf_aqc_get_set_rss_key_data *key)\n {\n \treturn iavf_aq_get_set_rss_key(hw, vsi_id, key, false);\n }\n@@ -494,7 +494,7 @@ enum iavf_status iavf_aq_get_rss_key(struct iavf_hw *hw, u16 vsi_id,\n  * set the RSS key per VSI\n  **/\n enum iavf_status iavf_aq_set_rss_key(struct iavf_hw *hw, u16 vsi_id,\n-\t\t\t\t     struct i40e_aqc_get_set_rss_key_data *key)\n+\t\t\t\t     struct iavf_aqc_get_set_rss_key_data *key)\n {\n \treturn iavf_aq_get_set_rss_key(hw, vsi_id, key, true);\n }\n@@ -881,21 +881,21 @@ enum iavf_status iavf_aq_send_msg_to_pf(struct iavf_hw *hw,\n \t\t\t\t\tenum virtchnl_ops v_opcode,\n \t\t\t\t\tenum iavf_status v_retval,\n \t\t\t\t\tu8 *msg, u16 msglen,\n-\t\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n+\t\t\t\t\tstruct iavf_asq_cmd_details *cmd_details)\n {\n-\tstruct i40e_asq_cmd_details details;\n-\tstruct i40e_aq_desc desc;\n+\tstruct iavf_asq_cmd_details details;\n+\tstruct iavf_aq_desc desc;\n \tenum iavf_status status;\n \n-\tiavf_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);\n-\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);\n+\tiavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_send_msg_to_pf);\n+\tdesc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_SI);\n \tdesc.cookie_high = cpu_to_le32(v_opcode);\n \tdesc.cookie_low = cpu_to_le32(v_retval);\n \tif (msglen) {\n-\t\tdesc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF\n-\t\t\t\t\t\t| I40E_AQ_FLAG_RD));\n-\t\tif (msglen > I40E_AQ_LARGE_BUF)\n-\t\t\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);\n+\t\tdesc.flags |= cpu_to_le16((u16)(IAVF_AQ_FLAG_BUF\n+\t\t\t\t\t\t| IAVF_AQ_FLAG_RD));\n+\t\tif (msglen > IAVF_AQ_LARGE_BUF)\n+\t\t\tdesc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_LB);\n \t\tdesc.datalen = cpu_to_le16(msglen);\n \t}\n \tif (!cmd_details) {\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_ethtool.c b/drivers/net/ethernet/intel/iavf/iavf_ethtool.c\nindex 9f87304109fe..5bdcd78f216d 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_ethtool.c\n+++ b/drivers/net/ethernet/intel/iavf/iavf_ethtool.c\n@@ -280,10 +280,10 @@ static int iavf_get_link_ksettings(struct net_device *netdev,\n \tcmd->base.port = PORT_NONE;\n \t/* Set speed and duplex */\n \tswitch (adapter->link_speed) {\n-\tcase I40E_LINK_SPEED_40GB:\n+\tcase IAVF_LINK_SPEED_40GB:\n \t\tcmd->base.speed = SPEED_40000;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_25GB:\n+\tcase IAVF_LINK_SPEED_25GB:\n #ifdef SPEED_25000\n \t\tcmd->base.speed = SPEED_25000;\n #else\n@@ -291,16 +291,16 @@ static int iavf_get_link_ksettings(struct net_device *netdev,\n \t\t\t    \"Speed is 25G, display not supported by this version of ethtool.\\n\");\n #endif\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_20GB:\n+\tcase IAVF_LINK_SPEED_20GB:\n \t\tcmd->base.speed = SPEED_20000;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_10GB:\n+\tcase IAVF_LINK_SPEED_10GB:\n \t\tcmd->base.speed = SPEED_10000;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_1GB:\n+\tcase IAVF_LINK_SPEED_1GB:\n \t\tcmd->base.speed = SPEED_1000;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_100MB:\n+\tcase IAVF_LINK_SPEED_100MB:\n \t\tcmd->base.speed = SPEED_100;\n \t\tbreak;\n \tdefault:\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_main.c b/drivers/net/ethernet/intel/iavf/iavf_main.c\nindex ab4e3573f9db..d1f4a3329abb 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_main.c\n+++ b/drivers/net/ethernet/intel/iavf/iavf_main.c\n@@ -1229,8 +1229,8 @@ static int iavf_set_interrupt_capability(struct iavf_adapter *adapter)\n  **/\n static int iavf_config_rss_aq(struct iavf_adapter *adapter)\n {\n-\tstruct i40e_aqc_get_set_rss_key_data *rss_key =\n-\t\t(struct i40e_aqc_get_set_rss_key_data *)adapter->rss_key;\n+\tstruct iavf_aqc_get_set_rss_key_data *rss_key =\n+\t\t(struct iavf_aqc_get_set_rss_key_data *)adapter->rss_key;\n \tstruct iavf_hw *hw = &adapter->hw;\n \tint ret = 0;\n \n@@ -2022,7 +2022,7 @@ static void iavf_adminq_task(struct work_struct *work)\n \tstruct iavf_adapter *adapter =\n \t\tcontainer_of(work, struct iavf_adapter, adminq_task);\n \tstruct iavf_hw *hw = &adapter->hw;\n-\tstruct i40e_arq_event_info event;\n+\tstruct iavf_arq_event_info event;\n \tenum virtchnl_ops v_op;\n \tenum iavf_status ret, v_ret;\n \tu32 val, oldval;\n@@ -2241,22 +2241,22 @@ static int iavf_validate_tx_bandwidth(struct iavf_adapter *adapter,\n \tint speed = 0, ret = 0;\n \n \tswitch (adapter->link_speed) {\n-\tcase I40E_LINK_SPEED_40GB:\n+\tcase IAVF_LINK_SPEED_40GB:\n \t\tspeed = 40000;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_25GB:\n+\tcase IAVF_LINK_SPEED_25GB:\n \t\tspeed = 25000;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_20GB:\n+\tcase IAVF_LINK_SPEED_20GB:\n \t\tspeed = 20000;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_10GB:\n+\tcase IAVF_LINK_SPEED_10GB:\n \t\tspeed = 10000;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_1GB:\n+\tcase IAVF_LINK_SPEED_1GB:\n \t\tspeed = 1000;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_100MB:\n+\tcase IAVF_LINK_SPEED_100MB:\n \t\tspeed = 100;\n \t\tbreak;\n \tdefault:\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_prototype.h b/drivers/net/ethernet/intel/iavf/iavf_prototype.h\nindex 0dea4419c01f..edebfbbcffdc 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_prototype.h\n+++ b/drivers/net/ethernet/intel/iavf/iavf_prototype.h\n@@ -20,13 +20,13 @@ enum iavf_status iavf_init_adminq(struct iavf_hw *hw);\n enum iavf_status iavf_shutdown_adminq(struct iavf_hw *hw);\n void iavf_adminq_init_ring_data(struct iavf_hw *hw);\n enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,\n-\t\t\t\t\tstruct i40e_arq_event_info *e,\n+\t\t\t\t\tstruct iavf_arq_event_info *e,\n \t\t\t\t\tu16 *events_pending);\n enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,\n-\t\t\t\t       struct i40e_aq_desc *desc,\n+\t\t\t\t       struct iavf_aq_desc *desc,\n \t\t\t\t       void *buff, /* can be NULL */\n \t\t\t\t       u16 buff_size,\n-\t\t\t\t       struct i40e_asq_cmd_details *cmd_details);\n+\t\t\t\t       struct iavf_asq_cmd_details *cmd_details);\n bool iavf_asq_done(struct iavf_hw *hw);\n \n /* debug function for adminq */\n@@ -37,7 +37,7 @@ void iavf_idle_aq(struct iavf_hw *hw);\n void iavf_resume_aq(struct iavf_hw *hw);\n bool iavf_check_asq_alive(struct iavf_hw *hw);\n enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw, bool unloading);\n-const char *iavf_aq_str(struct iavf_hw *hw, enum i40e_admin_queue_err aq_err);\n+const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err);\n const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status stat_err);\n \n enum iavf_status iavf_aq_get_rss_lut(struct iavf_hw *hw, u16 seid,\n@@ -45,9 +45,9 @@ enum iavf_status iavf_aq_get_rss_lut(struct iavf_hw *hw, u16 seid,\n enum iavf_status iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 seid,\n \t\t\t\t     bool pf_lut, u8 *lut, u16 lut_size);\n enum iavf_status iavf_aq_get_rss_key(struct iavf_hw *hw, u16 seid,\n-\t\t\t\t     struct i40e_aqc_get_set_rss_key_data *key);\n+\t\t\t\t     struct iavf_aqc_get_set_rss_key_data *key);\n enum iavf_status iavf_aq_set_rss_key(struct iavf_hw *hw, u16 seid,\n-\t\t\t\t     struct i40e_aqc_get_set_rss_key_data *key);\n+\t\t\t\t     struct iavf_aqc_get_set_rss_key_data *key);\n \n enum iavf_status iavf_set_mac_type(struct iavf_hw *hw);\n \n@@ -65,5 +65,5 @@ enum iavf_status iavf_aq_send_msg_to_pf(struct iavf_hw *hw,\n \t\t\t\t\tenum virtchnl_ops v_opcode,\n \t\t\t\t\tenum iavf_status v_retval,\n \t\t\t\t\tu8 *msg, u16 msglen,\n-\t\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n+\t\t\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n #endif /* _IAVF_PROTOTYPE_H_ */\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_txrx.c b/drivers/net/ethernet/intel/iavf/iavf_txrx.c\nindex b64187753ad6..e0fb509b6fe1 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_txrx.c\n+++ b/drivers/net/ethernet/intel/iavf/iavf_txrx.c\n@@ -379,19 +379,19 @@ static inline unsigned int iavf_itr_divisor(struct iavf_q_vector *q_vector)\n \tunsigned int divisor;\n \n \tswitch (q_vector->adapter->link_speed) {\n-\tcase I40E_LINK_SPEED_40GB:\n+\tcase IAVF_LINK_SPEED_40GB:\n \t\tdivisor = IAVF_ITR_ADAPTIVE_MIN_INC * 1024;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_25GB:\n-\tcase I40E_LINK_SPEED_20GB:\n+\tcase IAVF_LINK_SPEED_25GB:\n+\tcase IAVF_LINK_SPEED_20GB:\n \t\tdivisor = IAVF_ITR_ADAPTIVE_MIN_INC * 512;\n \t\tbreak;\n \tdefault:\n-\tcase I40E_LINK_SPEED_10GB:\n+\tcase IAVF_LINK_SPEED_10GB:\n \t\tdivisor = IAVF_ITR_ADAPTIVE_MIN_INC * 256;\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_1GB:\n-\tcase I40E_LINK_SPEED_100MB:\n+\tcase IAVF_LINK_SPEED_1GB:\n+\tcase IAVF_LINK_SPEED_100MB:\n \t\tdivisor = IAVF_ITR_ADAPTIVE_MIN_INC * 32;\n \t\tbreak;\n \t}\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_type.h b/drivers/net/ethernet/intel/iavf/iavf_type.h\nindex 58b3efd1ed04..4bc05d2837d7 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_type.h\n+++ b/drivers/net/ethernet/intel/iavf/iavf_type.h\n@@ -21,7 +21,7 @@\n \n /* forward declaration */\n struct iavf_hw;\n-typedef void (*I40E_ADMINQ_CALLBACK)(struct iavf_hw *, struct i40e_aq_desc *);\n+typedef void (*I40E_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *);\n \n /* Data type manipulation macros. */\n \ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c b/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c\nindex 95457869f249..47df277e12d7 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c\n+++ b/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c\n@@ -67,7 +67,7 @@ int iavf_verify_api_ver(struct iavf_adapter *adapter)\n {\n \tstruct virtchnl_version_info *pf_vvi;\n \tstruct iavf_hw *hw = &adapter->hw;\n-\tstruct i40e_arq_event_info event;\n+\tstruct iavf_arq_event_info event;\n \tenum virtchnl_ops op;\n \tenum iavf_status err;\n \n@@ -189,7 +189,7 @@ static void iavf_validate_num_queues(struct iavf_adapter *adapter)\n int iavf_get_vf_config(struct iavf_adapter *adapter)\n {\n \tstruct iavf_hw *hw = &adapter->hw;\n-\tstruct i40e_arq_event_info event;\n+\tstruct iavf_arq_event_info event;\n \tenum virtchnl_ops op;\n \tenum iavf_status err;\n \tu16 len;\n@@ -938,22 +938,22 @@ static void iavf_print_link_message(struct iavf_adapter *adapter)\n \t}\n \n \tswitch (adapter->link_speed) {\n-\tcase I40E_LINK_SPEED_40GB:\n+\tcase IAVF_LINK_SPEED_40GB:\n \t\tspeed = \"40 G\";\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_25GB:\n+\tcase IAVF_LINK_SPEED_25GB:\n \t\tspeed = \"25 G\";\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_20GB:\n+\tcase IAVF_LINK_SPEED_20GB:\n \t\tspeed = \"20 G\";\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_10GB:\n+\tcase IAVF_LINK_SPEED_10GB:\n \t\tspeed = \"10 G\";\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_1GB:\n+\tcase IAVF_LINK_SPEED_1GB:\n \t\tspeed = \"1000 M\";\n \t\tbreak;\n-\tcase I40E_LINK_SPEED_100MB:\n+\tcase IAVF_LINK_SPEED_100MB:\n \t\tspeed = \"100 M\";\n \t\tbreak;\n \tdefault:\n",
    "prefixes": [
        "next",
        "S4",
        "iavf",
        "4/9"
    ]
}