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GET /api/patches/1086464/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 1086464,
    "url": "http://patchwork.ozlabs.org/api/patches/1086464/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190416172439.27908-11-anirudh.venkataramanan@intel.com/",
    "project": {
        "id": 46,
        "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api",
        "name": "Intel Wired Ethernet development",
        "link_name": "intel-wired-lan",
        "list_id": "intel-wired-lan.osuosl.org",
        "list_email": "intel-wired-lan@osuosl.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20190416172439.27908-11-anirudh.venkataramanan@intel.com>",
    "list_archive_url": null,
    "date": "2019-04-16T17:24:34",
    "name": "[S19,10/15] ice: Reorganize tx_buf and ring structs",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "d1a353c581f09cc7d6da0073f63949227151de64",
    "submitter": {
        "id": 73601,
        "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api",
        "name": "Anirudh Venkataramanan",
        "email": "anirudh.venkataramanan@intel.com"
    },
    "delegate": {
        "id": 68,
        "url": "http://patchwork.ozlabs.org/api/users/68/?format=api",
        "username": "jtkirshe",
        "first_name": "Jeff",
        "last_name": "Kirsher",
        "email": "jeffrey.t.kirsher@intel.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190416172439.27908-11-anirudh.venkataramanan@intel.com/mbox/",
    "series": [
        {
            "id": 103107,
            "url": "http://patchwork.ozlabs.org/api/series/103107/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=103107",
            "date": "2019-04-16T17:24:38",
            "name": "Fixes and feature updates for ice",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/103107/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1086464/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1086464/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<intel-wired-lan-bounces@osuosl.org>",
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        ],
        "Authentication-Results": [
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            "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Apr 2019 10:25:11 -0700",
            "from shasta.jf.intel.com ([10.166.244.191])\n\tby orsmga001.jf.intel.com with ESMTP; 16 Apr 2019 10:25:11 -0700"
        ],
        "X-Virus-Scanned": [
            "amavisd-new at osuosl.org",
            "amavisd-new at osuosl.org"
        ],
        "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6",
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.60,358,1549958400\"; d=\"scan'208\";a=\"224064173\"",
        "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>",
        "To": "intel-wired-lan@lists.osuosl.org",
        "Date": "Tue, 16 Apr 2019 10:24:34 -0700",
        "Message-Id": "<20190416172439.27908-11-anirudh.venkataramanan@intel.com>",
        "X-Mailer": "git-send-email 2.20.1",
        "In-Reply-To": "<20190416172439.27908-1-anirudh.venkataramanan@intel.com>",
        "References": "<20190416172439.27908-1-anirudh.venkataramanan@intel.com>",
        "MIME-Version": "1.0",
        "Subject": "[Intel-wired-lan] [PATCH S19 10/15] ice: Reorganize tx_buf and ring\n\tstructs",
        "X-BeenThere": "intel-wired-lan@osuosl.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>",
        "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>",
        "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>",
        "List-Post": "<mailto:intel-wired-lan@osuosl.org>",
        "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>",
        "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>",
        "Content-Type": "text/plain; charset=\"us-ascii\"",
        "Content-Transfer-Encoding": "7bit",
        "Errors-To": "intel-wired-lan-bounces@osuosl.org",
        "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>"
    },
    "content": "From: Jesse Brandeburg <jesse.brandeburg@intel.com>\n\nUse more efficient structure ordering by using the pahole tool\nand a lot of code inspection to get hot cache lines to have\npacked data (no holes if possible) and adjacent warm data.\n\nice_ring prior to this change:\n  /* size: 192, cachelines: 3, members: 23 */\n  /* sum members: 158, holes: 4, sum holes: 12 */\n  /* padding: 22 */\n\nice_ring after this change:\n  /* size: 192, cachelines: 3, members: 25 */\n  /* sum members: 162, holes: 1, sum holes: 1 */\n  /* padding: 29 */\n\nice_tx_buf prior to this change:\n  /* size: 48, cachelines: 1, members: 7 */\n  /* sum members: 38, holes: 2, sum holes: 6 */\n  /* padding: 4 */\n  /* last cacheline: 48 bytes */\n\nice_tx_buf after this change:\n  /* size: 40, cachelines: 1, members: 7 */\n  /* sum members: 38, holes: 1, sum holes: 2 */\n  /* last cacheline: 40 bytes */\n\nSigned-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n[Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> cleaned up commit message]\n---\n drivers/net/ethernet/intel/ice/ice_txrx.h | 35 ++++++++++++++---------\n 1 file changed, 21 insertions(+), 14 deletions(-)",
    "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_txrx.h b/drivers/net/ethernet/intel/ice/ice_txrx.h\nindex 66e05032ee56..4cff52ffefe0 100644\n--- a/drivers/net/ethernet/intel/ice/ice_txrx.h\n+++ b/drivers/net/ethernet/intel/ice/ice_txrx.h\n@@ -58,19 +58,19 @@ struct ice_tx_buf {\n \tunsigned int bytecount;\n \tunsigned short gso_segs;\n \tu32 tx_flags;\n-\tDEFINE_DMA_UNMAP_ADDR(dma);\n \tDEFINE_DMA_UNMAP_LEN(len);\n+\tDEFINE_DMA_UNMAP_ADDR(dma);\n };\n \n struct ice_tx_offload_params {\n-\tu8 header_len;\n+\tu64 cd_qw1;\n+\tstruct ice_ring *tx_ring;\n \tu32 td_cmd;\n \tu32 td_offset;\n \tu32 td_l2tag1;\n-\tu16 cd_l2tag2;\n \tu32 cd_tunnel_params;\n-\tu64 cd_qw1;\n-\tstruct ice_ring *tx_ring;\n+\tu16 cd_l2tag2;\n+\tu8 header_len;\n };\n \n struct ice_rx_buf {\n@@ -150,6 +150,7 @@ enum ice_rx_dtype {\n \n /* descriptor ring, associated with a VSI */\n struct ice_ring {\n+\t/* CL1 - 1st cacheline starts here */\n \tstruct ice_ring *next;\t\t/* pointer to next ring in q_vector */\n \tvoid *desc;\t\t\t/* Descriptor ring memory */\n \tstruct device *dev;\t\t/* Used for DMA mapping */\n@@ -161,11 +162,11 @@ struct ice_ring {\n \t\tstruct ice_tx_buf *tx_buf;\n \t\tstruct ice_rx_buf *rx_buf;\n \t};\n+\t/* CL2 - 2nd cacheline starts here */\n \tu16 q_index;\t\t\t/* Queue number of ring */\n-\tu32 txq_teid;\t\t\t/* Added Tx queue TEID */\n-#ifdef CONFIG_DCB\n-\tu8 dcb_tc;\t\t/* Traffic class of ring */\n-#endif /* CONFIG_DCB */\n+\tu16 q_handle;\t\t\t/* Queue handle per TC */\n+\n+\tu8 ring_active;\t\t\t/* is ring online or not */\n \n \tu16 count;\t\t\t/* Number of descriptors */\n \tu16 reg_idx;\t\t\t/* HW register index of the ring */\n@@ -173,8 +174,7 @@ struct ice_ring {\n \t/* used in interrupt processing */\n \tu16 next_to_use;\n \tu16 next_to_clean;\n-\n-\tu8 ring_active;\t\t\t/* is ring online or not */\n+\tu16 next_to_alloc;\n \n \t/* stats structs */\n \tstruct ice_q_stats\tstats;\n@@ -184,10 +184,17 @@ struct ice_ring {\n \t\tstruct ice_rxq_stats rx_stats;\n \t};\n \n-\tunsigned int size;\t\t/* length of descriptor ring in bytes */\n-\tdma_addr_t dma;\t\t\t/* physical address of ring */\n \tstruct rcu_head rcu;\t\t/* to avoid race on free */\n-\tu16 next_to_alloc;\n+\t/* CLX - the below items are only accessed infrequently and should be\n+\t * in their own cache line if possible\n+\t */\n+\tdma_addr_t dma;\t\t\t/* physical address of ring */\n+\tunsigned int size;\t\t/* length of descriptor ring in bytes */\n+\tu32 txq_teid;\t\t\t/* Added Tx queue TEID */\n+\tu16 rx_buf_len;\n+#ifdef CONFIG_DCB\n+\tu8 dcb_tc;\t\t\t/* Traffic class of ring */\n+#endif /* CONFIG_DCB */\n } ____cacheline_internodealigned_in_smp;\n \n struct ice_ring_container {\n",
    "prefixes": [
        "S19",
        "10/15"
    ]
}