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GET /api/patches/1084801/?format=api
{ "id": 1084801, "url": "http://patchwork.ozlabs.org/api/patches/1084801/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190412153319.5163-1-jacob.e.keller@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190412153319.5163-1-jacob.e.keller@intel.com>", "list_archive_url": null, "date": "2019-04-12T15:33:19", "name": "[v2] ixgbe: implement support for SDP/PPS output on X550 hardware", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "fa5c42815b4e2947d8f8baef9727ef8f004f59f3", "submitter": { "id": 9784, "url": "http://patchwork.ozlabs.org/api/people/9784/?format=api", "name": "Jacob Keller", "email": "jacob.e.keller@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190412153319.5163-1-jacob.e.keller@intel.com/mbox/", "series": [ { "id": 102488, "url": "http://patchwork.ozlabs.org/api/series/102488/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=102488", "date": "2019-04-12T15:33:19", "name": "[v2] ixgbe: implement support for SDP/PPS output on X550 hardware", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/102488/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1084801/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1084801/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 44ghkK1ZCfz9s00\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 13 Apr 2019 01:33:28 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 7516386DF4;\n\tFri, 12 Apr 2019 15:33:26 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id nDfYkdjIqsDQ; Fri, 12 Apr 2019 15:33:24 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id C26BB86E21;\n\tFri, 12 Apr 2019 15:33:24 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id DFE261BF408\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 12 Apr 2019 15:33:23 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id DC1E92266C\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 12 Apr 2019 15:33:23 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id K-j8t1vwdR0l for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 12 Apr 2019 15:33:23 +0000 (UTC)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby silver.osuosl.org (Postfix) with ESMTPS id ED1432206E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 12 Apr 2019 15:33:22 +0000 (UTC)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t12 Apr 2019 08:33:22 -0700", "from jekeller-desk.amr.corp.intel.com ([10.166.244.182])\n\tby orsmga001.jf.intel.com with ESMTP; 12 Apr 2019 08:33:22 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.60,341,1549958400\"; d=\"scan'208\";a=\"222985291\"", "From": "Jacob Keller <jacob.e.keller@intel.com>", "To": "Intel Wired LAN <intel-wired-lan@lists.osuosl.org>", "Date": "Fri, 12 Apr 2019 08:33:19 -0700", "Message-Id": "<20190412153319.5163-1-jacob.e.keller@intel.com>", "X-Mailer": "git-send-email 2.21.0.564.g2d7e7e4d310b", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH v2] ixgbe: implement support for SDP/PPS\n\toutput on X550 hardware", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Similar to the X540 hardware, enable support for generating a 1pps\noutput signal on SDP0.\n\nThis support is slightly different to the X540 hardware, because of the\nregister layout changes. First, the system time register is now\nrepresented in 'cycles' and 'billions of cycles'. Second, we need to\nalso program the TSSDP register, as well as the ESDP register. Third,\nthe clock output uses only FREQOUT, instead of a full 64bit value for\nthe output clock period. Finally, we have to use the ST0 bit instead of\nthe SYNCLK bit in the TSAUXC register.\n\nThis support should work even for the hardware with a higher frequency\nclock, as it carefully takes into account the multiply and shift of the\ncycle counter used.\n\nWe also set the pps configuration to 1, since we now support generating\na pulse per second output.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\n---\n drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c | 99 ++++++++++++++++++-\n drivers/net/ethernet/intel/ixgbe/ixgbe_type.h | 14 ++-\n 2 files changed, 108 insertions(+), 5 deletions(-)\n\nChanges in v2\n* use div_u64 instead of a divide instruction, to avoid issues with 64bit\n division on 32bit platforms.", "diff": "diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c\nindex 047767408df0..21b02ec55013 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c\n@@ -224,6 +224,101 @@ static void ixgbe_ptp_setup_sdp_X540(struct ixgbe_adapter *adapter)\n \tIXGBE_WRITE_FLUSH(hw);\n }\n \n+/**\n+ * ixgbe_ptp_setup_sdp_X550\n+ * @adapter: private adapter structure\n+ *\n+ * Enable or disable a clock output signal on SDP 0 for X550 hardware.\n+ *\n+ * Use the target time feature to align the output signal on the next full\n+ * second.\n+ *\n+ * This works by using the cycle counter shift and mult values in reverse, and\n+ * assumes that the values we're shifting will not overflow.\n+ */\n+static void ixgbe_ptp_setup_sdp_X550(struct ixgbe_adapter *adapter)\n+{\n+\tstruct cyclecounter *cc = &adapter->hw_cc;\n+\tstruct ixgbe_hw *hw = &adapter->hw;\n+\tu32 esdp, tsauxc, freqout, trgttiml, trgttimh, rem, tssdp;\n+\tu64 ns = 0, clock_edge = 0;\n+\tstruct timespec64 ts;\n+\tunsigned long flags;\n+\n+\t/* disable the pin first */\n+\tIXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);\n+\tIXGBE_WRITE_FLUSH(hw);\n+\n+\tif (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))\n+\t\treturn;\n+\n+\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\n+\t/* enable the SDP0 pin as output, and connected to the\n+\t * native function for Timesync (ClockOut)\n+\t */\n+\tesdp |= IXGBE_ESDP_SDP0_DIR |\n+\t\tIXGBE_ESDP_SDP0_NATIVE;\n+\n+\t/* enable the Clock Out feature on SDP0, and use Target Time 0 to\n+\t * enable generation of interrupts on the clock change.\n+\t */\n+#define IXGBE_TSAUXC_DIS_TS_CLEAR 0x40000000\n+\ttsauxc = (IXGBE_TSAUXC_EN_CLK | IXGBE_TSAUXC_ST0 |\n+\t\t IXGBE_TSAUXC_EN_TT0 | IXGBE_TSAUXC_SDP0_INT |\n+\t\t IXGBE_TSAUXC_DIS_TS_CLEAR);\n+\n+\ttssdp = (IXGBE_TSSDP_TS_SDP0_EN |\n+\t\t IXGBE_TSSDP_TS_SDP0_CLK0);\n+\n+\t/* Determine the clock time period to use. This assumes that the\n+\t * cycle counter shift is small enough to avoid overflowing a 32bit\n+\t * value.\n+\t */\n+\tfreqout = div_u64(NS_PER_HALF_SEC << cc->shift, cc->mult);\n+\n+\t/* Read the current clock time, and save the cycle counter value */\n+\tspin_lock_irqsave(&adapter->tmreg_lock, flags);\n+\tns = timecounter_read(&adapter->hw_tc);\n+\tclock_edge = adapter->hw_tc.cycle_last;\n+\tspin_unlock_irqrestore(&adapter->tmreg_lock, flags);\n+\n+\t/* Figure out how far past the next second we are */\n+\tdiv_u64_rem(ns, NS_PER_SEC, &rem);\n+\n+\t/* Figure out how many nanoseconds to add to round the clock edge up\n+\t * to the next full second\n+\t */\n+\trem = (NS_PER_SEC - rem);\n+\n+\t/* Adjust the clock edge to align with the next full second. This\n+\t * assumes that the cycle counter shift is small enough to avoid\n+\t * overflowing when shifting the remainder.\n+\t */\n+\tclock_edge += div_u64((rem << cc->shift), cc->mult);\n+\n+\t/* X550 hardware stores the time in 32bits of 'billions of cycles' and\n+\t * 32bits of 'cycles'. There's no guarantee that cycles represents\n+\t * nanoseconds. However, we can use the math from a timespec64 to\n+\t * convert into the hardware representation.\n+\t *\n+\t * See ixgbe_ptp_read_X550() for more details.\n+\t */\n+\tts = ns_to_timespec64(clock_edge);\n+\ttrgttiml = (u32)ts.tv_nsec;\n+\ttrgttimh = (u32)ts.tv_sec;\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_FREQOUT0, freqout);\n+\tIXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);\n+\tIXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n+\tIXGBE_WRITE_REG(hw, IXGBE_TSSDP, tssdp);\n+\tIXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);\n+\n+\tIXGBE_WRITE_FLUSH(hw);\n+}\n+\n /**\n * ixgbe_ptp_read_X550 - read cycle counter value\n * @hw_cc: cyclecounter structure\n@@ -1293,13 +1388,13 @@ static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)\n \t\tadapter->ptp_caps.n_alarm = 0;\n \t\tadapter->ptp_caps.n_ext_ts = 0;\n \t\tadapter->ptp_caps.n_per_out = 0;\n-\t\tadapter->ptp_caps.pps = 0;\n+\t\tadapter->ptp_caps.pps = 1;\n \t\tadapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_X550;\n \t\tadapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;\n \t\tadapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;\n \t\tadapter->ptp_caps.settime64 = ixgbe_ptp_settime;\n \t\tadapter->ptp_caps.enable = ixgbe_ptp_feature_enable;\n-\t\tadapter->ptp_setup_sdp = NULL;\n+\t\tadapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_X550;\n \t\tbreak;\n \tdefault:\n \t\tadapter->ptp_clock = NULL;\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h\nindex 84f2dba39e36..2be1c4c72435 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h\n@@ -1067,6 +1067,7 @@ struct ixgbe_nvm_version {\n #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */\n #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */\n #define IXGBE_TSIM 0x08C68 /* TimeSync Interrupt Mask Register - RW */\n+#define IXGBE_TSSDP 0x0003C /* TimeSync SDP Configuration Register - RW */\n \n /* Diagnostic Registers */\n #define IXGBE_RDSTATCTL 0x02C20\n@@ -2240,11 +2241,18 @@ enum {\n #define IXGBE_RXDCTL_RLPML_EN 0x00008000\n #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */\n \n-#define IXGBE_TSAUXC_EN_CLK 0x00000004\n-#define IXGBE_TSAUXC_SYNCLK 0x00000008\n-#define IXGBE_TSAUXC_SDP0_INT 0x00000040\n+#define IXGBE_TSAUXC_EN_CLK\t\t0x00000004\n+#define IXGBE_TSAUXC_SYNCLK\t\t0x00000008\n+#define IXGBE_TSAUXC_SDP0_INT\t\t0x00000040\n+#define IXGBE_TSAUXC_EN_TT0\t\t0x00000001\n+#define IXGBE_TSAUXC_EN_TT1\t\t0x00000002\n+#define IXGBE_TSAUXC_ST0\t\t0x00000010\n #define IXGBE_TSAUXC_DISABLE_SYSTIME\t0x80000000\n \n+#define IXGBE_TSSDP_TS_SDP0_SEL_MASK\t0x000000C0\n+#define IXGBE_TSSDP_TS_SDP0_CLK0\t0x00000080\n+#define IXGBE_TSSDP_TS_SDP0_EN\t\t0x00000100\n+\n #define IXGBE_TSYNCTXCTL_VALID\t\t0x00000001 /* Tx timestamp valid */\n #define IXGBE_TSYNCTXCTL_ENABLED\t0x00000010 /* Tx timestamping enabled */\n \n", "prefixes": [ "v2" ] }