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GET /api/patches/1083258/?format=api
{ "id": 1083258, "url": "http://patchwork.ozlabs.org/api/patches/1083258/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190410084335.16828-2-andy.tang@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190410084335.16828-2-andy.tang@nxp.com>", "list_archive_url": null, "date": "2019-04-10T08:43:34", "name": "[U-Boot,2/3,v3] armv8: ls1028ardb: Add support for LS1028ARDB platform", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "6d5608460894c341a2662957773cb0b02b8b28de", "submitter": { "id": 71141, "url": "http://patchwork.ozlabs.org/api/people/71141/?format=api", "name": "Andy Tang", "email": "andy.tang@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190410084335.16828-2-andy.tang@nxp.com/mbox/", "series": [ { "id": 101925, "url": "http://patchwork.ozlabs.org/api/series/101925/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=101925", "date": "2019-04-10T08:43:33", "name": "[U-Boot,1/3,v3] armv8: ls1028a: Add NXP LS1028A SoC support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/101925/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1083258/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1083258/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 44fHv81CVXz9s70\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 10 Apr 2019 18:51:15 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 9A54BC21E1A; Wed, 10 Apr 2019 08:51:14 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id ADBEBC21DFA;\n\tWed, 10 Apr 2019 08:50:37 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid A29C1C21DE8; Wed, 10 Apr 2019 08:50:35 +0000 (UTC)", "from inva021.nxp.com (inva021.nxp.com [92.121.34.21])\n\tby lists.denx.de (Postfix) with ESMTPS id 27F96C21C3F\n\tfor <u-boot@lists.denx.de>; Wed, 10 Apr 2019 08:50:35 +0000 (UTC)", "from inva021.nxp.com (localhost [127.0.0.1])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id DBEF220000F;\n\tWed, 10 Apr 2019 10:50:34 +0200 (CEST)", "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 572EE200220;\n\tWed, 10 Apr 2019 10:50:30 +0200 (CEST)", "from titan.ap.freescale.net (TITAN.ap.freescale.net\n\t[10.192.208.233])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id DBA45402A8;\n\tWed, 10 Apr 2019 16:50:24 +0800 (SGT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "Yuantian Tang <andy.tang@nxp.com>", "To": "prabhakar.kushwaha@nxp.com", "Date": "Wed, 10 Apr 2019 16:43:34 +0800", "Message-Id": "<20190410084335.16828-2-andy.tang@nxp.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20190410084335.16828-1-andy.tang@nxp.com>", "References": "<20190410084335.16828-1-andy.tang@nxp.com>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Cc": "sudhanshu.gupta@nxp.com, Yuantian Tang <andy.tang@nxp.com>,\n\tu-boot@lists.denx.de, ran.wang_1@nxp.com, Bhaskar.Upadhaya@nxp.com", "Subject": "[U-Boot] [PATCH 2/3 v3] armv8: ls1028ardb: Add support for\n\tLS1028ARDB platform", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluatoin\nplatform that supports the LS1028A family SoCs. This patch add basic\nsupport of the platform.\n\nSigned-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>\nSigned-off-by: Rai Harninder <harninder.rai@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\nSigned-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>\nSigned-off-by: Tang Yuantian <andy.tang@nxp.com>\n---\nv3:\n\t- remove ddr fixed initialization\n arch/arm/Kconfig | 12 +++\n arch/arm/cpu/armv8/Kconfig | 1 +\n arch/arm/dts/fsl-ls1028a-rdb.dts | 88 +++++++++++++++\n board/freescale/ls1028a/Kconfig | 26 +++++\n board/freescale/ls1028a/MAINTAINERS | 10 ++\n board/freescale/ls1028a/Makefile | 8 ++\n board/freescale/ls1028a/README | 79 ++++++++++++++\n board/freescale/ls1028a/ddr.c | 20 ++++\n board/freescale/ls1028a/ls1028a.c | 193 +++++++++++++++++++++++++++++++++\n configs/ls1028ardb_tfa_defconfig | 61 +++++++++++\n include/configs/ls1028a_common.h | 209 ++++++++++++++++++++++++++++++++++++\n include/configs/ls1028ardb.h | 77 +++++++++++++\n 12 files changed, 784 insertions(+)\n create mode 100644 arch/arm/dts/fsl-ls1028a-rdb.dts\n create mode 100644 board/freescale/ls1028a/Kconfig\n create mode 100644 board/freescale/ls1028a/MAINTAINERS\n create mode 100644 board/freescale/ls1028a/Makefile\n create mode 100644 board/freescale/ls1028a/README\n create mode 100644 board/freescale/ls1028a/ddr.c\n create mode 100644 board/freescale/ls1028a/ls1028a.c\n create mode 100644 configs/ls1028ardb_tfa_defconfig\n create mode 100644 include/configs/ls1028a_common.h\n create mode 100644 include/configs/ls1028ardb.h", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex f42ecce..aaaf36a 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -1203,6 +1203,17 @@ config TARGET_LS1012AFRDM\n \t development platform that supports the QorIQ LS1012A\n \t Layerscape Architecture processor.\n \n+config TARGET_LS1028ARDB\n+\tbool \"Support ls1028ardb\"\n+\tselect ARCH_LS1028A\n+\tselect ARM64\n+\tselect ARMV8_MULTIENTRY\n+\thelp\n+\t Support for Freescale LS1028ARDB platform\n+\t The LS1028A Development System (RDB) is a high-performance\n+\t development platform that supports the QorIQ LS1028A\n+\t Layerscape Architecture processor.\n+\n config TARGET_LS1088ARDB\n \tbool \"Support ls1088ardb\"\n \tselect ARCH_LS1088A\n@@ -1585,6 +1596,7 @@ source \"board/freescale/ls2080a/Kconfig\"\n source \"board/freescale/ls2080aqds/Kconfig\"\n source \"board/freescale/ls2080ardb/Kconfig\"\n source \"board/freescale/ls1088a/Kconfig\"\n+source \"board/freescale/ls1028a/Kconfig\"\n source \"board/freescale/ls1021aqds/Kconfig\"\n source \"board/freescale/ls1043aqds/Kconfig\"\n source \"board/freescale/ls1021atwr/Kconfig\"\ndiff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig\nindex f053603..a4fa63b 100644\n--- a/arch/arm/cpu/armv8/Kconfig\n+++ b/arch/arm/cpu/armv8/Kconfig\n@@ -104,6 +104,7 @@ config PSCI_RESET\n \t\t !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \\\n \t\t !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \\\n \t\t !TARGET_LS1012AFRWY && \\\n+\t\t !TARGET_LS1028ARDB && \\\n \t\t !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \\\n \t\t !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \\\n \t\t !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \\\ndiff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts\nnew file mode 100644\nindex 0000000..932cfa2\n--- /dev/null\n+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts\n@@ -0,0 +1,88 @@\n+// SPDX-License-Identifier: GPL-2.0+ OR X11\n+/*\n+ * NXP ls1028ARDB device tree source\n+ *\n+ * Copyright 2019 NXP\n+ *\n+ */\n+\n+/dts-v1/;\n+\n+#include \"fsl-ls1028a.dtsi\"\n+\n+/ {\n+\tmodel = \"NXP Layerscape 1028a RDB Board\";\n+\tcompatible = \"fsl,ls1028a-rdb\", \"fsl,ls1028a\";\n+};\n+\n+&dspi0 {\n+\tstatus = \"okay\";\n+};\n+\n+&dspi1 {\n+\tstatus = \"okay\";\n+};\n+\n+&dspi2 {\n+\tstatus = \"okay\";\n+};\n+\n+&esdhc0 {\n+\tstatus = \"okay\";\n+};\n+\n+&esdhc1 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c0 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c1 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c2 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c3 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c4 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c5 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c6 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c7 {\n+\tstatus = \"okay\";\n+};\n+\n+&sata {\n+\tstatus = \"okay\";\n+};\n+\n+&serial0 {\n+\tstatus = \"okay\";\n+};\n+\n+&serial1 {\n+\tstatus = \"okay\";\n+};\n+\n+&usb1 {\n+\tstatus = \"okay\";\n+};\n+\n+&usb2 {\n+\tstatus = \"okay\";\n+};\ndiff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig\nnew file mode 100644\nindex 0000000..bbfd4dd\n--- /dev/null\n+++ b/board/freescale/ls1028a/Kconfig\n@@ -0,0 +1,26 @@\n+if TARGET_LS1028ARDB\n+\n+config SYS_BOARD\n+\tdefault \"ls1028a\"\n+\n+config SYS_VENDOR\n+\tdefault \"freescale\"\n+\n+config SYS_SOC\n+\tdefault \"fsl-layerscape\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"ls1028ardb\"\n+\n+config EMMC_BOOT\n+\tbool \"Support for booting from EMMC\"\n+\tdefault n\n+\n+config SYS_TEXT_BASE\n+\tdefault 0x96000000 if SD_BOOT || EMMC_BOOT\n+\tdefault 0x82000000 if TFABOOT\n+\tdefault 0x20100000\n+\n+source \"board/freescale/common/Kconfig\"\n+\n+endif\ndiff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS\nnew file mode 100644\nindex 0000000..135454c\n--- /dev/null\n+++ b/board/freescale/ls1028a/MAINTAINERS\n@@ -0,0 +1,10 @@\n+LS1028ARDB BOARD\n+M:\tSudhanshu Gupta <sudhanshu.gupta@nxp.com>\n+M:\tRai Harninder <harninder.rai@nxp.com>\n+M:\tRajesh Bhagat <rajesh.bhagat@nxp.com>\n+M:\tTang Yuantian <andy.tang@nxp.com>\n+S:\tMaintained\n+F:\tboard/freescale/ls1028a/\n+F:\tinclude/configs/ls1028a_common.h\n+F:\tinclude/configs/ls1028ardb.h\n+F:\tconfigs/ls1028ardb_tfa_defconfig\ndiff --git a/board/freescale/ls1028a/Makefile b/board/freescale/ls1028a/Makefile\nnew file mode 100644\nindex 0000000..9bc144c\n--- /dev/null\n+++ b/board/freescale/ls1028a/Makefile\n@@ -0,0 +1,8 @@\n+#\n+# Copyright 2019 NXP\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+obj-y += ls1028a.o\n+obj-y += ddr.o\ndiff --git a/board/freescale/ls1028a/README b/board/freescale/ls1028a/README\nnew file mode 100644\nindex 0000000..94a390c\n--- /dev/null\n+++ b/board/freescale/ls1028a/README\n@@ -0,0 +1,79 @@\n+Overview\n+--------\n+The LS1028A Reference Design (RDB) is a high-performance computing,\n+evaluation, and development platform that supports ARM SoC LS1028A and its\n+derivatives.\n+\n+LS1028A SoC Overview\n+--------------------------------------\n+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc\n+\n+RDB Default Switch Settings (1: ON; 0: OFF)\n+-------------------------------------------\n+For XSPI NOR boot (default)\n+SW2: 1111_1000\n+SW3: 1111_0000\n+SW5: 0011_1001\n+\n+For SD Boot\n+SW2: 1000_1000\n+SW3: 1111_0000\n+SW5: 0011_1001\n+\n+For eMMC Boot\n+SW2: 1001_1000\n+SW3: 1111_0000\n+SW5: 0011_1001\n+\n+LS1028ARDB board Overview\n+-------------------------\n+Processor\n+ Two Arm Cortex- A72 processor cores:\n+ - Based on 64-bit ARMv8 architecture\n+ - Up to 1.3 GHz operation\n+ - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1\n+ data cache\n+ - Arranged as a single cluster of two cores sharing a single 1 MB L2\n+ cache\n+DDR memory\n+ - Five onboard 1G x8 discrete memory modules (Four data byte lanes\n+ ECC)\n+ - 32-bit data and 4-bit ECC\n+ - One chip select\n+ - Data transfer rates of up to 1.6 GT/s\n+ - Single-bit error correction and double-bit error detection ECC (4-bit\n+ check word across 32-bit data)\n+High-speed serial ports(SerDes)\n+ - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the\n+ Qualcomm AR8033 PHY\n+ - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected\n+ through the NXP F104S8A PHY\n+ - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3\n+ (8 Gbit/s) cards\n+ - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B\n+ slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or\n+ SATA Gen 3 cards (6 Gbit/s) at a time\n+eSDHC\n+ - eSDHC1, eSDHC2\n+SPI\n+ - Connects to two mikroBUS sockets to support mikro-click modules,\n+ such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near\n+ field communications (NFC) controller\n+Octal SPI (XSPI)\n+ - One 256 MB onboard XSPI serial NOR flash memory\n+ - One 512 MB onboard XSPI serial NAND flash memory\n+ - Supports a QSPI emulator for offboard QSPI emulation\n+I2C\n+ - All system devices are accessed via I2C1, which is multiplexed on\n+ I2C multiplexer PCA9848 to isolate address conflicts and reduce\n+ capacitive load\n+ - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,\n+ thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules\n+ 1 and 2\n+CAN\n+ - The two CAN DB9 ports can support CAN FD fast phase at data rates of\n+ up to 5 Mbit/s\n+Serial audio interface(SAI)\n+ - Audio codec SGTL5000 provides headphone and audio LINEOUT for\n+ stereo speakers\n+ - IEEE1588 interface to support audio on SAI4\ndiff --git a/board/freescale/ls1028a/ddr.c b/board/freescale/ls1028a/ddr.c\nnew file mode 100644\nindex 0000000..74d3af5\n--- /dev/null\n+++ b/board/freescale/ls1028a/ddr.c\n@@ -0,0 +1,20 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2019 NXP\n+ */\n+\n+#include <common.h>\n+#include <fsl_ddr_sdram.h>\n+#include <fsl_ddr_dimm_params.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int fsl_initdram(void)\n+{\n+\tgd->ram_size = tfa_get_dram_size();\n+\n+\tif (!gd->ram_size)\n+\t\tgd->ram_size = fsl_ddr_sdram_size();\n+\n+\treturn 0;\n+}\ndiff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c\nnew file mode 100644\nindex 0000000..e3666c3\n--- /dev/null\n+++ b/board/freescale/ls1028a/ls1028a.c\n@@ -0,0 +1,193 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2019 NXP\n+ */\n+\n+#include <common.h>\n+#include <malloc.h>\n+#include <errno.h>\n+#include <fsl_ddr.h>\n+#include <asm/io.h>\n+#include <hwconfig.h>\n+#include <fdt_support.h>\n+#include <linux/libfdt.h>\n+#include <environment.h>\n+#include <asm/arch-fsl-layerscape/soc.h>\n+#include <i2c.h>\n+#include <asm/arch/soc.h>\n+#ifdef CONFIG_FSL_LS_PPA\n+#include <asm/arch/ppa.h>\n+#endif\n+#include <fsl_immap.h>\n+#include <netdev.h>\n+\n+#include <fdtdec.h>\n+#include <miiphy.h>\n+#include \"../common/qixis.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int board_init(void)\n+{\n+#ifdef CONFIG_ENV_IS_NOWHERE\n+\tgd->env_addr = (ulong)&default_environment[0];\n+#endif\n+\n+#ifdef CONFIG_FSL_LS_PPA\n+\tppa_init();\n+#endif\n+\n+#ifndef CONFIG_SYS_EARLY_PCI_INIT\n+\tpci_init();\n+#endif\n+\n+#if defined(CONFIG_TARGET_LS1028ARDB)\n+\tu8 val = I2C_MUX_CH_DEFAULT;\n+\n+\ti2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);\n+#endif\n+\treturn 0;\n+}\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn pci_eth_init(bis);\n+}\n+\n+int board_early_init_f(void)\n+{\n+#ifdef CONFIG_SYS_I2C_EARLY_INIT\n+\ti2c_early_init_f();\n+#endif\n+\n+\tfsl_lsch3_early_init_f();\n+\treturn 0;\n+}\n+\n+void detail_board_ddr_info(void)\n+{\n+\tputs(\"\\nDDR \");\n+\tprint_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, \"\");\n+\tprint_ddr_info(0);\n+}\n+\n+#ifdef CONFIG_OF_BOARD_SETUP\n+int ft_board_setup(void *blob, bd_t *bd)\n+{\n+\tu64 base[CONFIG_NR_DRAM_BANKS];\n+\tu64 size[CONFIG_NR_DRAM_BANKS];\n+\n+\tft_cpu_setup(blob, bd);\n+\n+\t/* fixup DT for the two GPP DDR banks */\n+\tbase[0] = gd->bd->bi_dram[0].start;\n+\tsize[0] = gd->bd->bi_dram[0].size;\n+\tbase[1] = gd->bd->bi_dram[1].start;\n+\tsize[1] = gd->bd->bi_dram[1].size;\n+\n+#ifdef CONFIG_RESV_RAM\n+\t/* reduce size if reserved memory is within this bank */\n+\tif (gd->arch.resv_ram >= base[0] &&\n+\t gd->arch.resv_ram < base[0] + size[0])\n+\t\tsize[0] = gd->arch.resv_ram - base[0];\n+\telse if (gd->arch.resv_ram >= base[1] &&\n+\t\t gd->arch.resv_ram < base[1] + size[1])\n+\t\tsize[1] = gd->arch.resv_ram - base[1];\n+#endif\n+\n+\tfdt_fixup_memory_banks(blob, base, size, 2);\n+\n+\treturn 0;\n+}\n+#endif\n+\n+#ifdef CONFIG_FSL_QIXIS\n+int checkboard(void)\n+{\n+#ifdef CONFIG_TFABOOT\n+\tenum boot_src src = get_boot_src();\n+#endif\n+\tu8 sw;\n+\n+\tint clock;\n+\tchar *board;\n+\tchar buf[64] = {0};\n+\tstatic const char *freq[6] = {\"100.00\", \"125.00\", \"156.25\",\n+\t\t\t\t\t\"161.13\", \"322.26\", \"100.00 SS\"};\n+\n+\tcpu_name(buf);\n+\t/* find the board details */\n+\tsw = QIXIS_READ(id);\n+\n+\tswitch (sw) {\n+\tcase 0x46:\n+\t\tboard = \"QDS\";\n+\t\tbreak;\n+\tcase 0x47:\n+\t\tboard = \"RDB\";\n+\t\tbreak;\n+\tcase 0x49:\n+\t\tboard = \"HSSI\";\n+\t\tbreak;\n+\tdefault:\n+\t\tboard = \"unknown\";\n+\t\tbreak;\n+\t}\n+\n+\tsw = QIXIS_READ(arch);\n+\tprintf(\"Board: %s-%s, Version: %c, boot from \",\n+\t buf, board, (sw & 0xf) + 'A' - 1);\n+\n+\tsw = QIXIS_READ(brdcfg[0]);\n+\tsw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;\n+\n+#ifdef CONFIG_TFABOOT\n+\tif (src == BOOT_SOURCE_SD_MMC) {\n+\t\tputs(\"SD\\n\");\n+\t} else if (src == BOOT_SOURCE_SD_MMC2) {\n+\t\tputs(\"eMMC\\n\");\n+\t} else {\n+#endif\n+#ifdef CONFIG_SD_BOOT\n+\t\tputs(\"SD\\n\");\n+#elif defined(CONFIG_EMMC_BOOT)\n+\t\tputs(\"eMMC\\n\");\n+#else\n+\t\tswitch (sw) {\n+\t\tcase 0:\n+\t\tcase 4:\n+\t\t\tprintf(\"NOR\\n\");\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\tprintf(\"NAND\\n\");\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tprintf(\"invalid setting of SW%u\\n\", QIXIS_LBMAP_SWITCH);\n+\t\t\tbreak;\n+\t\t}\n+#endif\n+#ifdef CONFIG_TFABOOT\n+\t}\n+#endif\n+\n+\tprintf(\"FPGA: v%d (%s)\\n\", QIXIS_READ(scver), board);\n+\tputs(\"SERDES1 Reference : \");\n+\n+\tsw = QIXIS_READ(brdcfg[2]);\n+#ifdef CONFIG_TARGET_LS1028ARDB\n+\tclock = (sw >> 6) & 3;\n+#else\n+\tclock = (sw >> 4) & 0xf;\n+#endif\n+\n+\tprintf(\"Clock1 = %sMHz \", freq[clock]);\n+#ifdef CONFIG_TARGET_LS1028ARDB\n+\tclock = (sw >> 4) & 3;\n+#else\n+\tclock = sw & 0xf;\n+#endif\n+\tprintf(\"Clock2 = %sMHz\\n\", freq[clock]);\n+\n+\treturn 0;\n+}\n+#endif\ndiff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig\nnew file mode 100644\nindex 0000000..7a6068d\n--- /dev/null\n+++ b/configs/ls1028ardb_tfa_defconfig\n@@ -0,0 +1,61 @@\n+CONFIG_ARM=y\n+CONFIG_TARGET_LS1028ARDB=y\n+CONFIG_SYS_FSL_SDHC_CLK_DIV=1\n+CONFIG_TFABOOT=y\n+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y\n+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y\n+CONFIG_AHCI=y\n+CONFIG_DISTRO_DEFAULTS=y\n+CONFIG_NR_DRAM_BANKS=2\n+# CONFIG_SYS_MALLOC_F is not set\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_OF_BOARD_SETUP=y\n+CONFIG_OF_STDOUT_VIA_ALIAS=y\n+CONFIG_BOOTDELAY=10\n+CONFIG_USE_BOOTARGS=y\n+CONFIG_BOOTARGS=\"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M\"\n+CONFIG_CMD_GREPENV=y\n+CONFIG_CMD_GPT=y\n+CONFIG_CMD_I2C=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_PCI=y\n+CONFIG_CMD_SF=y\n+CONFIG_CMD_USB=y\n+# CONFIG_CMD_SETEXPR is not set\n+CONFIG_CMD_CACHE=y\n+CONFIG_OF_CONTROL=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"fsl-ls1028a-rdb\"\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_ENV_IS_IN_SPI_FLASH=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_NETCONSOLE=y\n+CONFIG_DM=y\n+CONFIG_SCSI_AHCI=y\n+CONFIG_SATA_CEVA=y\n+CONFIG_FSL_CAAM=y\n+CONFIG_DM_MMC=y\n+CONFIG_DM_SPI_FLASH=y\n+CONFIG_SPI_FLASH=y\n+CONFIG_SPI_FLASH_SPANSION=y\n+CONFIG_SPI_FLASH_STMICRO=y\n+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set\n+CONFIG_PHYLIB=y\n+CONFIG_PHY_ATHEROS=y\n+CONFIG_DM_ETH=y\n+CONFIG_PHY_GIGE=y\n+CONFIG_E1000=y\n+CONFIG_PCI=y\n+CONFIG_DM_PCI=y\n+CONFIG_DM_PCI_COMPAT=y\n+CONFIG_PCIE_LAYERSCAPE=y\n+CONFIG_SCSI=y\n+CONFIG_DM_SCSI=y\n+CONFIG_SYS_NS16550=y\n+CONFIG_SPI=y\n+CONFIG_DM_SPI=y\n+CONFIG_FSL_DSPI=y\n+CONFIG_USB=y\n+CONFIG_DM_USB=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_DWC3=y\n+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y\ndiff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h\nnew file mode 100644\nindex 0000000..10f2e88\n--- /dev/null\n+++ b/include/configs/ls1028a_common.h\n@@ -0,0 +1,209 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef __L1028A_COMMON_H\n+#define __L1028A_COMMON_H\n+\n+#define CONFIG_REMAKE_ELF\n+#define CONFIG_FSL_LAYERSCAPE\n+#define CONFIG_MP\n+\n+#include <asm/arch/stream_id_lsch3.h>\n+#include <asm/arch/config.h>\n+#include <asm/arch/soc.h>\n+\n+/* Link Definitions */\n+#define CONFIG_SYS_INIT_SP_ADDR\t\tCONFIG_SYS_TEXT_BASE\n+\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+\n+#define CONFIG_VERY_BIG_RAM\n+#define CONFIG_SYS_DDR_SDRAM_BASE\t0x80000000UL\n+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY\t0\n+#define CONFIG_SYS_SDRAM_BASE\t\tCONFIG_SYS_DDR_SDRAM_BASE\n+#define CONFIG_SYS_DDR_BLOCK2_BASE\t0x2080000000ULL\n+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS\t1\n+\n+#define CONFIG_CMD_MEMTEST\n+#define CONFIG_SYS_MEMTEST_START 0x80000000\n+#define CONFIG_SYS_MEMTEST_END 0x9fffffff\n+\n+/*\n+ * SMP Definitinos\n+ */\n+#define CPU_RELEASE_ADDR\t\tsecondary_boot_func\n+\n+/* Generic Timer Definitions */\n+#define COUNTER_FREQUENCY\t\t25000000\t/* 25MHz */\n+\n+/* Size of malloc() pool */\n+#define CONFIG_SYS_MALLOC_LEN\t\t(CONFIG_ENV_SIZE + 2048 * 1024)\n+\n+/* I2C */\n+#define CONFIG_SYS_I2C\n+\n+/* Serial Port */\n+#define CONFIG_CONS_INDEX 1\n+#define CONFIG_SYS_NS16550_SERIAL\n+#define CONFIG_SYS_NS16550_REG_SIZE 1\n+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)\n+\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_SYS_BAUDRATE_TABLE\t{ 9600, 19200, 38400, 57600, 115200 }\n+\n+/* Miscellaneous configurable options */\n+#define CONFIG_SYS_LOAD_ADDR\t(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)\n+\n+/* Physical Memory Map */\n+#define CONFIG_CHIP_SELECTS_PER_CTRL\t4\n+\n+#define CONFIG_HWCONFIG\n+#define HWCONFIG_BUFFER_SIZE\t\t128\n+\n+/* Allow to overwrite serial and ethaddr */\n+#define CONFIG_ENV_OVERWRITE\n+\n+#define BOOT_TARGET_DEVICES(func) \\\n+\tfunc(MMC, mmc, 0) \\\n+\tfunc(USB, usb, 0)\n+#include <config_distro_bootcmd.h>\n+\n+/* Initial environment variables */\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\t\\\n+\t\"board=ls1028ardb\\0\"\t\t\t\\\n+\t\"hwconfig=fsl_ddr:bank_intlv=auto\\0\"\t\\\n+\t\"ramdisk_addr=0x800000\\0\"\t\t\\\n+\t\"ramdisk_size=0x2000000\\0\"\t\t\\\n+\t\"fdt_high=0xffffffffffffffff\\0\"\t\t\\\n+\t\"initrd_high=0xffffffffffffffff\\0\"\t\\\n+\t\"fdt_addr=0x00f00000\\0\" \\\n+\t\"kernel_addr=0x01000000\\0\" \\\n+\t\"scriptaddr=0x80000000\\0\" \\\n+\t\"scripthdraddr=0x80080000\\0\"\t\t\\\n+\t\"fdtheader_addr_r=0x80100000\\0\" \\\n+\t\"kernelheader_addr_r=0x80200000\\0\" \\\n+\t\"load_addr=0xa0000000\\0\" \\\n+\t\"kernel_addr_r=0x81000000\\0\" \\\n+\t\"fdt_addr_r=0x90000000\\0\" \\\n+\t\"ramdisk_addr_r=0xa0000000\\0\" \\\n+\t\"kernel_start=0x1000000\\0\"\t\t\\\n+\t\"kernelheader_start=0x800000\\0\"\t\t\\\n+\t\"kernel_load=0xa0000000\\0\"\t\t\\\n+\t\"kernel_size=0x2800000\\0\"\t\t\\\n+\t\"kernelheader_size=0x40000\\0\"\t\t\\\n+\t\"kernel_addr_sd=0x8000\\0\"\t\t\\\n+\t\"kernel_size_sd=0x14000\\0\"\t\t\\\n+\t\"kernelhdr_addr_sd=0x4000\\0\"\t\t\\\n+\t\"kernelhdr_size_sd=0x10\\0\"\t\t\\\n+\t\"console=ttyS0,115200\\0\" \\\n+\t\"mtdparts=\" CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\\\n+\tBOOTENV\t\t\t\t\t\\\n+\t\"boot_scripts=ls1028ardb_boot.scr\\0\" \\\n+\t\"boot_script_hdr=hdr_ls1028ardb_bs.out\\0\"\t\\\n+\t\"scan_dev_for_boot_part=\" \\\n+\t\t\"part list ${devtype} ${devnum} devplist; \" \\\n+\t\t\"env exists devplist || setenv devplist 1; \" \\\n+\t\t\"for distro_bootpart in ${devplist}; do \" \\\n+\t\t \"if fstype ${devtype} \" \\\n+\t\t\t\"${devnum}:${distro_bootpart} \" \\\n+\t\t\t\"bootfstype; then \" \\\n+\t\t\t\"run scan_dev_for_boot; \" \\\n+\t\t \"fi; \" \\\n+\t\t\"done\\0\" \\\n+\t\"scan_dev_for_boot=\"\t\t\t\t \\\n+\t\t\"echo Scanning ${devtype} \"\t\t \\\n+\t\t\t\t\"${devnum}:${distro_bootpart}...; \" \\\n+\t\t\"for prefix in ${boot_prefixes}; do \"\t \\\n+\t\t\t\"run scan_dev_for_scripts; \"\t \\\n+\t\t\"done;\"\t\t\t\t\t \\\n+\t\t\"\\0\"\t\t\t\t\t \\\n+\t\"boot_a_script=\"\t\t\t\t \\\n+\t\t\"load ${devtype} ${devnum}:${distro_bootpart} \" \\\n+\t\t\t\"${scriptaddr} ${prefix}${script}; \" \\\n+\t\t\"env exists secureboot && load ${devtype} \" \\\n+\t\t\t\"${devnum}:${distro_bootpart} \"\t\t\\\n+\t\t\t\"${scripthdraddr} ${prefix}${boot_script_hdr} \" \\\n+\t\t\t\"&& esbc_validate ${scripthdraddr};\" \\\n+\t\t\"source ${scriptaddr}\\0\"\t \\\n+\t\"sd_bootcmd=echo Trying load from SD ..;\"\t\\\n+\t\t\"mmcinfo; mmc read $load_addr \"\t\t\\\n+\t\t\"$kernel_addr_sd $kernel_size_sd && \"\t\\\n+\t\t\"env exists secureboot && mmc read $kernelheader_addr_r \" \\\n+\t\t\"$kernelhdr_addr_sd $kernelhdr_size_sd \"\t\t\\\n+\t\t\" && esbc_validate ${kernelheader_addr_r};\"\t\\\n+\t\t\"bootm $load_addr#$board\\0\"\t\t\\\n+\t\"sd_hdploadcmd=echo Trying load HDP firmware from SD..;\" \\\n+\t\t\"mmcinfo;mmc read $load_addr 0x4800 0x200 \"\t\t\\\n+\t\t\"&& hdp load $load_addr 0x2000\\0\"\t\\\n+\t\"emmc_bootcmd=echo Trying load from EMMC ..;\"\t\\\n+\t\t\"mmcinfo; mmc dev 1; mmc read $load_addr \"\t\t\\\n+\t\t\"$kernel_addr_sd $kernel_size_sd && \"\t\\\n+\t\t\"env exists secureboot && mmc read $kernelheader_addr_r \" \\\n+\t\t\"$kernelhdr_addr_sd $kernelhdr_size_sd \"\t\t\\\n+\t\t\" && esbc_validate ${kernelheader_addr_r};\"\t\\\n+\t\t\"bootm $load_addr#$board\\0\"\t\t\t\\\n+\t\"emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;\" \\\n+\t\t\"mmc dev 1;mmcinfo;mmc read $load_addr 0x4800 0x200 \"\t\\\n+\t\t\"&& hdp load $load_addr 0x2000\\0\"\n+\n+#undef CONFIG_BOOTCOMMAND\n+\n+#define XSPI_NOR_BOOTCOMMAND\t\\\n+\t\"run qspi_hdploadcmd; run distro_bootcmd; run qspi_bootcmd; \" \\\n+\t\"env exists secureboot && esbc_halt;;\"\n+#define SD_BOOTCOMMAND\t\\\n+\t\"run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; \" \\\n+\t\"env exists secureboot && esbc_halt;\"\n+\n+/* Monitor Command Prompt */\n+#define CONFIG_SYS_CBSIZE\t\t512\t/* Console I/O Buffer Size */\n+#define CONFIG_SYS_PBSIZE\t\t(CONFIG_SYS_CBSIZE + \\\n+\t\t\t\t\tsizeof(CONFIG_SYS_PROMPT) + 16)\n+#define CONFIG_SYS_BARGSIZE\t\tCONFIG_SYS_CBSIZE /* Boot args buffer */\n+\n+#ifndef CONFIG_CMDLINE_EDITING\n+#define CONFIG_CMDLINE_EDITING\t\t1\n+#endif\n+\n+#define CONFIG_SYS_MAXARGS\t\t64\t/* max command args */\n+\n+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */\n+\n+/* MMC */\n+#ifdef CONFIG_MMC\n+#define CONFIG_FSL_ESDHC\n+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33\n+#endif\n+\n+#define CONFIG_SYS_MMC_ENV_DEV 0\n+#define OCRAM_NONSECURE_SIZE\t\t0x00010000\n+#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */\n+#define CONFIG_SYS_FSL_QSPI_BASE\t0x20000000\n+#define CONFIG_ENV_ADDR\tCONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET\n+#define CONFIG_ENV_SIZE\t\t\t0x2000 /* 8KB */\n+#define CONFIG_ENV_SECT_SIZE 0x40000\n+\n+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE\n+\n+/* MMC */\n+#ifdef CONFIG_MMC\n+#define CONFIG_FSL_ESDHC\n+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33\n+#endif\n+\n+/* I2C bus multiplexer */\n+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/\n+#define I2C_MUX_CH_DEFAULT 0x8\n+\n+/* EEPROM */\n+#define CONFIG_ID_EEPROM\n+#define CONFIG_SYS_I2C_EEPROM_NXID\n+#define CONFIG_SYS_EEPROM_BUS_NUM\t\t0\n+#define CONFIG_SYS_I2C_EEPROM_ADDR\t\t0x57\n+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN\t\t1\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS\t3\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS\t5\n+\n+#endif /* __L1028A_COMMON_H */\ndiff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h\nnew file mode 100644\nindex 0000000..10791be\n--- /dev/null\n+++ b/include/configs/ls1028ardb.h\n@@ -0,0 +1,77 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef __LS1028A_RDB_H\n+#define __LS1028A_RDB_H\n+\n+#include \"ls1028a_common.h\"\n+\n+#define CONFIG_SYS_CLK_FREQ\t\t100000000\n+#define CONFIG_DDR_CLK_FREQ\t\t100000000\n+#define COUNTER_FREQUENCY_REAL\t\t(CONFIG_SYS_CLK_FREQ / 4)\n+\n+#define CONFIG_SYS_RTC_BUS_NUM 0\n+\n+/* Store environment at top of flash */\n+#define CONFIG_ENV_SIZE\t\t\t0x2000\n+\n+#define CONFIG_DIMM_SLOTS_PER_CTLR 1\n+\n+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE\n+\n+#define CONFIG_QIXIS_I2C_ACCESS\n+#define CONFIG_SYS_I2C_EARLY_INIT\n+\n+/*\n+ * QIXIS Definitions\n+ */\n+#define CONFIG_FSL_QIXIS\n+\n+#ifdef CONFIG_FSL_QIXIS\n+#define QIXIS_BASE\t\t\t0x7fb00000\n+#define QIXIS_BASE_PHYS\t\t\tQIXIS_BASE\n+#define CONFIG_SYS_I2C_FPGA_ADDR\t0x66\n+#define QIXIS_LBMAP_SWITCH\t\t2\n+#define QIXIS_LBMAP_MASK\t\t0xe0\n+#define QIXIS_LBMAP_SHIFT\t\t0x5\n+#define QIXIS_LBMAP_DFLTBANK\t\t0x00\n+#define QIXIS_LBMAP_ALTBANK\t\t0x00\n+#define QIXIS_LBMAP_SD\t\t\t0x00\n+#define QIXIS_LBMAP_EMMC\t\t0x00\n+#define QIXIS_LBMAP_QSPI\t\t0x00\n+#define QIXIS_RCW_SRC_SD\t\t0xf8\n+#define QIXIS_RCW_SRC_EMMC\t\t0xf9\n+#define QIXIS_RCW_SRC_QSPI\t\t0xff\n+#define QIXIS_RST_CTL_RESET\t\t0x31\n+#define QIXIS_RCFG_CTL_RECONFIG_IDLE\t0x10\n+#define QIXIS_RCFG_CTL_RECONFIG_START\t0x11\n+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE\t0x08\n+#define QIXIS_RST_FORCE_MEM\t\t0x01\n+\n+#define CONFIG_SYS_FPGA_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_FPGA_CSPR\t\t(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \\\n+\t\t\t\t\tCSPR_PORT_SIZE_8 | \\\n+\t\t\t\t\tCSPR_MSEL_GPCM | \\\n+\t\t\t\t\tCSPR_V)\n+#define CONFIG_SYS_FPGA_CSOR\t\t(CSOR_NOR_ADM_SHIFT(4) | \\\n+\t\t\t\t\tCSOR_NOR_NOR_MODE_AVD_NOR | \\\n+\t\t\t\t\tCSOR_NOR_TRHZ_80)\n+#endif\n+\n+/* SATA */\n+#ifndef CONFIG_CMD_EXT2\n+#define CONFIG_CMD_EXT2\n+#endif\n+#define CONFIG_SYS_SCSI_MAX_SCSI_ID\t\t1\n+#define CONFIG_SYS_SCSI_MAX_LUN\t\t\t1\n+#define CONFIG_SYS_SCSI_MAX_DEVICE\t\t(CONFIG_SYS_SCSI_MAX_SCSI_ID * \\\n+\t\t\t\t\t\tCONFIG_SYS_SCSI_MAX_LUN)\n+#define SCSI_VEND_ID 0x1b4b\n+#define SCSI_DEV_ID 0x9170\n+#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}\n+#define CONFIG_SCSI_AHCI_PLAT\n+#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1\n+\n+#endif /* __LS1028A_RDB_H */\n", "prefixes": [ "U-Boot", "2/3", "v3" ] }