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{ "id": 1083257, "url": "http://patchwork.ozlabs.org/api/patches/1083257/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190410084335.16828-1-andy.tang@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190410084335.16828-1-andy.tang@nxp.com>", "list_archive_url": null, "date": "2019-04-10T08:43:33", "name": "[U-Boot,1/3,v3] armv8: ls1028a: Add NXP LS1028A SoC support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "d8b3ddc317027fc1a8153850b65116ea1823fd8c", "submitter": { "id": 71141, "url": "http://patchwork.ozlabs.org/api/people/71141/?format=api", "name": "Andy Tang", "email": "andy.tang@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190410084335.16828-1-andy.tang@nxp.com/mbox/", "series": [ { "id": 101925, "url": "http://patchwork.ozlabs.org/api/series/101925/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=101925", "date": "2019-04-10T08:43:33", "name": "[U-Boot,1/3,v3] armv8: ls1028a: Add NXP LS1028A SoC support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/101925/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1083257/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1083257/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 44fHtT64fPz9s0W\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 10 Apr 2019 18:50:41 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 8A769C21E15; Wed, 10 Apr 2019 08:50:40 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 50F7EC21DAF;\n\tWed, 10 Apr 2019 08:50:35 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid C82BFC21CB1; Wed, 10 Apr 2019 08:50:33 +0000 (UTC)", "from inva021.nxp.com (inva021.nxp.com [92.121.34.21])\n\tby lists.denx.de (Postfix) with ESMTPS id 39B75C21C3F\n\tfor <u-boot@lists.denx.de>; Wed, 10 Apr 2019 08:50:33 +0000 (UTC)", "from inva021.nxp.com (localhost [127.0.0.1])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id AEB9C200394;\n\tWed, 10 Apr 2019 10:50:32 +0200 (CEST)", "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 5BF5020000F;\n\tWed, 10 Apr 2019 10:50:28 +0200 (CEST)", "from titan.ap.freescale.net (TITAN.ap.freescale.net\n\t[10.192.208.233])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id D233140249;\n\tWed, 10 Apr 2019 16:50:22 +0800 (SGT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "Yuantian Tang <andy.tang@nxp.com>", "To": "prabhakar.kushwaha@nxp.com", "Date": "Wed, 10 Apr 2019 16:43:33 +0800", "Message-Id": "<20190410084335.16828-1-andy.tang@nxp.com>", "X-Mailer": "git-send-email 2.14.1", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Cc": "sudhanshu.gupta@nxp.com, Yuantian Tang <andy.tang@nxp.com>,\n\tu-boot@lists.denx.de, ran.wang_1@nxp.com, Bhaskar.Upadhaya@nxp.com", "Subject": "[U-Boot] [PATCH 1/3 v3] armv8: ls1028a: Add NXP LS1028A SoC support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Ls1028a Soc is based on Layerscape Chassis Generation 3.2\narchitecture with features:\n 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN\n ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,\n 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.\n\nSigned-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>\nSigned-off-by: Rai Harninder <harninder.rai@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\nSigned-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>\nSigned-off-by: Tang Yuantian <andy.tang@nxp.com>\n---\nv3:\n\t-- fix some issues\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++-\n arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 +\n arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +\n arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 51 ++++\n arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 73 ++++++\n arch/arm/dts/fsl-ls1028a.dtsi | 280 +++++++++++++++++++++\n arch/arm/include/asm/arch-fsl-layerscape/config.h | 61 +++++\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 +\n arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +\n .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +-\n 10 files changed, 521 insertions(+), 2 deletions(-)\n create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c\n create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex f48481f..8ecd095 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -20,6 +20,40 @@ config ARCH_LS1012A\n \tselect SYS_I2C_MXC_I2C2\n \timply PANIC_HANG\n \n+config ARCH_LS1028A\n+\tbool\n+\tselect ARMV8_SET_SMPEN\n+\tselect FSL_LSCH3\n+\tselect NXP_LSCH3_2\n+\tselect SYS_FSL_HAS_CCI400\n+\tselect SYS_FSL_SRDS_1\n+\tselect SYS_HAS_SERDES\n+\tselect SYS_FSL_DDR\n+\tselect SYS_FSL_DDR_LE\n+\tselect SYS_FSL_DDR_VER_50\n+\tselect SYS_FSL_HAS_DDR3\n+\tselect SYS_FSL_HAS_DDR4\n+\tselect SYS_FSL_HAS_SEC\n+\tselect SYS_FSL_SEC_COMPAT_5\n+\tselect SYS_FSL_SEC_LE\n+\tselect FSL_TZASC_1\n+\tselect ARCH_EARLY_INIT_R\n+\tselect BOARD_EARLY_INIT_F\n+\tselect SYS_I2C_MXC\n+\tselect SYS_I2C_MXC_I2C1\n+\tselect SYS_I2C_MXC_I2C2\n+\tselect SYS_I2C_MXC_I2C3\n+\tselect SYS_I2C_MXC_I2C4\n+\tselect SYS_I2C_MXC_I2C5\n+\tselect SYS_I2C_MXC_I2C6\n+\tselect SYS_I2C_MXC_I2C7\n+\tselect SYS_I2C_MXC_I2C8\n+\tselect SYS_FSL_ERRATUM_A009007\n+\tselect SYS_FSL_ERRATUM_A008514 if !TFABOOT\n+\tselect SYS_FSL_ERRATUM_A009663 if !TFABOOT\n+\tselect SYS_FSL_ERRATUM_A009942 if !TFABOOT\n+\timply PANIC_HANG\n+\n config ARCH_LS1043A\n \tbool\n \tselect ARMV8_SET_SMPEN\n@@ -244,6 +278,7 @@ config FSL_PCIE_COMPAT\n \tstring \"PCIe compatible of Kernel DT\"\n \tdepends on PCIE_LAYERSCAPE\n \tdefault \"fsl,ls1012a-pcie\" if ARCH_LS1012A\n+\tdefault \"fsl,ls1028a-pcie\" if ARCH_LS1028A\n \tdefault \"fsl,ls1043a-pcie\" if ARCH_LS1043A\n \tdefault \"fsl,ls1046a-pcie\" if ARCH_LS1046A\n \tdefault \"fsl,ls2080a-pcie\" if ARCH_LS2080A\n@@ -343,6 +378,7 @@ config SYS_FSL_ERRATUM_A010539\n \n config MAX_CPUS\n \tint \"Maximum number of CPUs permitted for Layerscape\"\n+\tdefault 2 if ARCH_LS1028A\n \tdefault 4 if ARCH_LS1043A\n \tdefault 4 if ARCH_LS1046A\n \tdefault 16 if ARCH_LS2080A\n@@ -377,7 +413,7 @@ config QSPI_AHB_INIT\n config SYS_CCI400_OFFSET\n \thex \"Offset for CCI400 base\"\n \tdepends on SYS_FSL_HAS_CCI400\n-\tdefault 0x3090000 if ARCH_LS1088A\n+\tdefault 0x3090000 if ARCH_LS1088A || ARCH_LS1028A\n \tdefault 0x180000 if FSL_LSCH2\n \thelp\n \t Offset for CCI400 base\n@@ -446,6 +482,7 @@ config CLUSTER_CLK_FREQ\n \n config SYS_FSL_PCLK_DIV\n \tint \"Platform clock divider\"\n+\tdefault 1 if ARCH_LS1028A\n \tdefault 1 if ARCH_LS1043A\n \tdefault 1 if ARCH_LS1046A\n \tdefault 1 if ARCH_LS1088A\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile\nindex e9bc987..a8d3cf9 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile\n@@ -48,3 +48,7 @@ endif\n ifneq ($(CONFIG_ARCH_LS1088A),)\n obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o\n endif\n+\n+ifneq ($(CONFIG_ARCH_LS1028A),)\n+obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o\n+endif\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\nindex 978d46b..c258f2e 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\n@@ -58,6 +58,7 @@ static struct cpu_type cpu_type_list[] = {\n \tCPU_TYPE_ENTRY(LS1026A, LS1026A, 2),\n \tCPU_TYPE_ENTRY(LS2040A, LS2040A, 4),\n \tCPU_TYPE_ENTRY(LS1012A, LS1012A, 1),\n+\tCPU_TYPE_ENTRY(LS1028A, LS1028A, 2),\n \tCPU_TYPE_ENTRY(LS1088A, LS1088A, 8),\n \tCPU_TYPE_ENTRY(LS1084A, LS1084A, 8),\n \tCPU_TYPE_ENTRY(LS1048A, LS1048A, 4),\n@@ -246,11 +247,13 @@ static struct mm_region final_map[] = {\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN\n \t},\n+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR\n \t{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,\n \t CONFIG_SYS_PCIE3_PHYS_SIZE,\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN\n \t},\n+#endif\n #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)\n \t{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,\n \t CONFIG_SYS_PCIE4_PHYS_SIZE,\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc\nindex a0e2621..ad55573 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc\n@@ -8,6 +8,7 @@ SoC overview\n \t6. LS2088A\n \t7. LS2081A\n \t8. LX2160A\n+\t9. LS1028A\n \n LS1043A\n ---------\n@@ -328,3 +329,53 @@ LX2160A SoC has 2 more similar SoC personalities\n \n 2)LX2080A, few difference w.r.t. LX2160A:\n a) Eight 64-bit ARM v8 Cortex-A72 CPUs\n+\n+\n+LS1028A\n+--------\n+The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with\n+a GPU and LCD controller, as well as two TSN-enabled Ethernet controllers and\n+a TSNenabled 4-port switch.\n+\n+The high performance Cortex-A72 cores, performing above 16,000 CoreMarks,\n+combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and\n+Octal/Quad SPI interfaces provide capabilities for a number of industrial and\n+embedded applications. The device provides excellent integration with the\n+new Time-Sensitive Networking standard, and enables a number of\n+TSN applications.\n+\n+The LS1028A SoC includes the following function and features:\n+ - Two 64-bit ARM v8 A72 CPUs\n+ - Cache Coherent interconnect (CCI-400)\n+ - One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC\n+ - eDP/Displayport interface\n+ - Graphics processing unit\n+ - One Configurable x4 SerDes\n+ - Ethernet interfaces\n+ - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one\n+ ethernet MAC supporting 1G, 100M, 10M.\n+ - Switched: TSN IP to support four 2.5/1G interfaces.\n+ - None of the MACs support MACSEC\n+ - Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII\n+ - Support for 10G-SXGMII and 10G-QXGMII.\n+ - Energy efficient Ethernet support (802.3az)\n+ - IEEE 1588 support\n+ - High-speed peripheral interfaces\n+ - Two PCIe 3.0 controllers, one supporting x4 operation\n+ - One serial ATA (SATA 3.0) controller\n+ - Additional peripheral interfaces\n+ - Two high-speed USB 2.0/3.0 controllers with integrated PHY each\n+ supporting host or device modes\n+ - Two Enhanced secure digital host controllers (SD/SDIO/eMMC)\n+ - Two Serial peripheral interface (SPI) controllers\n+ - Eight I2C controllers\n+ - Two UART controllers\n+ - Additional six Industrual UARTs (LPUART).\n+ - One FlexSPI controller\n+ - General Purpose IO (GPIO)\n+ - Two CAN-FD interfaces\n+ - Eight Flextimers with PWM I/O\n+ - Support for hardware virtualization and partitioning enforcement\n+ - Layerscape Trust Architecture\n+ - Service Processor (SP) provides pre-boot initialization and secure-boot\n+ capabilities\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c\nnew file mode 100644\nindex 0000000..ef598c4\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c\n@@ -0,0 +1,73 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2019 NXP\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/fsl_serdes.h>\n+\n+struct serdes_config {\n+\tu32 protocol;\n+\tu8 lanes[SRDS_MAX_LANES];\n+\tu8 rcw_lanes[SRDS_MAX_LANES];\n+};\n+\n+static struct serdes_config serdes1_cfg_tbl[] = {\n+\t/* SerDes 1 */\n+\t{0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} },\n+\t{0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} },\n+\t{0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} },\n+\t{0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} },\n+\t{0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },\n+\t{0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },\n+\t{0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },\n+\t{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },\n+\t{}\n+};\n+\n+static struct serdes_config *serdes_cfg_tbl[] = {\n+\tserdes1_cfg_tbl,\n+};\n+\n+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)\n+{\n+\tstruct serdes_config *ptr;\n+\n+\tif (serdes >= ARRAY_SIZE(serdes_cfg_tbl))\n+\t\treturn 0;\n+\n+\tptr = serdes_cfg_tbl[serdes];\n+\twhile (ptr->protocol) {\n+\t\tif (ptr->protocol == cfg)\n+\t\t\treturn ptr->lanes[lane];\n+\t\tptr++;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int is_serdes_prtcl_valid(int serdes, u32 prtcl)\n+{\n+\tint i;\n+\tstruct serdes_config *ptr;\n+\n+\tif (serdes >= ARRAY_SIZE(serdes_cfg_tbl))\n+\t\treturn 0;\n+\n+\tptr = serdes_cfg_tbl[serdes];\n+\twhile (ptr->protocol) {\n+\t\tif (ptr->protocol == prtcl)\n+\t\t\tbreak;\n+\t\tptr++;\n+\t}\n+\n+\tif (!ptr->protocol)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < SRDS_MAX_LANES; i++) {\n+\t\tif (ptr->lanes[i] != NONE)\n+\t\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi\nnew file mode 100644\nindex 0000000..1274d2c\n--- /dev/null\n+++ b/arch/arm/dts/fsl-ls1028a.dtsi\n@@ -0,0 +1,280 @@\n+// SPDX-License-Identifier: GPL-2.0+ OR X11\n+/*\n+ * NXP ls1028a SOC common device tree source\n+ *\n+ * Copyright 2019 NXP\n+ *\n+ */\n+\n+/ {\n+\tcompatible = \"fsl,ls1028a\";\n+\tinterrupt-parent = <&gic>;\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\tsysclk: sysclk {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <100000000>;\n+\t\tclock-output-names = \"sysclk\";\n+\t};\n+\n+\tclockgen: clocking@1300000 {\n+\t\tcompatible = \"fsl,ls1028a-clockgen\";\n+\t\treg = <0x0 0x1300000 0x0 0xa0000>;\n+\t\t#clock-cells = <2>;\n+\t\tclocks = <&sysclk>;\n+\t};\n+\n+\tmemory@01080000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x00000000 0x01080000 0 0x80000000>;\n+\t\t /* DRAM space - 1, size : 2 GB DRAM */\n+\t};\n+\n+\tgic: interrupt-controller@6000000 {\n+\t\tcompatible = \"arm,gic-v3\";\n+\t\treg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */\n+\t\t\t <0x0 0x06040000 0 0x40000>;\n+\t\t#interrupt-cells = <3>;\n+\t\tinterrupt-controller;\n+\t\tinterrupts = <1 9 0x4>;\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */\n+\t\t\t <1 14 0x8>, /* Physical Non-Secure PPI, active-low */\n+\t\t\t <1 11 0x8>, /* Virtual PPI, active-low */\n+\t\t\t <1 10 0x8>; /* Hypervisor PPI, active-low */\n+\t};\n+\n+\tfspi: flexspi@20C0000 {\n+\t\tcompatible = \"nxp,dn-fspi\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x20C0000 0x0 0x10000>,\n+\t\t\t<0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/\n+\t\treg-names = \"FSPI\", \"FSPI-memory\";\n+\t\tnum-cs = <1>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tserial0: serial@21c0500 {\n+\t\tdevice_type = \"serial\";\n+\t\tcompatible = \"fsl,ns16550\", \"ns16550a\";\n+\t\treg = <0x0 0x21c0500 0x0 0x100>;\n+\t\tinterrupts = <0 32 0x1>; /* edge triggered */\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tserial1: serial@21c0600 {\n+\t\tdevice_type = \"serial\";\n+\t\tcompatible = \"fsl,ns16550\", \"ns16550a\";\n+\t\treg = <0x0 0x21c0600 0x0 0x100>;\n+\t\tinterrupts = <0 32 0x1>; /* edge triggered */\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tpcie@3400000 {\n+\t compatible = \"fsl,ls-pcie\", \"fsl,ls1028-pcie\", \"snps,dw-pcie\";\n+\t reg = <0x00 0x03400000 0x0 0x80000\n+\t\t 0x00 0x03480000 0x0 0x40000 /* lut registers */\n+\t\t 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */\n+\t\t 0x80 0x00000000 0x0 0x20000>; /* configuration space */\n+\t reg-names = \"dbi\", \"lut\", \"ctrl\", \"config\";\n+\t #address-cells = <3>;\n+\t #size-cells = <2>;\n+\t device_type = \"pci\";\n+\t num-lanes = <4>;\n+\t bus-range = <0x0 0xff>;\n+\t ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */\n+\t\t 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */\n+\t};\n+\n+\tpcie@3500000 {\n+\t compatible = \"fsl,ls-pcie\", \"fsl,ls1028-pcie\", \"snps,dw-pcie\";\n+\t reg = <0x00 0x03500000 0x0 0x80000\n+\t\t 0x00 0x03580000 0x0 0x40000 /* lut registers */\n+\t\t 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */\n+\t\t 0x88 0x00000000 0x0 0x20000>; /* configuration space */\n+\t reg-names = \"dbi\", \"lut\", \"ctrl\", \"config\";\n+\t #address-cells = <3>;\n+\t #size-cells = <2>;\n+\t device_type = \"pci\";\n+\t num-lanes = <4>;\n+\t bus-range = <0x0 0xff>;\n+\t ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */\n+\t\t 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */\n+\t};\n+\n+\ti2c0: i2c@2000000 {\n+\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2000000 0x0 0x10000>;\n+\t\tinterrupts = <0 34 0x4>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\ti2c1: i2c@2010000 {\n+\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2010000 0x0 0x10000>;\n+\t\tinterrupts = <0 34 0x4>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\ti2c2: i2c@2020000 {\n+\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2020000 0x0 0x10000>;\n+\t\tinterrupts = <0 35 0x4>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\ti2c3: i2c@2030000 {\n+\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2030000 0x0 0x10000>;\n+\t\tinterrupts = <0 35 0x4>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\ti2c4: i2c@2040000 {\n+\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2040000 0x0 0x10000>;\n+\t\tinterrupts = <0 74 0x4>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\ti2c5: i2c@2050000 {\n+\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2050000 0x0 0x10000>;\n+\t\tinterrupts = <0 74 0x4>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\ti2c6: i2c@2060000 {\n+\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2060000 0x0 0x10000>;\n+\t\tinterrupts = <0 75 0x4>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\ti2c7: i2c@2070000 {\n+\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2070000 0x0 0x10000>;\n+\t\tinterrupts = <0 75 0x4>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tusb1: usb3@3100000 {\n+\t\tcompatible = \"fsl,layerscape-dwc3\";\n+\t\treg = <0x0 0x3100000 0x0 0x10000>;\n+\t\tinterrupts = <0 80 0x4>;\n+\t\tdr_mode = \"host\";\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tusb2: usb3@3110000 {\n+\t\tcompatible = \"fsl,layerscape-dwc3\";\n+\t\treg = <0x0 0x3110000 0x0 0x10000>;\n+\t\tinterrupts = <0 81 0x4>;\n+\t\tdr_mode = \"host\";\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tdspi0: dspi@2100000 {\n+\t\tcompatible = \"fsl,vf610-dspi\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2100000 0x0 0x10000>;\n+\t\tinterrupts = <0 26 0x4>;\n+\t\tclock-names = \"dspi\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tnum-cs = <5>;\n+\t\tlitte-endian;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tdspi1: dspi@2110000 {\n+\t\tcompatible = \"fsl,vf610-dspi\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2110000 0x0 0x10000>;\n+\t\tinterrupts = <0 26 0x4>;\n+\t\tclock-names = \"dspi\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tnum-cs = <5>;\n+\t\tlittle-endian;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tdspi2: dspi@2120000 {\n+\t\tcompatible = \"fsl,vf610-dspi\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2120000 0x0 0x10000>;\n+\t\tinterrupts = <0 26 0x4>;\n+\t\tclock-names = \"dspi\";\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tnum-cs = <5>;\n+\t\tlittle-endian;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tesdhc0: esdhc@2140000 {\n+\t\tcompatible = \"fsl,esdhc\";\n+\t\treg = <0x0 0x2140000 0x0 0x10000>;\n+\t\tinterrupts = <0 28 0x4>;\n+\t\tbig-endian;\n+\t\tbus-width = <4>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tesdhc1: esdhc@2150000 {\n+\t\tcompatible = \"fsl,esdhc\";\n+\t\treg = <0x0 0x2150000 0x0 0x10000>;\n+\t\tinterrupts = <0 63 0x4>;\n+\t\tbig-endian;\n+\t\tnon-removable;\n+\t\tbus-width = <4>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tsata: sata@3200000 {\n+\t\tcompatible = \"fsl,ls1028a-ahci\";\n+\t\treg = <0x0 0x3200000 0x0 0x10000>;\n+\t\tinterrupts = <0 133 4>;\n+\t\tclocks = <&clockgen 4 1>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h\nindex 903d509..eb21c09 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h\n@@ -229,6 +229,67 @@\n \n #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC\t\t1\n \n+#elif defined(CONFIG_ARCH_LS1028A)\n+#define CONFIG_SYS_FSL_NUM_CC_PLLS\t\t3\n+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS\t\t{ 1, 1 }\n+#define CONFIG_GICV3\n+#define CONFIG_FSL_TZPC_BP147\n+#define CONFIG_FSL_TZASC_400\n+\n+/* TZ Protection Controller Definitions */\n+#define TZPC_BASE\t\t\t\t0x02200000\n+#define TZPCR0SIZE_BASE\t\t\t\t(TZPC_BASE)\n+#define TZPCDECPROT_0_STAT_BASE\t\t\t(TZPC_BASE + 0x800)\n+#define TZPCDECPROT_0_SET_BASE\t\t\t(TZPC_BASE + 0x804)\n+#define TZPCDECPROT_0_CLR_BASE\t\t\t(TZPC_BASE + 0x808)\n+#define TZPCDECPROT_1_STAT_BASE\t\t\t(TZPC_BASE + 0x80C)\n+#define TZPCDECPROT_1_SET_BASE\t\t\t(TZPC_BASE + 0x810)\n+#define TZPCDECPROT_1_CLR_BASE\t\t\t(TZPC_BASE + 0x814)\n+#define TZPCDECPROT_2_STAT_BASE\t\t\t(TZPC_BASE + 0x818)\n+#define TZPCDECPROT_2_SET_BASE\t\t\t(TZPC_BASE + 0x81C)\n+#define TZPCDECPROT_2_CLR_BASE\t\t\t(TZPC_BASE + 0x820)\n+\n+#define\tSRDS_MAX_LANES\t4\n+\n+#define CONFIG_SYS_FSL_OCRAM_BASE\t\t0x18000000 /* initial RAM */\n+#define SYS_FSL_OCRAM_SPACE_SIZE\t\t0x00200000 /* 2M */\n+#define CONFIG_SYS_FSL_OCRAM_SIZE\t\t0x00040000 /* Real size 256K */\n+\n+/* Generic Interrupt Controller Definitions */\n+#define GICD_BASE\t\t\t\t0x06000000\n+#define GICR_BASE\t\t\t\t0x06040000\n+\n+/* SMMU Definitions */\n+#define SMMU_BASE\t\t\t\t0x05000000 /* GR0 Base */\n+\n+/* DDR */\n+#define CONFIG_SYS_DDR_BLOCK1_SIZE\t((phys_size_t)2 << 30)\n+#define CONFIG_MAX_MEM_MAPPED\t\tCONFIG_SYS_DDR_BLOCK1_SIZE\n+\n+#define CONFIG_SYS_FSL_CCSR_GUR_LE\n+#define CONFIG_SYS_FSL_CCSR_SCFG_LE\n+#define CONFIG_SYS_FSL_ESDHC_LE\n+#define CONFIG_SYS_FSL_PEX_LUT_LE\n+\n+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN\n+\n+/* SFP */\n+#define CONFIG_SYS_FSL_SFP_VER_3_4\n+#define CONFIG_SYS_FSL_SFP_LE\n+#define CONFIG_SYS_FSL_SRK_LE\n+\n+/* SEC */\n+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC\t\t1\n+\n+/* Security Monitor */\n+#define CONFIG_SYS_FSL_SEC_MON_LE\n+\n+/* Secure Boot */\n+#define CONFIG_ESBC_HDR_LS\n+\n+/* DCFG - GUR */\n+#define CONFIG_SYS_FSL_CCSR_GUR_LE\n+\n #elif defined(CONFIG_FSL_LSCH2)\n #define CONFIG_SYS_FSL_OCRAM_BASE\t\t0x10000000 /* initial RAM */\n #define SYS_FSL_OCRAM_SPACE_SIZE\t\t0x00200000 /* 2M space */\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 9fab88a..dbf3215 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -171,6 +171,9 @@\n #define CONFIG_SYS_PCIE1_PHYS_ADDR\t\t0x2000000000ULL\n #define CONFIG_SYS_PCIE2_PHYS_ADDR\t\t0x2800000000ULL\n #define CONFIG_SYS_PCIE3_PHYS_ADDR\t\t0x3000000000ULL\n+#elif CONFIG_ARCH_LS1028A\n+#define CONFIG_SYS_PCIE1_PHYS_ADDR\t\t0x8000000000ULL\n+#define CONFIG_SYS_PCIE2_PHYS_ADDR\t\t0x8800000000ULL\n #else\n #define CONFIG_SYS_PCIE1_PHYS_ADDR\t\t0x1000000000ULL\n #define CONFIG_SYS_PCIE2_PHYS_ADDR\t\t0x1200000000ULL\n@@ -375,6 +378,12 @@ struct ccsr_gur {\n #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT\tFSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT\n #define FSL_CHASSIS3_SRDS1_REGSR\t29\n #define FSL_CHASSIS3_SRDS2_REGSR\t30\n+#elif defined(CONFIG_ARCH_LS1028A)\n+#define\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK\t0xFFFF0000\n+#define\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT\t16\n+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK\n+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT\n+#define FSL_CHASSIS3_SRDS1_REGSR\t29\n #endif\n #define RCW_SB_EN_REG_INDEX\t9\n #define RCW_SB_EN_MASK\t\t0x00000400\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h\nindex 7d95c4e..234440b 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h\n@@ -83,6 +83,7 @@ enum boot_src get_boot_src(void);\n /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */\n #define SVR_LS1043A_P23\t\t0x879202\n #define SVR_LS1023A_P23\t\t0x87920A\n+#define SVR_LS1028A\t\t0x870B00\n #define SVR_LS1046A\t\t0x870700\n #define SVR_LS1026A\t\t0x870708\n #define SVR_LS1048A\t\t0x870320\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\nindex e017d8b..c53cc57 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\n@@ -87,7 +87,7 @@\n #define FSL_PEX_STREAM_ID_NUM\t\t(0x100)\n #endif\n \n-#if defined(CONFIG_ARCH_LS2080A)\n+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A)\n #define FSL_PEX_STREAM_ID_END\t\t22\n #elif defined(CONFIG_ARCH_LS1088A)\n #define FSL_PEX_STREAM_ID_END\t\t18\n", "prefixes": [ "U-Boot", "1/3", "v3" ] }