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GET /api/patches/1081610/?format=api
{ "id": 1081610, "url": "http://patchwork.ozlabs.org/api/patches/1081610/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190408235202.10676-2-jacob.e.keller@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190408235202.10676-2-jacob.e.keller@intel.com>", "list_archive_url": null, "date": "2019-04-08T23:51:59", "name": "[2/5] ixgbe: fix PTP SDP pin setup on X540 hardware", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "8e237f471b5db298112400109ae029f8b245b912", "submitter": { "id": 9784, "url": "http://patchwork.ozlabs.org/api/people/9784/?format=api", "name": "Jacob Keller", "email": "jacob.e.keller@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190408235202.10676-2-jacob.e.keller@intel.com/mbox/", "series": [ { "id": 101594, "url": "http://patchwork.ozlabs.org/api/series/101594/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=101594", "date": "2019-04-08T23:51:58", "name": "[1/5] ixgbe: reduce PTP Tx timestamp timeout to 1 second", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/101594/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1081610/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1081610/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 44dRzd75QSz9sNr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 9 Apr 2019 09:52:13 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 72A4E279B9;\n\tMon, 8 Apr 2019 23:52:12 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id CMcjnc4TXcQX; Mon, 8 Apr 2019 23:52:10 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 0AE40283E2;\n\tMon, 8 Apr 2019 23:52:10 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 4FCD71BF279\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 8 Apr 2019 23:52:07 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 4D0F487C9F\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 8 Apr 2019 23:52:07 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id UeQnueYy-Tw0 for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 8 Apr 2019 23:52:06 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 9FBB287D46\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 8 Apr 2019 23:52:06 +0000 (UTC)", "from orsmga006.jf.intel.com ([10.7.209.51])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t08 Apr 2019 16:52:05 -0700", "from jekeller-desk.amr.corp.intel.com ([10.166.244.182])\n\tby orsmga006.jf.intel.com with ESMTP; 08 Apr 2019 16:52:05 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.60,327,1549958400\"; d=\"scan'208\";a=\"134096402\"", "From": "Jacob Keller <jacob.e.keller@intel.com>", "To": "Intel Wired LAN <intel-wired-lan@lists.osuosl.org>", "Date": "Mon, 8 Apr 2019 16:51:59 -0700", "Message-Id": "<20190408235202.10676-2-jacob.e.keller@intel.com>", "X-Mailer": "git-send-email 2.21.0.564.g2d7e7e4d310b", "In-Reply-To": "<20190408235202.10676-1-jacob.e.keller@intel.com>", "References": "<20190408235202.10676-1-jacob.e.keller@intel.com>", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH 2/5] ixgbe: fix PTP SDP pin setup on X540\n\thardware", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "The function ixgbe_ptp_setup_sdp_X540 attempts to program a software\ndefined pin, in order to generate a pulse-per-second output on SDP 0.\n\nIt does work to generate the output, but does not align the output on\nthe full second. Additionally, it does not take into account the\ncyclecounter multiplier. This leads to somewhat confusing code which is\nlikely to be incorrect if blindly copied to another hardware type.\n\nUpdate this code to account for the cyclecounter multiplier, and to\ndirectly use timecounter_read.\n\nThis change ensures that the SDP output will align properly on a full\nsecond, and makes the intent of the calculations a bit more clear.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\n---\n drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c | 71 ++++++++++++--------\n 1 file changed, 42 insertions(+), 29 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c\nindex dbe84a4d2f7f..047767408df0 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c\n@@ -74,11 +74,11 @@\n #define IXGBE_OVERFLOW_PERIOD (HZ * 30)\n #define IXGBE_PTP_TX_TIMEOUT (HZ)\n \n-/* half of a one second clock period, for use with PPS signal. We have to use\n- * this instead of something pre-defined like IXGBE_PTP_PPS_HALF_SECOND, in\n- * order to force at least 64bits of precision for shifting\n+/* We use our own definitions instead of NSEC_PER_SEC because we want to mark\n+ * the value as a ULL to force precision when bit shifting.\n */\n-#define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL\n+#define NS_PER_SEC 1000000000ULL\n+#define NS_PER_HALF_SEC 500000000ULL\n \n /* In contrast, the X550 controller has two registers, SYSTIMEH and SYSTIMEL\n * which contain measurements of seconds and nanoseconds respectively. This\n@@ -141,23 +141,26 @@\n #define MAX_TIMADJ\t0x7FFFFFFF\n \n /**\n- * ixgbe_ptp_setup_sdp_x540\n+ * ixgbe_ptp_setup_sdp_X540\n * @adapter: private adapter structure\n *\n * this function enables or disables the clock out feature on SDP0 for\n- * the X540 device. It will create a 1second periodic output that can\n+ * the X540 device. It will create a 1 second periodic output that can\n * be used as the PPS (via an interrupt).\n *\n- * It calculates when the systime will be on an exact second, and then\n- * aligns the start of the PPS signal to that value. The shift is\n- * necessary because it can change based on the link speed.\n+ * It calculates when the system time will be on an exact second, and then\n+ * aligns the start of the PPS signal to that value.\n+ *\n+ * This works by using the cycle counter shift and mult values in reverse, and\n+ * assumes that the values we're shifting will not overflow.\n */\n-static void ixgbe_ptp_setup_sdp_x540(struct ixgbe_adapter *adapter)\n+static void ixgbe_ptp_setup_sdp_X540(struct ixgbe_adapter *adapter)\n {\n+\tstruct cyclecounter *cc = &adapter->hw_cc;\n \tstruct ixgbe_hw *hw = &adapter->hw;\n-\tint shift = adapter->hw_cc.shift;\n \tu32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;\n-\tu64 ns = 0, clock_edge = 0;\n+\tu64 ns = 0, clock_edge = 0, clock_period;\n+\tunsigned long flags;\n \n \t/* disable the pin first */\n \tIXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);\n@@ -177,26 +180,36 @@ static void ixgbe_ptp_setup_sdp_x540(struct ixgbe_adapter *adapter)\n \t/* enable the Clock Out feature on SDP0, and allow\n \t * interrupts to occur when the pin changes\n \t */\n-\ttsauxc = IXGBE_TSAUXC_EN_CLK |\n-\t\t IXGBE_TSAUXC_SYNCLK |\n-\t\t IXGBE_TSAUXC_SDP0_INT;\n+\ttsauxc = (IXGBE_TSAUXC_EN_CLK |\n+\t\t IXGBE_TSAUXC_SYNCLK |\n+\t\t IXGBE_TSAUXC_SDP0_INT);\n \n-\t/* clock period (or pulse length) */\n-\tclktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift);\n-\tclktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32);\n-\n-\t/* Account for the cyclecounter wrap-around value by\n-\t * using the converted ns value of the current time to\n-\t * check for when the next aligned second would occur.\n+\t/* Determine the clock time period to use. This assumes that the\n+\t * cycle counter shift is small enough to avoid overflow.\n \t */\n-\tclock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);\n-\tclock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;\n-\tns = timecounter_cyc2time(&adapter->hw_tc, clock_edge);\n+\tclock_period = div_u64((NS_PER_HALF_SEC << cc->shift), cc->mult);\n+\tclktiml = (u32)(clock_period);\n+\tclktimh = (u32)(clock_period >> 32);\n \n-\tdiv_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem);\n-\tclock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift);\n+\t/* Read the current clock time, and save the cycle counter value */\n+\tspin_lock_irqsave(&adapter->tmreg_lock, flags);\n+\tns = timecounter_read(&adapter->hw_tc);\n+\tclock_edge = adapter->hw_tc.cycle_last;\n+\tspin_unlock_irqrestore(&adapter->tmreg_lock, flags);\n \n-\t/* specify the initial clock start time */\n+\t/* Figure out how many seconds to add in order to round up */\n+\tdiv_u64_rem(ns, NS_PER_SEC, &rem);\n+\n+\t/* Figure out how many nanoseconds to add to round the clock edge up\n+\t * to the next full second\n+\t */\n+\trem = (NS_PER_SEC - rem);\n+\n+\t/* Adjust the clock edge to align with the next full second. This\n+\t * assumes that the cycle counter shift is small enough to avoid\n+\t * overflowing when shifting the remainder.\n+\t */\n+\tclock_edge += div_u64((rem << cc->shift), cc->mult);\n \ttrgttiml = (u32)clock_edge;\n \ttrgttimh = (u32)(clock_edge >> 32);\n \n@@ -1253,7 +1266,7 @@ static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)\n \t\tadapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;\n \t\tadapter->ptp_caps.settime64 = ixgbe_ptp_settime;\n \t\tadapter->ptp_caps.enable = ixgbe_ptp_feature_enable;\n-\t\tadapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_x540;\n+\t\tadapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_X540;\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \t\tsnprintf(adapter->ptp_caps.name,\n", "prefixes": [ "2/5" ] }