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GET /api/patches/1080853/?format=api
{ "id": 1080853, "url": "http://patchwork.ozlabs.org/api/patches/1080853/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190408101708.23251-7-Zhiqiang.Hou@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190408101708.23251-7-Zhiqiang.Hou@nxp.com>", "list_archive_url": null, "date": "2019-04-08T10:15:54", "name": "[U-Boot,PATCHv5,6/8] pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs", "commit_ref": "1d341bc4b6b357e7348ab4393247e369aeb30aa6", "pull_url": null, "state": "accepted", "archived": false, "hash": "2919da182e1ad4c534b4beea007d30552cb2123f", "submitter": { "id": 67929, "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api", "name": "Z.Q. Hou", "email": "zhiqiang.hou@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190408101708.23251-7-Zhiqiang.Hou@nxp.com/mbox/", "series": [ { "id": 101447, "url": "http://patchwork.ozlabs.org/api/series/101447/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=101447", "date": "2019-04-08T10:15:28", "name": "pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/101447/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1080853/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1080853/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"fILaQE1W\";\n\tdkim-atps=neutral", "spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; " ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 44d5xn1wstz9sQq\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 8 Apr 2019 20:19:24 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 93669C21E29; Mon, 8 Apr 2019 10:17:58 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id E3835C21E74;\n\tMon, 8 Apr 2019 10:16:47 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid DBE22C21DF8; Mon, 8 Apr 2019 10:16:03 +0000 (UTC)", "from EUR02-AM5-obe.outbound.protection.outlook.com\n\t(mail-eopbgr00084.outbound.protection.outlook.com [40.107.0.84])\n\tby lists.denx.de (Postfix) with ESMTPS id 95015C21E0D\n\tfor <u-boot@lists.denx.de>; Mon, 8 Apr 2019 10:15:59 +0000 (UTC)", "from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.3.19) by\n\tAM6PR04MB4533.eurprd04.prod.outlook.com (20.177.38.21) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1771.16; Mon, 8 Apr 2019 10:15:54 +0000", "from AM6PR04MB5781.eurprd04.prod.outlook.com\n\t([fe80::f9db:ed86:614e:460]) by\n\tAM6PR04MB5781.eurprd04.prod.outlook.com\n\t([fe80::f9db:ed86:614e:460%3]) with mapi id 15.20.1771.014;\n\tMon, 8 Apr 2019 10:15:54 +0000" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=SPF_HELO_PASS, T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=woMqArCCp0nvKdGKpXUW/Q0wok+y3V0h8RRprWryd9Y=;\n\tb=fILaQE1WPsk0qwW24J56itM13VxRrVL9ubLl/oWA8QU0wT75zeKcQur6g2vfTa+bjAd3qUzWDBOHYybfm+mGvAkeWCjDLj8JtSFrO00zhwZ4/64eON1pFvCehc7pT88XJ2+6tBH6GHq2/qM1pvpkDFS7CjUk4PGZSYF763TEnZA=", "From": "\"Z.q. Hou\" <zhiqiang.hou@nxp.com>", "To": "\"u-boot@lists.denx.de\" <u-boot@lists.denx.de>,\n\t\"albert.u.boot@aribaud.net\"\n\t<albert.u.boot@aribaud.net>, Priyanka Jain <priyanka.jain@nxp.com>,\n\tYork Sun <york.sun@nxp.com>,\n\t\"sriram.dash@nxp.com\" <sriram.dash@nxp.com>, \n\t\"yamada.masahiro@socionext.com\" <yamada.masahiro@socionext.com>,\n\tPrabhakar\n\tKushwaha <prabhakar.kushwaha@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com>,\n\t\"M.h. Lian\" <minghuan.lian@nxp.com>,\n\t\"bmeng.cn@gmail.com\" <bmeng.cn@gmail.com>", "Thread-Topic": "[PATCHv5 6/8] pci: ls_pcie_g4: add device tree fixups for PCI\n\tStream IDs", "Thread-Index": "AQHU7fQNToDtmwhzfEGbfLuoyWhrPg==", "Date": "Mon, 8 Apr 2019 10:15:54 +0000", "Message-ID": "<20190408101708.23251-7-Zhiqiang.Hou@nxp.com>", "References": "<20190408101708.23251-1-Zhiqiang.Hou@nxp.com>", "In-Reply-To": "<20190408101708.23251-1-Zhiqiang.Hou@nxp.com>", "Accept-Language": "zh-CN, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "HK0PR03CA0107.apcprd03.prod.outlook.com\n\t(2603:1096:203:b0::23) To AM6PR04MB5781.eurprd04.prod.outlook.com\n\t(2603:10a6:20b:ad::19)", "authentication-results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"fILaQE1W\";\n\tdkim-atps=neutral", "spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; " ], "x-ms-exchange-messagesentrepresentingtype": "1", "x-mailer": "git-send-email 2.17.1", "x-originating-ip": "[119.31.174.73]", "x-ms-publictraffictype": "Email", "x-ms-office365-filtering-correlation-id": "f3129f11-15f3-410a-ad85-08d6bc0b2f59", "x-ms-office365-filtering-ht": "Tenant", "x-microsoft-antispam": "BCL:0; PCL:0;\n\tRULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);\n\tSRVR:AM6PR04MB4533; ", "x-ms-traffictypediagnostic": "AM6PR04MB4533:", "x-microsoft-antispam-prvs": "<AM6PR04MB45333CC76A2081685956E19F842C0@AM6PR04MB4533.eurprd04.prod.outlook.com>", "x-forefront-prvs": "0001227049", "x-forefront-antispam-report": "SFV:NSPM;\n\tSFS:(10009020)(136003)(39860400002)(396003)(366004)(346002)(376002)(189003)(199004)(186003)(36756003)(11346002)(102836004)(2501003)(316002)(76176011)(14444005)(6506007)(386003)(25786009)(26005)(52116002)(110136005)(66066001)(68736007)(476003)(8936002)(81166006)(50226002)(81156014)(4326008)(256004)(106356001)(1076003)(71200400001)(71190400001)(105586002)(86362001)(2616005)(2201001)(2906002)(7736002)(8676002)(99286004)(486006)(53936002)(6512007)(6116002)(3846002)(6436002)(446003)(478600001)(6486002)(97736004)(305945005)(14454004)(5660300002)(921003)(1121003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4533;\n\tH:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; MX:1; A:1; ", "received-spf": "None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)", "x-ms-exchange-senderadcheck": "1", "x-microsoft-antispam-message-info": "kGcg2gqdA013syNOH6gDv1IBM+vfgIdD9BtPck6Ax666OoOwc/CQw1pdPYZGl8JWuuowB2b4dufji34N57oWYQETMT8L7msQZHoiJCrBWqToVy+Y3Bwpd1LnXGVODA/SfnEEeBh4POltCv3MBQGnoWRoPVj1/p/sLHpqVwrkjx4l8iBw9oLcMIeGKBANXm3TCRv5rgQOPhLKHqFJRizNa24n6hA91Rprm9896BYIT5r0LEkAPZ6ic9hfgtiVdpJ7eQpttZNjJ1+X2DB+AldKfaRGFp87KWVJK193HPayrkc7suJSbMxfPipyyltl6TqfqXllmmSvDec+eJg0F3kgK6J3/yCFVX74Iy/YowWLCFb0W/lwnm3nBgJBE1uqXYT6MXZnl+okfmkaS/BsjAzE8WVVg4wB+/E163mDhdqXjVY=", "MIME-Version": "1.0", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "f3129f11-15f3-410a-ad85-08d6bc0b2f59", "X-MS-Exchange-CrossTenant-originalarrivaltime": "08 Apr 2019 10:15:54.8224\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM6PR04MB4533", "Cc": "\"Z.q. Hou\" <zhiqiang.hou@nxp.com>", "Subject": "[U-Boot] [PATCHv5 6/8] pci: ls_pcie_g4: add device tree fixups for\n\tPCI Stream IDs", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nAdd the infrastructure for Layerscape SoCs PCIe Gen4 controller\nto update device tree nodes to convey SMMU stream IDs in the\ndevice tree.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n---\nV5:\n - Updated the Copyright\n\n drivers/pci/Makefile | 3 +-\n drivers/pci/pcie_layerscape_gen4.c | 5 -\n drivers/pci/pcie_layerscape_gen4_fixup.c | 249 +++++++++++++++++++++++\n 3 files changed, 251 insertions(+), 6 deletions(-)\n create mode 100644 drivers/pci/pcie_layerscape_gen4_fixup.c", "diff": "diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile\nindex 7f585aad55..8ee828af6d 100644\n--- a/drivers/pci/Makefile\n+++ b/drivers/pci/Makefile\n@@ -32,6 +32,7 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o\n obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o\n obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o\n obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o\n-obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o\n+obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \\\n+\t\t\t\tpcie_layerscape_gen4_fixup.o\n obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o\n obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o\ndiff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c\nindex da77caccfd..1fd8761bbc 100644\n--- a/drivers/pci/pcie_layerscape_gen4.c\n+++ b/drivers/pci/pcie_layerscape_gen4.c\n@@ -570,8 +570,3 @@ U_BOOT_DRIVER(pcie_layerscape_gen4) = {\n \t.probe\t= ls_pcie_g4_probe,\n \t.priv_auto_alloc_size = sizeof(struct ls_pcie_g4),\n };\n-\n-/* No any fixup so far */\n-void ft_pci_setup(void *blob, bd_t *bd)\n-{\n-}\ndiff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c\nnew file mode 100644\nindex 0000000000..1c9e5750bd\n--- /dev/null\n+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c\n@@ -0,0 +1,249 @@\n+// SPDX-License-Identifier: GPL-2.0+ OR X11\n+/*\n+ * Copyright 2018-2019 NXP\n+ *\n+ * PCIe Gen4 driver for NXP Layerscape SoCs\n+ * Author: Hou Zhiqiang <Minder.Hou@gmail.com>\n+ *\n+ */\n+\n+#include <common.h>\n+#include <pci.h>\n+#include <asm/arch/fsl_serdes.h>\n+#include <asm/io.h>\n+#include <errno.h>\n+#ifdef CONFIG_OF_BOARD_SETUP\n+#include <linux/libfdt.h>\n+#include <fdt_support.h>\n+#ifdef CONFIG_ARM\n+#include <asm/arch/clock.h>\n+#endif\n+#include \"pcie_layerscape_gen4.h\"\n+\n+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)\n+/*\n+ * Return next available LUT index.\n+ */\n+static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)\n+{\n+\tif (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)\n+\t\treturn pcie->next_lut_index++;\n+\n+\treturn -ENOSPC; /* LUT is full */\n+}\n+\n+/* returns the next available streamid for pcie, -errno if failed */\n+static int ls_pcie_g4_next_streamid(struct ls_pcie_g4 *pcie)\n+{\n+\tint stream_id = pcie->stream_id_cur;\n+\n+\tif (stream_id > FSL_PEX_STREAM_ID_NUM)\n+\t\treturn -EINVAL;\n+\n+\tpcie->stream_id_cur++;\n+\n+\treturn stream_id | ((pcie->idx + 1) << 11);\n+}\n+\n+/*\n+ * Program a single LUT entry\n+ */\n+static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,\n+\t\t\t\t u32 devid, u32 streamid)\n+{\n+\t/* leave mask as all zeroes, want to match all bits */\n+\tlut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));\n+\tlut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));\n+}\n+\n+/*\n+ * An msi-map is a property to be added to the pci controller\n+ * node. It is a table, where each entry consists of 4 fields\n+ * e.g.:\n+ *\n+ * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]\n+ * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;\n+ */\n+static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie_g4 *pcie,\n+\t\t\t\t u32 devid, u32 streamid)\n+{\n+\tu32 *prop;\n+\tu32 phandle;\n+\tint nodeoff;\n+\n+#ifdef CONFIG_FSL_PCIE_COMPAT\n+\tnodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,\n+\t\t\t\t\t\tpcie->ccsr_res.start);\n+#else\n+#error \"No CONFIG_FSL_PCIE_COMPAT defined\"\n+#endif\n+\tif (nodeoff < 0) {\n+\t\tdebug(\"%s: ERROR: failed to find pcie compatiable\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\t/* get phandle to MSI controller */\n+\tprop = (u32 *)fdt_getprop(blob, nodeoff, \"msi-parent\", 0);\n+\tif (!prop) {\n+\t\tdebug(\"\\n%s: ERROR: missing msi-parent: PCIe%d\\n\",\n+\t\t __func__, pcie->idx);\n+\t\treturn;\n+\t}\n+\tphandle = fdt32_to_cpu(*prop);\n+\n+\t/* set one msi-map row */\n+\tfdt_appendprop_u32(blob, nodeoff, \"msi-map\", devid);\n+\tfdt_appendprop_u32(blob, nodeoff, \"msi-map\", phandle);\n+\tfdt_appendprop_u32(blob, nodeoff, \"msi-map\", streamid);\n+\tfdt_appendprop_u32(blob, nodeoff, \"msi-map\", 1);\n+}\n+\n+/*\n+ * An iommu-map is a property to be added to the pci controller\n+ * node. It is a table, where each entry consists of 4 fields\n+ * e.g.:\n+ *\n+ * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]\n+ * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;\n+ */\n+static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie_g4 *pcie,\n+\t\t\t\t\t u32 devid, u32 streamid)\n+{\n+\tu32 *prop;\n+\tu32 iommu_map[4];\n+\tint nodeoff;\n+\tint lenp;\n+\n+#ifdef CONFIG_FSL_PCIE_COMPAT\n+\tnodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,\n+\t\t\t\t\t\tpcie->ccsr_res.start);\n+#else\n+#error \"No CONFIG_FSL_PCIE_COMPAT defined\"\n+#endif\n+\tif (nodeoff < 0) {\n+\t\tdebug(\"%s: ERROR: failed to find pcie compatiable\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\t/* get phandle to iommu controller */\n+\tprop = fdt_getprop_w(blob, nodeoff, \"iommu-map\", &lenp);\n+\tif (!prop) {\n+\t\tdebug(\"\\n%s: ERROR: missing iommu-map: PCIe%d\\n\",\n+\t\t __func__, pcie->idx);\n+\t\treturn;\n+\t}\n+\n+\t/* set iommu-map row */\n+\tiommu_map[0] = cpu_to_fdt32(devid);\n+\tiommu_map[1] = *++prop;\n+\tiommu_map[2] = cpu_to_fdt32(streamid);\n+\tiommu_map[3] = cpu_to_fdt32(1);\n+\n+\tif (devid == 0)\n+\t\tfdt_setprop_inplace(blob, nodeoff, \"iommu-map\", iommu_map, 16);\n+\telse\n+\t\tfdt_appendprop(blob, nodeoff, \"iommu-map\", iommu_map, 16);\n+}\n+\n+static void fdt_fixup_pcie(void *blob)\n+{\n+\tstruct udevice *dev, *bus;\n+\tstruct ls_pcie_g4 *pcie;\n+\tint streamid;\n+\tint index;\n+\tpci_dev_t bdf;\n+\n+\t/* Scan all known buses */\n+\tfor (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {\n+\t\tfor (bus = dev; device_is_on_pci_bus(bus);)\n+\t\t\tbus = bus->parent;\n+\t\tpcie = dev_get_priv(bus);\n+\n+\t\tstreamid = ls_pcie_g4_next_streamid(pcie);\n+\t\tif (streamid < 0) {\n+\t\t\tdebug(\"ERROR: no stream ids free\\n\");\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tindex = ls_pcie_g4_next_lut_index(pcie);\n+\t\tif (index < 0) {\n+\t\t\tdebug(\"ERROR: no LUT indexes free\\n\");\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* the DT fixup must be relative to the hose first_busno */\n+\t\tbdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);\n+\t\t/* map PCI b.d.f to streamID in LUT */\n+\t\tls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);\n+\t\t/* update msi-map in device tree */\n+\t\tfdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, streamid);\n+\t\t/* update iommu-map in device tree */\n+\t\tfdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8, streamid);\n+\t}\n+}\n+#endif\n+\n+static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)\n+{\n+\tint off;\n+\n+\toff = fdt_node_offset_by_compat_reg(blob, \"fsl,lx2160a-pcie-ep\",\n+\t\t\t\t\t pcie->ccsr_res.start);\n+\n+\tif (off < 0) {\n+\t\tdebug(\"%s: ERROR: failed to find pcie compatiable\\n\",\n+\t\t __func__);\n+\t\treturn;\n+\t}\n+\n+\tif (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)\n+\t\tfdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);\n+\telse\n+\t\tfdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);\n+}\n+\n+static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)\n+{\n+\tint off;\n+\n+#ifdef CONFIG_FSL_PCIE_COMPAT\n+\toff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,\n+\t\t\t\t\t pcie->ccsr_res.start);\n+#else\n+#error \"No CONFIG_FSL_PCIE_COMPAT defined\"\n+#endif\n+\tif (off < 0) {\n+\t\tdebug(\"%s: ERROR: failed to find pcie compatiable\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\tif (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)\n+\t\tfdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);\n+\telse\n+\t\tfdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);\n+}\n+\n+static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)\n+{\n+\tft_pcie_rc_layerscape_gen4_fix(blob, pcie);\n+\tft_pcie_ep_layerscape_gen4_fix(blob, pcie);\n+}\n+\n+/* Fixup Kernel DT for PCIe */\n+void ft_pci_setup(void *blob, bd_t *bd)\n+{\n+\tstruct ls_pcie_g4 *pcie;\n+\n+\tlist_for_each_entry(pcie, &ls_pcie_g4_list, list)\n+\t\tft_pcie_layerscape_gen4_setup(blob, pcie);\n+\n+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)\n+\tfdt_fixup_pcie(blob);\n+#endif\n+}\n+\n+#else /* !CONFIG_OF_BOARD_SETUP */\n+void ft_pci_setup(void *blob, bd_t *bd)\n+{\n+}\n+#endif\n", "prefixes": [ "U-Boot", "PATCHv5", "6/8" ] }