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GET /api/patches/1080850/?format=api
{ "id": 1080850, "url": "http://patchwork.ozlabs.org/api/patches/1080850/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190408101708.23251-5-Zhiqiang.Hou@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190408101708.23251-5-Zhiqiang.Hou@nxp.com>", "list_archive_url": null, "date": "2019-04-08T10:15:46", "name": "[U-Boot,PATCHv5,4/8] pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs", "commit_ref": "07ce19f5e9ad637caa8cb2b6db45a6a28d2d69a1", "pull_url": null, "state": "accepted", "archived": false, "hash": "021cbf5864d5cd05b6a18a409ba12f01bedf7c9f", "submitter": { "id": 67929, "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api", "name": "Z.Q. Hou", "email": "zhiqiang.hou@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190408101708.23251-5-Zhiqiang.Hou@nxp.com/mbox/", "series": [ { "id": 101447, "url": "http://patchwork.ozlabs.org/api/series/101447/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=101447", "date": "2019-04-08T10:15:28", "name": "pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/101447/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1080850/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1080850/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"py4Ho4zu\";\n\tdkim-atps=neutral", "spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; " ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 44d5vf2XQGz9sPd\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 8 Apr 2019 20:17:34 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid D3A83C21E13; Mon, 8 Apr 2019 10:16:38 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id EA4EAC21D4A;\n\tMon, 8 Apr 2019 10:15:56 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 7C5DFC21E7F; Mon, 8 Apr 2019 10:15:52 +0000 (UTC)", "from EUR02-AM5-obe.outbound.protection.outlook.com\n\t(mail-eopbgr00068.outbound.protection.outlook.com [40.107.0.68])\n\tby lists.denx.de (Postfix) with ESMTPS id 24499C21E2F\n\tfor <u-boot@lists.denx.de>; Mon, 8 Apr 2019 10:15:48 +0000 (UTC)", "from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.3.19) by\n\tAM6PR04MB4533.eurprd04.prod.outlook.com (20.177.38.21) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1771.16; Mon, 8 Apr 2019 10:15:46 +0000", "from AM6PR04MB5781.eurprd04.prod.outlook.com\n\t([fe80::f9db:ed86:614e:460]) by\n\tAM6PR04MB5781.eurprd04.prod.outlook.com\n\t([fe80::f9db:ed86:614e:460%3]) with mapi id 15.20.1771.014;\n\tMon, 8 Apr 2019 10:15:46 +0000" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=SPF_HELO_PASS, T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=Ts6+nms8Y4wffOP3x3IhpLeCR2edmMYoWZDelB215Vk=;\n\tb=py4Ho4zuV6pGqomw25XU09d1HDiWAUXXeQOqiRnWPERLHe+EhkyzddpYwMy4hlaXZibw7DVsQ5anV0fruhk27sxqiuMX150f+VVz+AqoQQ+NcxFkdHwj39zq+JBaHWWXyJEd4Nrn5vWwT+wFA5uQjfd9gtA9N/qtf4RCvQ3Xz0U=", "From": "\"Z.q. Hou\" <zhiqiang.hou@nxp.com>", "To": "\"u-boot@lists.denx.de\" <u-boot@lists.denx.de>,\n\t\"albert.u.boot@aribaud.net\"\n\t<albert.u.boot@aribaud.net>, Priyanka Jain <priyanka.jain@nxp.com>,\n\tYork Sun <york.sun@nxp.com>,\n\t\"sriram.dash@nxp.com\" <sriram.dash@nxp.com>, \n\t\"yamada.masahiro@socionext.com\" <yamada.masahiro@socionext.com>,\n\tPrabhakar\n\tKushwaha <prabhakar.kushwaha@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com>,\n\t\"M.h. Lian\" <minghuan.lian@nxp.com>,\n\t\"bmeng.cn@gmail.com\" <bmeng.cn@gmail.com>", "Thread-Topic": "[PATCHv5 4/8] pci: Add PCIe Gen4 controller driver for NXP\n\tLayerscape SoCs", "Thread-Index": "AQHU7fQHctiRmK0kGUmcTC7BESyNgw==", "Date": "Mon, 8 Apr 2019 10:15:46 +0000", "Message-ID": "<20190408101708.23251-5-Zhiqiang.Hou@nxp.com>", "References": "<20190408101708.23251-1-Zhiqiang.Hou@nxp.com>", "In-Reply-To": "<20190408101708.23251-1-Zhiqiang.Hou@nxp.com>", "Accept-Language": "zh-CN, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "HK0PR03CA0107.apcprd03.prod.outlook.com\n\t(2603:1096:203:b0::23) To AM6PR04MB5781.eurprd04.prod.outlook.com\n\t(2603:10a6:20b:ad::19)", "authentication-results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"py4Ho4zu\";\n\tdkim-atps=neutral", "spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; " ], "x-ms-exchange-messagesentrepresentingtype": "1", "x-mailer": "git-send-email 2.17.1", "x-originating-ip": "[119.31.174.73]", "x-ms-publictraffictype": "Email", "x-ms-office365-filtering-correlation-id": "298a3ff0-a3ae-4506-92d7-08d6bc0b2a0f", "x-ms-office365-filtering-ht": "Tenant", "x-microsoft-antispam": "BCL:0; PCL:0;\n\tRULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);\n\tSRVR:AM6PR04MB4533; ", "x-ms-traffictypediagnostic": "AM6PR04MB4533:", "x-microsoft-antispam-prvs": "<AM6PR04MB453345EAA73528A3C28BA4F0842C0@AM6PR04MB4533.eurprd04.prod.outlook.com>", "x-forefront-prvs": "0001227049", "x-forefront-antispam-report": "SFV:NSPM;\n\tSFS:(10009020)(6029001)(136003)(39860400002)(396003)(366004)(346002)(376002)(189003)(199004)(186003)(54906003)(36756003)(11346002)(102836004)(30864003)(2501003)(316002)(76176011)(14444005)(6506007)(386003)(25786009)(26005)(52116002)(110136005)(66066001)(68736007)(476003)(8936002)(81166006)(50226002)(81156014)(4326008)(256004)(106356001)(1076003)(71200400001)(71190400001)(105586002)(86362001)(2616005)(2201001)(2906002)(7736002)(8676002)(99286004)(486006)(53936002)(53946003)(6512007)(6116002)(3846002)(6436002)(446003)(478600001)(6486002)(97736004)(305945005)(14454004)(5660300002)(921003)(1121003)(559001)(579004);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4533;\n\tH:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; MX:1; A:1; ", "received-spf": "None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)", "x-ms-exchange-senderadcheck": "1", "x-microsoft-antispam-message-info": "93asqHgWxlRwf3hdjJ44KRTPiv8+hJE4PQRd/LQ4VLUAxFd5RA+EcN0cdbAt9O1ctjJ4bz0/YiETm9LAuRhNC4tE2UUTnhVaBGq69Klff+9OhNn4iqookvk3nmq3gOP8aan8l42fCW0ReFLPR5iotsuRNG4f35Wh2WRyfTq2PtpHDyLzr0WzPIHmh3aC1aPUK1ew+5PB92MMk3hj0tn+F5jiWXSlYQguQszdS1hrY/pI3L9/eYBgDgSq2d1oIc+K4jIf58ih6F/upPsClPLagJhW9NzddIsK78A91MycfDOmFIo++Tx8R6l+c6MRUOgqcg9OW8kPX+OTO9oVBh1/T3Lm6lmgz0isoGM2A8qSk0WOgb1Gs8pC+lBVDhsVzmZnvuej/UKeeDoTcD9XCRb79iD7rZ4x2RizMHI9beESFHQ=", "Content-ID": "<A1F92DF787A40C48AA55602AAB323DD0@eurprd04.prod.outlook.com>", "MIME-Version": "1.0", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "298a3ff0-a3ae-4506-92d7-08d6bc0b2a0f", "X-MS-Exchange-CrossTenant-originalarrivaltime": "08 Apr 2019 10:15:46.0533\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM6PR04MB4533", "Cc": "\"Z.q. Hou\" <zhiqiang.hou@nxp.com>, Xiaowei Bao <xiaowei.bao@nxp.com>", "Subject": "[U-Boot] [PATCHv5 4/8] pci: Add PCIe Gen4 controller driver for NXP\n\tLayerscape SoCs", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nAdd PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe\ncontroller is based on the Mobiveil IP, which is compatible\nwith the PCI Express™ Base Specification, Revision 4.0.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\nSigned-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com>\nReviewed-by: Bin Meng <bmeng.cn@gmail.com>\n---\nV5:\n - Changed the config name to alphabetial order.\n - Updated the Copyright.\n\n drivers/pci/Kconfig | 8 +\n drivers/pci/Makefile | 1 +\n drivers/pci/pcie_layerscape_gen4.c | 577 +++++++++++++++++++++++++++++\n drivers/pci/pcie_layerscape_gen4.h | 264 +++++++++++++\n 4 files changed, 850 insertions(+)\n create mode 100644 drivers/pci/pcie_layerscape_gen4.c\n create mode 100644 drivers/pci/pcie_layerscape_gen4.h", "diff": "diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig\r\nindex 1521885bde..763bd500d4 100644\r\n--- a/drivers/pci/Kconfig\r\n+++ b/drivers/pci/Kconfig\r\n@@ -105,6 +105,14 @@ config PCIE_LAYERSCAPE\r\n \t PCIe controllers. The PCIe may works in RC or EP mode according to\r\n \t RCW[HOST_AGT_PEX] setting.\r\n \r\n+config PCIE_LAYERSCAPE_GEN4\r\n+\tbool \"Layerscape Gen4 PCIe support\"\r\n+\tdepends on DM_PCI\r\n+\thelp\r\n+\t Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or\r\n+\t several PCIe controllers. The PCIe controller can work in RC or\r\n+\t EP mode according to RCW[HOST_AGT_PEX] setting.\r\n+\r\n config PCIE_INTEL_FPGA\r\n \tbool \"Intel FPGA PCIe support\"\r\n \tdepends on DM_PCI\r\ndiff --git a/drivers/pci/Makefile b/drivers/pci/Makefile\r\nindex 4923641895..7f585aad55 100644\r\n--- a/drivers/pci/Makefile\r\n+++ b/drivers/pci/Makefile\r\n@@ -32,5 +32,6 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o\r\n obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o\r\n obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o\r\n obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o\r\n+obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o\r\n obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o\r\n obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o\r\ndiff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c\r\nnew file mode 100644\r\nindex 0000000000..da77caccfd\r\n--- /dev/null\r\n+++ b/drivers/pci/pcie_layerscape_gen4.c\r\n@@ -0,0 +1,577 @@\r\n+// SPDX-License-Identifier: GPL-2.0+ OR X11\r\n+/*\r\n+ * Copyright 2018-2019 NXP\r\n+ *\r\n+ * PCIe Gen4 driver for NXP Layerscape SoCs\r\n+ * Author: Hou Zhiqiang <Minder.Hou@gmail.com>\r\n+ */\r\n+\r\n+#include <common.h>\r\n+#include <asm/arch/fsl_serdes.h>\r\n+#include <pci.h>\r\n+#include <asm/io.h>\r\n+#include <errno.h>\r\n+#include <malloc.h>\r\n+#include <dm.h>\r\n+#include <linux/sizes.h>\r\n+\r\n+#include \"pcie_layerscape_gen4.h\"\r\n+\r\n+DECLARE_GLOBAL_DATA_PTR;\r\n+\r\n+LIST_HEAD(ls_pcie_g4_list);\r\n+\r\n+static u64 bar_size[4] = {\r\n+\tPCIE_BAR0_SIZE,\r\n+\tPCIE_BAR1_SIZE,\r\n+\tPCIE_BAR2_SIZE,\r\n+\tPCIE_BAR4_SIZE\r\n+};\r\n+\r\n+static int ls_pcie_g4_ltssm(struct ls_pcie_g4 *pcie)\r\n+{\r\n+\tu32 state;\r\n+\r\n+\tstate = pf_ctrl_readl(pcie, PCIE_LTSSM_STA) & LTSSM_STATE_MASK;\r\n+\r\n+\treturn state;\r\n+}\r\n+\r\n+static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie)\r\n+{\r\n+\tint ltssm;\r\n+\r\n+\tltssm = ls_pcie_g4_ltssm(pcie);\r\n+\tif (ltssm != LTSSM_PCIE_L0)\r\n+\t\treturn 0;\r\n+\r\n+\treturn 1;\r\n+}\r\n+\r\n+static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie)\r\n+{\r\n+\tccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY);\r\n+}\r\n+\r\n+static void ls_pcie_g4_cfg_set_target(struct ls_pcie_g4 *pcie, u32 target)\r\n+{\r\n+\tccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target);\r\n+\tccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0);\r\n+}\r\n+\r\n+static int ls_pcie_g4_outbound_win_set(struct ls_pcie_g4 *pcie, int idx,\r\n+\t\t\t\t int type, u64 phys, u64 bus_addr,\r\n+\t\t\t\t pci_size_t size)\r\n+{\r\n+\tu32 val;\r\n+\tu32 size_h, size_l;\r\n+\r\n+\tif (idx >= PAB_WINS_NUM)\r\n+\t\treturn -EINVAL;\r\n+\r\n+\tsize_h = upper_32_bits(~(size - 1));\r\n+\tsize_l = lower_32_bits(~(size - 1));\r\n+\r\n+\tval = ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));\r\n+\tval &= ~((AXI_AMAP_CTRL_TYPE_MASK << AXI_AMAP_CTRL_TYPE_SHIFT) |\r\n+\t\t(AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT) |\r\n+\t\tAXI_AMAP_CTRL_EN);\r\n+\tval |= ((type & AXI_AMAP_CTRL_TYPE_MASK) << AXI_AMAP_CTRL_TYPE_SHIFT) |\r\n+\t\t((size_l >> AXI_AMAP_CTRL_SIZE_SHIFT) <<\r\n+\t\tAXI_AMAP_CTRL_SIZE_SHIFT) | AXI_AMAP_CTRL_EN;\r\n+\r\n+\tccsr_writel(pcie, PAB_AXI_AMAP_CTRL(idx), val);\r\n+\r\n+\tccsr_writel(pcie, PAB_AXI_AMAP_AXI_WIN(idx), lower_32_bits(phys));\r\n+\tccsr_writel(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(idx), upper_32_bits(phys));\r\n+\tccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));\r\n+\tccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));\r\n+\tccsr_writel(pcie, PAB_EXT_AXI_AMAP_SIZE(idx), size_h);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int ls_pcie_g4_rc_inbound_win_set(struct ls_pcie_g4 *pcie, int idx,\r\n+\t\t\t\t\t int type, u64 phys, u64 bus_addr,\r\n+\t\t\t\t\t pci_size_t size)\r\n+{\r\n+\tu32 val;\r\n+\tpci_size_t win_size = ~(size - 1);\r\n+\r\n+\tval = ccsr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));\r\n+\r\n+\tval &= ~(PEX_AMAP_CTRL_TYPE_MASK << PEX_AMAP_CTRL_TYPE_SHIFT);\r\n+\tval &= ~(PEX_AMAP_CTRL_EN_MASK << PEX_AMAP_CTRL_EN_SHIFT);\r\n+\tval = (val | (type << PEX_AMAP_CTRL_TYPE_SHIFT));\r\n+\tval = (val | (1 << PEX_AMAP_CTRL_EN_SHIFT));\r\n+\r\n+\tccsr_writel(pcie, PAB_PEX_AMAP_CTRL(idx),\r\n+\t\t val | lower_32_bits(win_size));\r\n+\r\n+\tccsr_writel(pcie, PAB_EXT_PEX_AMAP_SIZE(idx), upper_32_bits(win_size));\r\n+\tccsr_writel(pcie, PAB_PEX_AMAP_AXI_WIN(idx), lower_32_bits(phys));\r\n+\tccsr_writel(pcie, PAB_EXT_PEX_AMAP_AXI_WIN(idx), upper_32_bits(phys));\r\n+\tccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));\r\n+\tccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static void ls_pcie_g4_dump_wins(struct ls_pcie_g4 *pcie, int wins)\r\n+{\r\n+\tint i;\r\n+\r\n+\tfor (i = 0; i < wins; i++) {\r\n+\t\tdebug(\"APIO Win%d:\\n\", i);\r\n+\t\tdebug(\"\\tLOWER PHYS:\t0x%08x\\n\",\r\n+\t\t ccsr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(i)));\r\n+\t\tdebug(\"\\tUPPER PHYS:\t0x%08x\\n\",\r\n+\t\t ccsr_readl(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(i)));\r\n+\t\tdebug(\"\\tLOWER BUS:\t0x%08x\\n\",\r\n+\t\t ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_L(i)));\r\n+\t\tdebug(\"\\tUPPER BUS:\t0x%08x\\n\",\r\n+\t\t ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(i)));\r\n+\t\tdebug(\"\\tSIZE:\t\t0x%08x\\n\",\r\n+\t\t ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)) &\r\n+\t\t (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT));\r\n+\t\tdebug(\"\\tEXT_SIZE:\t0x%08x\\n\",\r\n+\t\t ccsr_readl(pcie, PAB_EXT_AXI_AMAP_SIZE(i)));\r\n+\t\tdebug(\"\\tPARAM:\t\t0x%08x\\n\",\r\n+\t\t ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(i)));\r\n+\t\tdebug(\"\\tCTRL:\t\t0x%08x\\n\",\r\n+\t\t ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)));\r\n+\t}\r\n+}\r\n+\r\n+static void ls_pcie_g4_setup_wins(struct ls_pcie_g4 *pcie)\r\n+{\r\n+\tstruct pci_region *io, *mem, *pref;\r\n+\tint idx = 1;\r\n+\r\n+\t/* INBOUND WIN */\r\n+\tls_pcie_g4_rc_inbound_win_set(pcie, 0, IB_TYPE_MEM_F, 0, 0, SIZE_1T);\r\n+\r\n+\t/* OUTBOUND WIN 0: CFG */\r\n+\tls_pcie_g4_outbound_win_set(pcie, 0, PAB_AXI_TYPE_CFG,\r\n+\t\t\t\t pcie->cfg_res.start, 0,\r\n+\t\t\t\t fdt_resource_size(&pcie->cfg_res));\r\n+\r\n+\tpci_get_regions(pcie->bus, &io, &mem, &pref);\r\n+\r\n+\tif (io)\r\n+\t\t/* OUTBOUND WIN: IO */\r\n+\t\tls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_IO,\r\n+\t\t\t\t\t io->phys_start, io->bus_start,\r\n+\t\t\t\t\t io->size);\r\n+\r\n+\tif (mem)\r\n+\t\t/* OUTBOUND WIN: MEM */\r\n+\t\tls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,\r\n+\t\t\t\t\t mem->phys_start, mem->bus_start,\r\n+\t\t\t\t\t mem->size);\r\n+\r\n+\tif (pref)\r\n+\t\t/* OUTBOUND WIN: perf MEM */\r\n+\t\tls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,\r\n+\t\t\t\t\t pref->phys_start, pref->bus_start,\r\n+\t\t\t\t\t pref->size);\r\n+\r\n+\tls_pcie_g4_dump_wins(pcie, idx);\r\n+}\r\n+\r\n+/* Return 0 if the address is valid, -errno if not valid */\r\n+static int ls_pcie_g4_addr_valid(struct ls_pcie_g4 *pcie, pci_dev_t bdf)\r\n+{\r\n+\tstruct udevice *bus = pcie->bus;\r\n+\r\n+\tif (pcie->mode == PCI_HEADER_TYPE_NORMAL)\r\n+\t\treturn -ENODEV;\r\n+\r\n+\tif (!pcie->enabled)\r\n+\t\treturn -ENXIO;\r\n+\r\n+\tif (PCI_BUS(bdf) < bus->seq)\r\n+\t\treturn -EINVAL;\r\n+\r\n+\tif ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_g4_link_up(pcie)))\r\n+\t\treturn -EINVAL;\r\n+\r\n+\tif (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))\r\n+\t\treturn -EINVAL;\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+void *ls_pcie_g4_conf_address(struct ls_pcie_g4 *pcie, pci_dev_t bdf,\r\n+\t\t\t int offset)\r\n+{\r\n+\tstruct udevice *bus = pcie->bus;\r\n+\tu32 target;\r\n+\r\n+\tif (PCI_BUS(bdf) == bus->seq) {\r\n+\t\tif (offset < INDIRECT_ADDR_BNDRY) {\r\n+\t\t\tccsr_set_page(pcie, 0);\r\n+\t\t\treturn pcie->ccsr + offset;\r\n+\t\t}\r\n+\r\n+\t\tccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));\r\n+\t\treturn pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset);\r\n+\t}\r\n+\r\n+\ttarget = PAB_TARGET_BUS(PCI_BUS(bdf) - bus->seq) |\r\n+\t\t PAB_TARGET_DEV(PCI_DEV(bdf)) |\r\n+\t\t PAB_TARGET_FUNC(PCI_FUNC(bdf));\r\n+\r\n+\tls_pcie_g4_cfg_set_target(pcie, target);\r\n+\r\n+\treturn pcie->cfg + offset;\r\n+}\r\n+\r\n+static int ls_pcie_g4_read_config(struct udevice *bus, pci_dev_t bdf,\r\n+\t\t\t\t uint offset, ulong *valuep,\r\n+\t\t\t\t enum pci_size_t size)\r\n+{\r\n+\tstruct ls_pcie_g4 *pcie = dev_get_priv(bus);\r\n+\tvoid *address;\r\n+\tint ret = 0;\r\n+\r\n+\tif (ls_pcie_g4_addr_valid(pcie, bdf)) {\r\n+\t\t*valuep = pci_get_ff(size);\r\n+\t\treturn 0;\r\n+\t}\r\n+\r\n+\taddress = ls_pcie_g4_conf_address(pcie, bdf, offset);\r\n+\r\n+\tswitch (size) {\r\n+\tcase PCI_SIZE_8:\r\n+\t\t*valuep = readb(address);\r\n+\t\tbreak;\r\n+\tcase PCI_SIZE_16:\r\n+\t\t*valuep = readw(address);\r\n+\t\tbreak;\r\n+\tcase PCI_SIZE_32:\r\n+\t\t*valuep = readl(address);\r\n+\t\tbreak;\r\n+\tdefault:\r\n+\t\tret = -EINVAL;\r\n+\t\tbreak;\r\n+\t}\r\n+\r\n+\treturn ret;\r\n+}\r\n+\r\n+static int ls_pcie_g4_write_config(struct udevice *bus, pci_dev_t bdf,\r\n+\t\t\t\t uint offset, ulong value,\r\n+\t\t\t\t enum pci_size_t size)\r\n+{\r\n+\tstruct ls_pcie_g4 *pcie = dev_get_priv(bus);\r\n+\tvoid *address;\r\n+\r\n+\tif (ls_pcie_g4_addr_valid(pcie, bdf))\r\n+\t\treturn 0;\r\n+\r\n+\taddress = ls_pcie_g4_conf_address(pcie, bdf, offset);\r\n+\r\n+\tswitch (size) {\r\n+\tcase PCI_SIZE_8:\r\n+\t\twriteb(value, address);\r\n+\t\treturn 0;\r\n+\tcase PCI_SIZE_16:\r\n+\t\twritew(value, address);\r\n+\t\treturn 0;\r\n+\tcase PCI_SIZE_32:\r\n+\t\twritel(value, address);\r\n+\t\treturn 0;\r\n+\tdefault:\r\n+\t\treturn -EINVAL;\r\n+\t}\r\n+}\r\n+\r\n+static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie)\r\n+{\r\n+\tu32 val;\r\n+\r\n+\t/* Fix class code */\r\n+\tval = ccsr_readl(pcie, GPEX_CLASSCODE);\r\n+\tval &= ~(GPEX_CLASSCODE_MASK << GPEX_CLASSCODE_SHIFT);\r\n+\tval |= PCI_CLASS_BRIDGE_PCI << GPEX_CLASSCODE_SHIFT;\r\n+\tccsr_writel(pcie, GPEX_CLASSCODE, val);\r\n+\r\n+\t/* Enable APIO and Memory/IO/CFG Wins */\r\n+\tval = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));\r\n+\tval |= APIO_EN | MEM_WIN_EN | IO_WIN_EN | CFG_WIN_EN;\r\n+\tccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);\r\n+\r\n+\tls_pcie_g4_setup_wins(pcie);\r\n+\r\n+\tpcie->stream_id_cur = 0;\r\n+}\r\n+\r\n+static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf,\r\n+\t\t\t\t\t int bar, u64 phys)\r\n+{\r\n+\tu32 val;\r\n+\r\n+\t/* PF BAR1 is for MSI-X and only need to enable */\r\n+\tif (bar == 1) {\r\n+\t\tccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), BAR_AMAP_EN);\r\n+\t\treturn;\r\n+\t}\r\n+\r\n+\tval = upper_32_bits(phys);\r\n+\tccsr_writel(pcie, PAB_EXT_PEX_BAR_AMAP(pf, bar), val);\r\n+\tval = lower_32_bits(phys) | BAR_AMAP_EN;\r\n+\tccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), val);\r\n+}\r\n+\r\n+static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)\r\n+{\r\n+\tu64 phys;\r\n+\tint bar;\r\n+\tu32 val;\r\n+\r\n+\tif ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1)\r\n+\t\treturn;\r\n+\r\n+\tphys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;\r\n+\tfor (bar = 0; bar < PF_BAR_NUM; bar++) {\r\n+\t\tls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys);\r\n+\t\tphys += PCIE_BAR_SIZE;\r\n+\t}\r\n+\r\n+\t/* OUTBOUND: map MEM */\r\n+\tls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM,\r\n+\t\t\t\t pcie->cfg_res.start +\r\n+\t\t\t\t CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0,\r\n+\t\t\t\t CONFIG_SYS_PCI_MEMORY_SIZE);\r\n+\r\n+\tval = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf));\r\n+\tval &= ~FUNC_NUM_PCIE_MASK;\r\n+\tval |= pf;\r\n+\tccsr_writel(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf), val);\r\n+}\r\n+\r\n+static void ls_pcie_g4_ep_enable_bar(struct ls_pcie_g4 *pcie, int pf,\r\n+\t\t\t\t int bar, bool vf_bar, bool enable)\r\n+{\r\n+\tu32 val;\r\n+\tu32 bar_pos = BAR_POS(bar, pf, vf_bar);\r\n+\r\n+\tval = ccsr_readl(pcie, GPEX_BAR_ENABLE);\r\n+\tif (enable)\r\n+\t\tval |= 1 << bar_pos;\r\n+\telse\r\n+\t\tval &= ~(1 << bar_pos);\r\n+\tccsr_writel(pcie, GPEX_BAR_ENABLE, val);\r\n+}\r\n+\r\n+static void ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4 *pcie, int pf,\r\n+\t\t\t\t int bar, bool vf_bar, u64 size)\r\n+{\r\n+\tu32 bar_pos = BAR_POS(bar, pf, vf_bar);\r\n+\tu32 mask_l = lower_32_bits(~(size - 1));\r\n+\tu32 mask_h = upper_32_bits(~(size - 1));\r\n+\r\n+\tccsr_writel(pcie, GPEX_BAR_SELECT, bar_pos);\r\n+\tccsr_writel(pcie, GPEX_BAR_SIZE_LDW, mask_l);\r\n+\tccsr_writel(pcie, GPEX_BAR_SIZE_UDW, mask_h);\r\n+}\r\n+\r\n+static void ls_pcie_g4_ep_setup_bar(struct ls_pcie_g4 *pcie, int pf,\r\n+\t\t\t\t int bar, bool vf_bar, u64 size)\r\n+{\r\n+\tbool en = size ? true : false;\r\n+\r\n+\tls_pcie_g4_ep_enable_bar(pcie, pf, bar, vf_bar, en);\r\n+\tls_pcie_g4_ep_set_bar_size(pcie, pf, bar, vf_bar, size);\r\n+}\r\n+\r\n+static void ls_pcie_g4_ep_setup_bars(struct ls_pcie_g4 *pcie, int pf)\r\n+{\r\n+\tint bar;\r\n+\r\n+\t/* Setup PF BARs */\r\n+\tfor (bar = 0; bar < PF_BAR_NUM; bar++)\r\n+\t\tls_pcie_g4_ep_setup_bar(pcie, pf, bar, false, bar_size[bar]);\r\n+\r\n+\tif (!pcie->sriov_support)\r\n+\t\treturn;\r\n+\r\n+\t/* Setup VF BARs */\r\n+\tfor (bar = 0; bar < VF_BAR_NUM; bar++)\r\n+\t\tls_pcie_g4_ep_setup_bar(pcie, pf, bar, true, bar_size[bar]);\r\n+}\r\n+\r\n+static void ls_pcie_g4_set_sriov(struct ls_pcie_g4 *pcie, int pf)\r\n+{\r\n+\tunsigned int val;\r\n+\r\n+\tval = ccsr_readl(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf));\r\n+\tval &= ~(TTL_VF_MASK << TTL_VF_SHIFT);\r\n+\tval |= PCIE_VF_NUM << TTL_VF_SHIFT;\r\n+\tval &= ~(INI_VF_MASK << INI_VF_SHIFT);\r\n+\tval |= PCIE_VF_NUM << INI_VF_SHIFT;\r\n+\tccsr_writel(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf), val);\r\n+\r\n+\tval = ccsr_readl(pcie, PCIE_SRIOV_VF_OFFSET_STRIDE);\r\n+\tval += PCIE_VF_NUM * pf - pf;\r\n+\tccsr_writel(pcie, GPEX_SRIOV_VF_OFFSET_STRIDE(pf), val);\r\n+}\r\n+\r\n+static void ls_pcie_g4_setup_ep(struct ls_pcie_g4 *pcie)\r\n+{\r\n+\tu32 pf, sriov;\r\n+\tu32 val;\r\n+\tint i;\r\n+\r\n+\t/* Enable APIO and Memory Win */\r\n+\tval = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));\r\n+\tval |= APIO_EN | MEM_WIN_EN;\r\n+\tccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);\r\n+\r\n+\tsriov = ccsr_readl(pcie, PCIE_SRIOV_CAPABILITY);\r\n+\tif (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)\r\n+\t\tpcie->sriov_support = 1;\r\n+\r\n+\tpf = pcie->sriov_support ? PCIE_PF_NUM : 1;\r\n+\r\n+\tfor (i = 0; i < pf; i++) {\r\n+\t\tls_pcie_g4_ep_setup_bars(pcie, i);\r\n+\t\tls_pcie_g4_ep_setup_wins(pcie, i);\r\n+\t\tif (pcie->sriov_support)\r\n+\t\t\tls_pcie_g4_set_sriov(pcie, i);\r\n+\t}\r\n+\r\n+\tls_pcie_g4_ep_enable_cfg(pcie);\r\n+\tls_pcie_g4_dump_wins(pcie, pf);\r\n+}\r\n+\r\n+static int ls_pcie_g4_probe(struct udevice *dev)\r\n+{\r\n+\tstruct ls_pcie_g4 *pcie = dev_get_priv(dev);\r\n+\tconst void *fdt = gd->fdt_blob;\r\n+\tint node = dev_of_offset(dev);\r\n+\tu32 link_ctrl_sta;\r\n+\tu32 val;\r\n+\tint ret;\r\n+\r\n+\tpcie->bus = dev;\r\n+\r\n+\tret = fdt_get_named_resource(fdt, node, \"reg\", \"reg-names\",\r\n+\t\t\t\t \"ccsr\", &pcie->ccsr_res);\r\n+\tif (ret) {\r\n+\t\tprintf(\"ls-pcie-g4: resource \\\"ccsr\\\" not found\\n\");\r\n+\t\treturn ret;\r\n+\t}\r\n+\r\n+\tpcie->idx = (pcie->ccsr_res.start - PCIE_SYS_BASE_ADDR) /\r\n+\t\t PCIE_CCSR_SIZE;\r\n+\r\n+\tlist_add(&pcie->list, &ls_pcie_g4_list);\r\n+\r\n+\tpcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));\r\n+\tif (!pcie->enabled) {\r\n+\t\tprintf(\"PCIe%d: %s disabled\\n\", pcie->idx, dev->name);\r\n+\t\treturn 0;\r\n+\t}\r\n+\r\n+\tpcie->ccsr = map_physmem(pcie->ccsr_res.start,\r\n+\t\t\t\t fdt_resource_size(&pcie->ccsr_res),\r\n+\t\t\t\t MAP_NOCACHE);\r\n+\r\n+\tret = fdt_get_named_resource(fdt, node, \"reg\", \"reg-names\",\r\n+\t\t\t\t \"config\", &pcie->cfg_res);\r\n+\tif (ret) {\r\n+\t\tprintf(\"%s: resource \\\"config\\\" not found\\n\", dev->name);\r\n+\t\treturn ret;\r\n+\t}\r\n+\r\n+\tpcie->cfg = map_physmem(pcie->cfg_res.start,\r\n+\t\t\t\tfdt_resource_size(&pcie->cfg_res),\r\n+\t\t\t\tMAP_NOCACHE);\r\n+\r\n+\tret = fdt_get_named_resource(fdt, node, \"reg\", \"reg-names\",\r\n+\t\t\t\t \"lut\", &pcie->lut_res);\r\n+\tif (ret) {\r\n+\t\tprintf(\"ls-pcie-g4: resource \\\"lut\\\" not found\\n\");\r\n+\t\treturn ret;\r\n+\t}\r\n+\r\n+\tpcie->lut = map_physmem(pcie->lut_res.start,\r\n+\t\t\t\tfdt_resource_size(&pcie->lut_res),\r\n+\t\t\t\tMAP_NOCACHE);\r\n+\r\n+\tret = fdt_get_named_resource(fdt, node, \"reg\", \"reg-names\",\r\n+\t\t\t\t \"pf_ctrl\", &pcie->pf_ctrl_res);\r\n+\tif (ret) {\r\n+\t\tprintf(\"ls-pcie-g4: resource \\\"pf_ctrl\\\" not found\\n\");\r\n+\t\treturn ret;\r\n+\t}\r\n+\r\n+\tpcie->pf_ctrl = map_physmem(pcie->pf_ctrl_res.start,\r\n+\t\t\t\t fdt_resource_size(&pcie->pf_ctrl_res),\r\n+\t\t\t\t MAP_NOCACHE);\r\n+\r\n+\tpcie->big_endian = fdtdec_get_bool(fdt, node, \"big-endian\");\r\n+\r\n+\tdebug(\"%s ccsr:%lx, cfg:0x%lx, big-endian:%d\\n\",\r\n+\t dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg,\r\n+\t pcie->big_endian);\r\n+\r\n+\tpcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;\r\n+\r\n+\tif (pcie->mode == PCI_HEADER_TYPE_NORMAL) {\r\n+\t\tprintf(\"PCIe%u: %s %s\", pcie->idx, dev->name, \"Endpoint\");\r\n+\t\tls_pcie_g4_setup_ep(pcie);\r\n+\t} else {\r\n+\t\tprintf(\"PCIe%u: %s %s\", pcie->idx, dev->name, \"Root Complex\");\r\n+\t\tls_pcie_g4_setup_ctrl(pcie);\r\n+\t}\r\n+\r\n+\t/* Enable Amba & PEX PIO */\r\n+\tval = ccsr_readl(pcie, PAB_CTRL);\r\n+\tval |= PAB_CTRL_APIO_EN | PAB_CTRL_PPIO_EN;\r\n+\tccsr_writel(pcie, PAB_CTRL, val);\r\n+\r\n+\tval = ccsr_readl(pcie, PAB_PEX_PIO_CTRL(0));\r\n+\tval |= PPIO_EN;\r\n+\tccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val);\r\n+\r\n+\tif (!ls_pcie_g4_link_up(pcie)) {\r\n+\t\t/* Let the user know there's no PCIe link */\r\n+\t\tprintf(\": no link\\n\");\r\n+\t\treturn 0;\r\n+\t}\r\n+\r\n+\t/* Print the negotiated PCIe link width */\r\n+\tlink_ctrl_sta = ccsr_readl(pcie, PCIE_LINK_CTRL_STA);\r\n+\tprintf(\": x%d gen%d\\n\",\r\n+\t (link_ctrl_sta >> PCIE_LINK_WIDTH_SHIFT & PCIE_LINK_WIDTH_MASK),\r\n+\t (link_ctrl_sta >> PCIE_LINK_SPEED_SHIFT) & PCIE_LINK_SPEED_MASK);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static const struct dm_pci_ops ls_pcie_g4_ops = {\r\n+\t.read_config\t= ls_pcie_g4_read_config,\r\n+\t.write_config\t= ls_pcie_g4_write_config,\r\n+};\r\n+\r\n+static const struct udevice_id ls_pcie_g4_ids[] = {\r\n+\t{ .compatible = \"fsl,lx2160a-pcie\" },\r\n+\t{ }\r\n+};\r\n+\r\n+U_BOOT_DRIVER(pcie_layerscape_gen4) = {\r\n+\t.name = \"pcie_layerscape_gen4\",\r\n+\t.id = UCLASS_PCI,\r\n+\t.of_match = ls_pcie_g4_ids,\r\n+\t.ops = &ls_pcie_g4_ops,\r\n+\t.probe\t= ls_pcie_g4_probe,\r\n+\t.priv_auto_alloc_size = sizeof(struct ls_pcie_g4),\r\n+};\r\n+\r\n+/* No any fixup so far */\r\n+void ft_pci_setup(void *blob, bd_t *bd)\r\n+{\r\n+}\r\ndiff --git a/drivers/pci/pcie_layerscape_gen4.h b/drivers/pci/pcie_layerscape_gen4.h\r\nnew file mode 100644\r\nindex 0000000000..27c2d09332\r\n--- /dev/null\r\n+++ b/drivers/pci/pcie_layerscape_gen4.h\r\n@@ -0,0 +1,264 @@\r\n+/* SPDX-License-Identifier: GPL-2.0+ */\r\n+/*\r\n+ * Copyright 2018-2019 NXP\r\n+ *\r\n+ * PCIe Gen4 driver for NXP Layerscape SoCs\r\n+ * Author: Hou Zhiqiang <Minder.Hou@gmail.com>\r\n+ */\r\n+\r\n+#ifndef _PCIE_LAYERSCAPE_GEN4_H_\r\n+#define _PCIE_LAYERSCAPE_GEN4_H_\r\n+#include <pci.h>\r\n+#include <dm.h>\r\n+\r\n+#ifndef CONFIG_SYS_PCI_MEMORY_SIZE\r\n+#define CONFIG_SYS_PCI_MEMORY_SIZE\t\t(4 * 1024 * 1024 * 1024ULL)\r\n+#endif\r\n+\r\n+#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE\r\n+#define CONFIG_SYS_PCI_EP_MEMORY_BASE\t\tCONFIG_SYS_LOAD_ADDR\r\n+#endif\r\n+\r\n+#define PCIE_PF_NUM\t\t\t\t2\r\n+#define PCIE_VF_NUM\t\t\t\t32\r\n+\r\n+#define LS_G4_PF0\t\t\t\t0\r\n+#define LS_G4_PF1\t\t\t\t1\r\n+#define PF_BAR_NUM\t\t\t\t4\r\n+#define VF_BAR_NUM\t\t\t\t4\r\n+#define PCIE_BAR_SIZE\t\t\t\t(8 * 1024)\t\t/* 8K */\r\n+#define PCIE_BAR0_SIZE\t\t\t\tPCIE_BAR_SIZE\r\n+#define PCIE_BAR1_SIZE\t\t\t\tPCIE_BAR_SIZE\r\n+#define PCIE_BAR2_SIZE\t\t\t\tPCIE_BAR_SIZE\r\n+#define PCIE_BAR4_SIZE\t\t\t\tPCIE_BAR_SIZE\r\n+#define SIZE_1T\t\t\t\t\t(1024 * 1024 * 1024 * 1024ULL)\r\n+\r\n+/* GPEX CSR */\r\n+#define GPEX_CLASSCODE\t\t\t\t0x474\r\n+#define GPEX_CLASSCODE_SHIFT\t\t\t16\r\n+#define GPEX_CLASSCODE_MASK\t\t\t0xffff\r\n+\r\n+#define GPEX_CFG_READY\t\t\t\t0x4b0\r\n+#define PCIE_CONFIG_READY\t\t\tBIT(0)\r\n+\r\n+#define GPEX_BAR_ENABLE\t\t\t\t0x4d4\r\n+#define GPEX_BAR_SIZE_LDW\t\t\t0x4d8\r\n+#define GPEX_BAR_SIZE_UDW\t\t\t0x4dC\r\n+#define GPEX_BAR_SELECT\t\t\t\t0x4e0\r\n+\r\n+#define BAR_POS(bar, pf, vf_bar)\t\t\\\r\n+\t((bar) + (pf) * PF_BAR_NUM + (vf_bar) * PCIE_PF_NUM * PF_BAR_NUM)\r\n+\r\n+#define GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf)\t(0x644 + (pf) * 4)\r\n+#define TTL_VF_MASK\t\t\t\t0xffff\r\n+#define TTL_VF_SHIFT\t\t\t\t16\r\n+#define INI_VF_MASK\t\t\t\t0xffff\r\n+#define INI_VF_SHIFT\t\t\t\t0\r\n+#define GPEX_SRIOV_VF_OFFSET_STRIDE(pf)\t\t(0x704 + (pf) * 4)\r\n+\r\n+/* PAB CSR */\r\n+#define PAB_CTRL\t\t\t\t0x808\r\n+#define PAB_CTRL_APIO_EN\t\t\tBIT(0)\r\n+#define PAB_CTRL_PPIO_EN\t\t\tBIT(1)\r\n+#define PAB_CTRL_MAX_BRST_LEN_SHIFT\t\t4\r\n+#define PAB_CTRL_MAX_BRST_LEN_MASK\t\t0x3\r\n+#define PAB_CTRL_PAGE_SEL_SHIFT\t\t\t13\r\n+#define PAB_CTRL_PAGE_SEL_MASK\t\t\t0x3f\r\n+#define PAB_CTRL_FUNC_SEL_SHIFT\t\t\t19\r\n+#define PAB_CTRL_FUNC_SEL_MASK\t\t\t0x1ff\r\n+\r\n+#define PAB_RST_CTRL\t\t\t\t0x820\r\n+#define PAB_BR_STAT\t\t\t\t0x80c\r\n+\r\n+/* AXI PIO Engines */\r\n+#define PAB_AXI_PIO_CTRL(idx)\t\t\t(0x840 + 0x10 * (idx))\r\n+#define APIO_EN\t\t\t\t\tBIT(0)\r\n+#define MEM_WIN_EN\t\t\t\tBIT(1)\r\n+#define IO_WIN_EN\t\t\t\tBIT(2)\r\n+#define CFG_WIN_EN\t\t\t\tBIT(3)\r\n+#define PAB_AXI_PIO_STAT(idx)\t\t\t(0x844 + 0x10 * (idx))\r\n+#define PAB_AXI_PIO_SL_CMD_STAT(idx)\t\t(0x848 + 0x10 * (idx))\r\n+#define PAB_AXI_PIO_SL_ADDR_STAT(idx)\t\t(0x84c + 0x10 * (idx))\r\n+#define PAB_AXI_PIO_SL_EXT_ADDR_STAT(idx)\t(0xb8a0 + 0x4 * (idx))\r\n+\r\n+/* PEX PIO Engines */\r\n+#define PAB_PEX_PIO_CTRL(idx)\t\t\t(0x8c0 + 0x10 * (idx))\r\n+#define PPIO_EN\t\t\t\t\tBIT(0)\r\n+#define PAB_PEX_PIO_STAT(idx)\t\t\t(0x8c4 + 0x10 * (idx))\r\n+#define PAB_PEX_PIO_MT_STAT(idx)\t\t(0x8c8 + 0x10 * (idx))\r\n+\r\n+#define INDIRECT_ADDR_BNDRY\t\t\t0xc00\r\n+#define PAGE_IDX_SHIFT\t\t\t\t10\r\n+#define PAGE_ADDR_MASK\t\t\t\t0x3ff\r\n+\r\n+#define OFFSET_TO_PAGE_IDX(off)\t\t\t\\\r\n+\t(((off) >> PAGE_IDX_SHIFT) & PAB_CTRL_PAGE_SEL_MASK)\r\n+\r\n+#define OFFSET_TO_PAGE_ADDR(off)\t\t\\\r\n+\t(((off) & PAGE_ADDR_MASK) | INDIRECT_ADDR_BNDRY)\r\n+\r\n+/* APIO WINs */\r\n+#define PAB_AXI_AMAP_CTRL(idx)\t\t\t(0xba0 + 0x10 * (idx))\r\n+#define PAB_EXT_AXI_AMAP_SIZE(idx)\t\t(0xbaf0 + 0x4 * (idx))\r\n+#define PAB_AXI_AMAP_AXI_WIN(idx)\t\t(0xba4 + 0x10 * (idx))\r\n+#define PAB_EXT_AXI_AMAP_AXI_WIN(idx)\t\t(0x80a0 + 0x4 * (idx))\r\n+#define PAB_AXI_AMAP_PEX_WIN_L(idx)\t\t(0xba8 + 0x10 * (idx))\r\n+#define PAB_AXI_AMAP_PEX_WIN_H(idx)\t\t(0xbac + 0x10 * (idx))\r\n+#define PAB_AXI_AMAP_PCI_HDR_PARAM(idx)\t\t(0x5ba0 + 0x4 * (idx))\r\n+#define FUNC_NUM_PCIE_MASK\t\t\tGENMASK(7, 0)\r\n+\r\n+#define AXI_AMAP_CTRL_EN\t\t\tBIT(0)\r\n+#define AXI_AMAP_CTRL_TYPE_SHIFT\t\t1\r\n+#define AXI_AMAP_CTRL_TYPE_MASK\t\t\t0x3\r\n+#define AXI_AMAP_CTRL_SIZE_SHIFT\t\t10\r\n+#define AXI_AMAP_CTRL_SIZE_MASK\t\t\t0x3fffff\r\n+\r\n+#define PAB_TARGET_BUS(x)\t\t\t(((x) & 0xff) << 24)\r\n+#define PAB_TARGET_DEV(x)\t\t\t(((x) & 0x1f) << 19)\r\n+#define PAB_TARGET_FUNC(x)\t\t\t(((x) & 0x7) << 16)\r\n+\r\n+#define PAB_AXI_TYPE_CFG\t\t\t0x00\r\n+#define PAB_AXI_TYPE_IO\t\t\t\t0x01\r\n+#define PAB_AXI_TYPE_MEM\t\t\t0x02\r\n+#define PAB_AXI_TYPE_ATOM\t\t\t0x03\r\n+\r\n+#define PAB_WINS_NUM\t\t\t\t256\r\n+\r\n+/* PPIO WINs RC mode */\r\n+#define PAB_PEX_AMAP_CTRL(idx)\t\t\t(0x4ba0 + 0x10 * (idx))\r\n+#define PAB_EXT_PEX_AMAP_SIZE(idx)\t\t(0xbef0 + 0x04 * (idx))\r\n+#define PAB_PEX_AMAP_AXI_WIN(idx)\t\t(0x4ba4 + 0x10 * (idx))\r\n+#define PAB_EXT_PEX_AMAP_AXI_WIN(idx)\t\t(0xb4a0 + 0x04 * (idx))\r\n+#define PAB_PEX_AMAP_PEX_WIN_L(idx)\t\t(0x4ba8 + 0x10 * (idx))\r\n+#define PAB_PEX_AMAP_PEX_WIN_H(idx)\t\t(0x4bac + 0x10 * (idx))\r\n+\r\n+#define IB_TYPE_MEM_F\t\t\t\t0x2\r\n+#define IB_TYPE_MEM_NF\t\t\t\t0x3\r\n+\r\n+#define PEX_AMAP_CTRL_TYPE_SHIFT\t\t0x1\r\n+#define PEX_AMAP_CTRL_EN_SHIFT\t\t\t0x0\r\n+#define PEX_AMAP_CTRL_TYPE_MASK\t\t\t0x3\r\n+#define PEX_AMAP_CTRL_EN_MASK\t\t\t0x1\r\n+\r\n+/* PPIO WINs EP mode */\r\n+#define PAB_PEX_BAR_AMAP(pf, bar)\t\t\\\r\n+\t(0x1ba0 + 0x20 * (pf) + 4 * (bar))\r\n+#define BAR_AMAP_EN\t\t\t\tBIT(0)\r\n+#define PAB_EXT_PEX_BAR_AMAP(pf, bar)\t\t\\\r\n+\t(0x84a0 + 0x20 * (pf) + 4 * (bar))\r\n+\r\n+/* CCSR registers */\r\n+#define PCIE_LINK_CTRL_STA\t\t\t0x5c\r\n+#define PCIE_LINK_SPEED_SHIFT\t\t\t16\r\n+#define PCIE_LINK_SPEED_MASK\t\t\t0x0f\r\n+#define PCIE_LINK_WIDTH_SHIFT\t\t\t20\r\n+#define PCIE_LINK_WIDTH_MASK\t\t\t0x3f\r\n+#define PCIE_SRIOV_CAPABILITY\t\t\t0x2a0\r\n+#define PCIE_SRIOV_VF_OFFSET_STRIDE\t\t0x2b4\r\n+\r\n+/* LUT registers */\r\n+#define PCIE_LUT_UDR(n)\t\t\t\t(0x800 + (n) * 8)\r\n+#define PCIE_LUT_LDR(n)\t\t\t\t(0x804 + (n) * 8)\r\n+#define PCIE_LUT_ENABLE\t\t\t\tBIT(31)\r\n+#define PCIE_LUT_ENTRY_COUNT\t\t\t32\r\n+\r\n+/* PF control registers */\r\n+#define PCIE_LTSSM_STA\t\t\t\t0x7fc\r\n+#define LTSSM_STATE_MASK\t\t\t0x7f\r\n+#define LTSSM_PCIE_L0\t\t\t\t0x2d /* L0 state */\r\n+\r\n+#define PCIE_SRDS_PRTCL(idx)\t\t\t(PCIE1 + (idx))\r\n+#define PCIE_SYS_BASE_ADDR\t\t\t0x3400000\r\n+#define PCIE_CCSR_SIZE\t\t\t\t0x0100000\r\n+\r\n+struct ls_pcie_g4 {\r\n+\tint idx;\r\n+\tstruct list_head list;\r\n+\tstruct udevice *bus;\r\n+\tstruct fdt_resource ccsr_res;\r\n+\tstruct fdt_resource cfg_res;\r\n+\tstruct fdt_resource lut_res;\r\n+\tstruct fdt_resource pf_ctrl_res;\r\n+\tvoid __iomem *ccsr;\r\n+\tvoid __iomem *cfg;\r\n+\tvoid __iomem *lut;\r\n+\tvoid __iomem *pf_ctrl;\r\n+\tbool big_endian;\r\n+\tbool enabled;\r\n+\tint next_lut_index;\r\n+\tstruct pci_controller hose;\r\n+\tint stream_id_cur;\r\n+\tint mode;\r\n+\tint sriov_support;\r\n+};\r\n+\r\n+extern struct list_head ls_pcie_g4_list;\r\n+\r\n+static inline void lut_writel(struct ls_pcie_g4 *pcie, unsigned int value,\r\n+\t\t\t unsigned int offset)\r\n+{\r\n+\tif (pcie->big_endian)\r\n+\t\tout_be32(pcie->lut + offset, value);\r\n+\telse\r\n+\t\tout_le32(pcie->lut + offset, value);\r\n+}\r\n+\r\n+static inline u32 lut_readl(struct ls_pcie_g4 *pcie, unsigned int offset)\r\n+{\r\n+\tif (pcie->big_endian)\r\n+\t\treturn in_be32(pcie->lut + offset);\r\n+\telse\r\n+\t\treturn in_le32(pcie->lut + offset);\r\n+}\r\n+\r\n+static inline void ccsr_set_page(struct ls_pcie_g4 *pcie, u8 pg_idx)\r\n+{\r\n+\tu32 val;\r\n+\r\n+\tval = in_le32(pcie->ccsr + PAB_CTRL);\r\n+\tval &= ~(PAB_CTRL_PAGE_SEL_MASK << PAB_CTRL_PAGE_SEL_SHIFT);\r\n+\tval |= (pg_idx & PAB_CTRL_PAGE_SEL_MASK) << PAB_CTRL_PAGE_SEL_SHIFT;\r\n+\r\n+\tout_le32(pcie->ccsr + PAB_CTRL, val);\r\n+}\r\n+\r\n+static inline unsigned int ccsr_readl(struct ls_pcie_g4 *pcie, u32 offset)\r\n+{\r\n+\tif (offset < INDIRECT_ADDR_BNDRY) {\r\n+\t\tccsr_set_page(pcie, 0);\r\n+\t\treturn in_le32(pcie->ccsr + offset);\r\n+\t}\r\n+\r\n+\tccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));\r\n+\treturn in_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset));\r\n+}\r\n+\r\n+static inline void ccsr_writel(struct ls_pcie_g4 *pcie, u32 offset, u32 value)\r\n+{\r\n+\tif (offset < INDIRECT_ADDR_BNDRY) {\r\n+\t\tccsr_set_page(pcie, 0);\r\n+\t\tout_le32(pcie->ccsr + offset, value);\r\n+\t} else {\r\n+\t\tccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));\r\n+\t\tout_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset), value);\r\n+\t}\r\n+}\r\n+\r\n+static inline unsigned int pf_ctrl_readl(struct ls_pcie_g4 *pcie, u32 offset)\r\n+{\r\n+\tif (pcie->big_endian)\r\n+\t\treturn in_be32(pcie->pf_ctrl + offset);\r\n+\telse\r\n+\t\treturn in_le32(pcie->pf_ctrl + offset);\r\n+}\r\n+\r\n+static inline void pf_ctrl_writel(struct ls_pcie_g4 *pcie, u32 offset,\r\n+\t\t\t\t u32 value)\r\n+{\r\n+\tif (pcie->big_endian)\r\n+\t\tout_be32(pcie->pf_ctrl + offset, value);\r\n+\telse\r\n+\t\tout_le32(pcie->pf_ctrl + offset, value);\r\n+}\r\n+\r\n+#endif /* _PCIE_LAYERSCAPE_GEN4_H_ */\r\n", "prefixes": [ "U-Boot", "PATCHv5", "4/8" ] }