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GET /api/patches/1080848/?format=api
{ "id": 1080848, "url": "http://patchwork.ozlabs.org/api/patches/1080848/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190408101708.23251-4-Zhiqiang.Hou@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190408101708.23251-4-Zhiqiang.Hou@nxp.com>", "list_archive_url": null, "date": "2019-04-08T10:15:41", "name": "[U-Boot,PATCHv5,3/8] armv8: lx2160a: add MMU table entries for PCIe", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "29cf5c9a3463c85b6ed24dd3e0a1886c7b677cc8", "submitter": { "id": 67929, "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api", "name": "Z.Q. Hou", "email": "zhiqiang.hou@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190408101708.23251-4-Zhiqiang.Hou@nxp.com/mbox/", "series": [ { "id": 101447, "url": "http://patchwork.ozlabs.org/api/series/101447/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=101447", "date": "2019-04-08T10:15:28", "name": "pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/101447/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1080848/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1080848/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"VfhwYrjt\";\n\tdkim-atps=neutral", "spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; " ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 44d5td2hy3z9sQq\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 8 Apr 2019 20:16:41 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid ED301C21E4F; Mon, 8 Apr 2019 10:16:09 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 00B71C21E77;\n\tMon, 8 Apr 2019 10:15:50 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 0634EC21E29; Mon, 8 Apr 2019 10:15:45 +0000 (UTC)", "from EUR02-AM5-obe.outbound.protection.outlook.com\n\t(mail-eopbgr00056.outbound.protection.outlook.com [40.107.0.56])\n\tby lists.denx.de (Postfix) with ESMTPS id 63168C21DFD\n\tfor <u-boot@lists.denx.de>; Mon, 8 Apr 2019 10:15:42 +0000 (UTC)", "from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.3.19) by\n\tAM6PR04MB4533.eurprd04.prod.outlook.com (20.177.38.21) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1771.16; Mon, 8 Apr 2019 10:15:41 +0000", "from AM6PR04MB5781.eurprd04.prod.outlook.com\n\t([fe80::f9db:ed86:614e:460]) by\n\tAM6PR04MB5781.eurprd04.prod.outlook.com\n\t([fe80::f9db:ed86:614e:460%3]) with mapi id 15.20.1771.014;\n\tMon, 8 Apr 2019 10:15:41 +0000" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=SPF_HELO_PASS, T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=gprQgwjmms1t1Z9Bo11xzStEjGpEM7z+W3uh44HKfmM=;\n\tb=VfhwYrjtHFv89ocvqihfsfxyHM1G6n9eUsz3phjEGbsQIzUlRB+dTd/zUPRXJdeqz6A5/vOYlV4ZiG2IwXU+qHphFnnA2GwCQqILgLl7Y1MRkWkcsywrB7cLohmZg9VIIGUOkB6iFR6oKwNuvLrUkn31xCLxLVPNWGeZ0qB54YU=", "From": "\"Z.q. Hou\" <zhiqiang.hou@nxp.com>", "To": "\"u-boot@lists.denx.de\" <u-boot@lists.denx.de>,\n\t\"albert.u.boot@aribaud.net\"\n\t<albert.u.boot@aribaud.net>, Priyanka Jain <priyanka.jain@nxp.com>,\n\tYork Sun <york.sun@nxp.com>,\n\t\"sriram.dash@nxp.com\" <sriram.dash@nxp.com>, \n\t\"yamada.masahiro@socionext.com\" <yamada.masahiro@socionext.com>,\n\tPrabhakar\n\tKushwaha <prabhakar.kushwaha@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com>,\n\t\"M.h. Lian\" <minghuan.lian@nxp.com>,\n\t\"bmeng.cn@gmail.com\" <bmeng.cn@gmail.com>", "Thread-Topic": "[PATCHv5 3/8] armv8: lx2160a: add MMU table entries for PCIe", "Thread-Index": "AQHU7fQFim+2INZoSUa/ursXzw/Adw==", "Date": "Mon, 8 Apr 2019 10:15:41 +0000", "Message-ID": "<20190408101708.23251-4-Zhiqiang.Hou@nxp.com>", "References": "<20190408101708.23251-1-Zhiqiang.Hou@nxp.com>", "In-Reply-To": "<20190408101708.23251-1-Zhiqiang.Hou@nxp.com>", "Accept-Language": "zh-CN, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "HK0PR03CA0107.apcprd03.prod.outlook.com\n\t(2603:1096:203:b0::23) To AM6PR04MB5781.eurprd04.prod.outlook.com\n\t(2603:10a6:20b:ad::19)", "authentication-results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"VfhwYrjt\";\n\tdkim-atps=neutral", "spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; " ], "x-ms-exchange-messagesentrepresentingtype": "1", "x-mailer": "git-send-email 2.17.1", "x-originating-ip": "[119.31.174.73]", "x-ms-publictraffictype": "Email", "x-ms-office365-filtering-correlation-id": "c1d2f346-b793-4120-48fe-08d6bc0b276b", "x-ms-office365-filtering-ht": "Tenant", "x-microsoft-antispam": "BCL:0; PCL:0;\n\tRULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);\n\tSRVR:AM6PR04MB4533; ", "x-ms-traffictypediagnostic": "AM6PR04MB4533:", "x-microsoft-antispam-prvs": "<AM6PR04MB4533C037A25F1F750EB05D6B842C0@AM6PR04MB4533.eurprd04.prod.outlook.com>", "x-forefront-prvs": "0001227049", "x-forefront-antispam-report": "SFV:NSPM;\n\tSFS:(10009020)(136003)(39860400002)(396003)(366004)(346002)(376002)(189003)(199004)(186003)(36756003)(11346002)(102836004)(2501003)(316002)(76176011)(14444005)(6506007)(386003)(25786009)(26005)(52116002)(110136005)(66066001)(68736007)(476003)(8936002)(81166006)(50226002)(81156014)(4326008)(256004)(106356001)(1076003)(71200400001)(71190400001)(105586002)(86362001)(2616005)(2201001)(2906002)(7736002)(8676002)(99286004)(486006)(53936002)(6512007)(6116002)(3846002)(6436002)(446003)(478600001)(6486002)(97736004)(305945005)(14454004)(5660300002)(921003)(1121003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4533;\n\tH:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; MX:1; A:1; ", "received-spf": "None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)", "x-ms-exchange-senderadcheck": "1", "x-microsoft-antispam-message-info": "fd6s6W/Cv5EOBME7+QPcV3kE/NHKshv3nlFEiAYM2R/p7/BCX+6VlEaPsgqVFzfERALtLBfyfVWe45R6rN8C6NuzyBAzZFbRBtLLhD9VDpf47GNDD+HUUbvVSmGSF63T1DZnddf5mWwRKyv4EzTjGzb56ftJ3qXrsH2UlCuvUM/21W25YEi8y8tN6JDPUeanf5j8uvWKBfneSRumLL11WUoIHZrqTFEbJ9iJO2mpbjgqlh8T/zqDjk2kgkmUCOhmQLbkgFWEhI5K8p+UwsSoTLfAiFkaz/YgJ9m6wnwGtfx0B0AMH6ZpTWKrobAxc80re4UwCvjRWTz9+zutYjBJhjOKNO/Rj5fVfbwlpr6V2toamIsffCXZEK4DATcVSVu7D33upnoIP+zoy+7y85VQrAkrEr++4eY4FGSLlYg/qB4=", "MIME-Version": "1.0", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "c1d2f346-b793-4120-48fe-08d6bc0b276b", "X-MS-Exchange-CrossTenant-originalarrivaltime": "08 Apr 2019 10:15:41.5441\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM6PR04MB4533", "Cc": "\"Z.q. Hou\" <zhiqiang.hou@nxp.com>", "Subject": "[U-Boot] [PATCHv5 3/8] armv8: lx2160a: add MMU table entries for\n\tPCIe", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nThe lx2160a have up to 6 PCIe controllers and have different\naddress and size of PCIe region.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n---\nV5:\n - Changed to use PCIe address macro to determine if precompile the PCIe\n MMU entry.\n\n arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 ++++++++++++++\n arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 ++\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 14 +++++++++++++-\n 3 files changed, 29 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\nindex 36ede9c98e..32ff5c87a8 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\n@@ -257,6 +257,20 @@ static struct mm_region final_map[] = {\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN\n \t},\n+#endif\n+#ifdef SYS_PCIE5_PHYS_ADDR\n+\t{ SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,\n+\t SYS_PCIE5_PHYS_SIZE,\n+\t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN\n+\t},\n+#endif\n+#ifdef SYS_PCIE6_PHYS_ADDR\n+\t{ SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,\n+\t SYS_PCIE6_PHYS_SIZE,\n+\t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN\n+\t},\n #endif\n \t{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,\n \t CONFIG_SYS_FSL_WRIOP1_SIZE,\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h\nindex 89124cdb0e..bdeb62576c 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h\n@@ -44,6 +44,8 @@\n #define CONFIG_SYS_PCIE2_PHYS_SIZE\t0x800000000\n #define CONFIG_SYS_PCIE3_PHYS_SIZE\t0x800000000\n #define CONFIG_SYS_PCIE4_PHYS_SIZE\t0x800000000\n+#define SYS_PCIE5_PHYS_SIZE\t\t0x800000000\n+#define SYS_PCIE6_PHYS_SIZE\t\t0x800000000\n #endif\n #define CONFIG_SYS_FSL_WRIOP1_BASE\t0x4300000000\n #define CONFIG_SYS_FSL_WRIOP1_SIZE\t0x100000000\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 9fab88ab2f..c9aa0cad71 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -167,7 +167,19 @@\n #define CONFIG_SYS_PCIE2_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x2500000)\n #define CONFIG_SYS_PCIE3_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x2600000)\n #define CONFIG_SYS_PCIE4_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x2700000)\n-#ifdef CONFIG_ARCH_LS1088A\n+#ifdef CONFIG_ARCH_LX2160A\n+#define SYS_PCIE5_ADDR\t\t\t\t(CONFIG_SYS_IMMR + 0x2800000)\n+#define SYS_PCIE6_ADDR\t\t\t\t(CONFIG_SYS_IMMR + 0x2900000)\n+#endif\n+\n+#ifdef CONFIG_ARCH_LX2160A\n+#define CONFIG_SYS_PCIE1_PHYS_ADDR\t\t0x8000000000ULL\n+#define CONFIG_SYS_PCIE2_PHYS_ADDR\t\t0x8800000000ULL\n+#define CONFIG_SYS_PCIE3_PHYS_ADDR\t\t0x9000000000ULL\n+#define CONFIG_SYS_PCIE4_PHYS_ADDR\t\t0x9800000000ULL\n+#define SYS_PCIE5_PHYS_ADDR\t\t\t0xa000000000ULL\n+#define SYS_PCIE6_PHYS_ADDR\t\t\t0xa800000000ULL\n+#elif CONFIG_ARCH_LS1088A\n #define CONFIG_SYS_PCIE1_PHYS_ADDR\t\t0x2000000000ULL\n #define CONFIG_SYS_PCIE2_PHYS_ADDR\t\t0x2800000000ULL\n #define CONFIG_SYS_PCIE3_PHYS_ADDR\t\t0x3000000000ULL\n", "prefixes": [ "U-Boot", "PATCHv5", "3/8" ] }