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GET /api/patches/1051998/?format=api
{ "id": 1051998, "url": "http://patchwork.ozlabs.org/api/patches/1051998/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/patch/1551820067-53510-1-git-send-email-anoo@linux.ibm.com/", "project": { "id": 56, "url": "http://patchwork.ozlabs.org/api/projects/56/?format=api", "name": "OpenBMC development", "link_name": "openbmc", "list_id": "openbmc.lists.ozlabs.org", "list_email": "openbmc@lists.ozlabs.org", "web_url": "http://github.com/openbmc/", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1551820067-53510-1-git-send-email-anoo@linux.ibm.com>", "list_archive_url": null, "date": "2019-03-05T21:07:47", "name": "ARM: dts: aspeed: Add Swift BMC machine", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "2279944baf675bbd38b8aa49add65c7f8c8eab65", "submitter": { "id": 74976, "url": "http://patchwork.ozlabs.org/api/people/74976/?format=api", "name": "Adriana Kobylak", "email": "anoo@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/openbmc/patch/1551820067-53510-1-git-send-email-anoo@linux.ibm.com/mbox/", "series": [ { "id": 95555, "url": "http://patchwork.ozlabs.org/api/series/95555/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/list/?series=95555", "date": "2019-03-05T21:07:47", "name": "ARM: dts: aspeed: Add Swift BMC machine", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/95555/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1051998/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1051998/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (4096 bits)\n\tserver-digest SHA256) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 44DTyQ0vyLz9s70\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 6 Mar 2019 08:08:30 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 44DTyP5zyCzDqCt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 6 Mar 2019 08:08:29 +1100 (AEDT)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 44DTxr3NWMzDqCX\n\tfor <openbmc@lists.ozlabs.org>; Wed, 6 Mar 2019 08:07:59 +1100 (AEDT)", "from pps.filterd (m0098399.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx25L59EQ080941\n\tfor <openbmc@lists.ozlabs.org>; Tue, 5 Mar 2019 16:07:55 -0500", "from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2r1x9a7p8k-1\n\t(version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT)\n\tfor <openbmc@lists.ozlabs.org>; Tue, 05 Mar 2019 16:07:54 -0500", "from localhost\n\tby e34.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <openbmc@lists.ozlabs.org> from <anoo@linux.ibm.com>;\n\tTue, 5 Mar 2019 21:07:53 -0000", "from b03cxnp08025.gho.boulder.ibm.com (9.17.130.17)\n\tby e34.co.us.ibm.com (192.168.1.134) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\t(version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256)\n\tTue, 5 Mar 2019 21:07:51 -0000", "from b03ledav005.gho.boulder.ibm.com\n\t(b03ledav005.gho.boulder.ibm.com [9.17.130.236])\n\tby b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id x25L7nNL32374794\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256\n\tverify=OK); Tue, 5 Mar 2019 21:07:50 GMT", "from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id B5054BE051;\n\tTue, 5 Mar 2019 21:07:49 +0000 (GMT)", "from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 4F43FBE04F;\n\tTue, 5 Mar 2019 21:07:49 +0000 (GMT)", "from habcap11p1.aus.stglabs.ibm.com (unknown [9.41.164.53])\n\tby b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP;\n\tTue, 5 Mar 2019 21:07:49 +0000 (GMT)" ], "Authentication-Results": [ "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=linux.ibm.com", "lists.ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=linux.ibm.com\n\t(client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=anoo@linux.ibm.com; receiver=<UNKNOWN>)", "lists.ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=linux.ibm.com" ], "From": "Adriana Kobylak <anoo@linux.ibm.com>", "To": "joel@jms.id.au, mspinler@linux.ibm.com, msbarth@linux.ibm.com", "Subject": "[PATCH] ARM: dts: aspeed: Add Swift BMC machine", "Date": "Tue, 5 Mar 2019 15:07:47 -0600", "X-Mailer": "git-send-email 2.7.4", "X-TM-AS-GCONF": "00", "x-cbid": "19030521-0016-0000-0000-0000098C5881", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00010710; HX=3.00000242; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000281; SDB=6.01170122; UDB=6.00611515;\n\tIPR=6.00950755; \n\tMB=3.00025846; MTD=3.00000008; XFM=3.00000015; UTC=2019-03-05 21:07:52", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "19030521-0017-0000-0000-0000425B311F", "Message-Id": "<1551820067-53510-1-git-send-email-anoo@linux.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-03-05_10:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tpriorityscore=1501\n\tmalwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0\n\tclxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0\n\tmlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx\n\tscancount=1 engine=8.0.1-1810050000 definitions=main-1903050136", "X-BeenThere": "openbmc@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Development list for OpenBMC <openbmc.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/openbmc>,\n\t<mailto:openbmc-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/openbmc/>", "List-Post": "<mailto:openbmc@lists.ozlabs.org>", "List-Help": "<mailto:openbmc-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/openbmc>,\n\t<mailto:openbmc-request@lists.ozlabs.org?subject=subscribe>", "Cc": "openbmc@lists.ozlabs.org", "Errors-To": "openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"openbmc\"\n\t<openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "The Swift BMC is an ASPEED ast2500 based BMC that is part of\na Power9 server. This adds the device tree description for\nmost upstream components.\nThere's a pending TODO to create the flash layout for its\n16GB NAND flash chip. Use the default 32MB NOR flash chip\nfor this initial commit.\n\nSigned-off-by: Adriana Kobylak <anoo@linux.ibm.com>\n---\n arch/arm/boot/dts/Makefile | 1 +\n arch/arm/boot/dts/aspeed-bmc-opp-swift.dts | 702 +++++++++++++++++++++++++++++\n 2 files changed, 703 insertions(+)\n create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-swift.dts", "diff": "diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile\nindex 1a2db60..2e0011b 100644\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -1204,6 +1204,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \\\n \taspeed-bmc-opp-lanyang.dtb \\\n \taspeed-bmc-opp-palmetto.dtb \\\n \taspeed-bmc-opp-romulus.dtb \\\n+\taspeed-bmc-opp-swift.dtb \\\n \taspeed-bmc-opp-witherspoon.dtb \\\n \taspeed-bmc-opp-zaius.dtb \\\n \taspeed-bmc-portwell-neptune.dtb \\\ndiff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts\nnew file mode 100644\nindex 0000000..27459b7\n--- /dev/null\n+++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts\n@@ -0,0 +1,702 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/dts-v1/;\n+#include \"aspeed-g5.dtsi\"\n+#include <dt-bindings/gpio/aspeed-gpio.h>\n+#include <dt-bindings/leds/leds-pca955x.h>\n+\n+/ {\n+\tmodel = \"Swift BMC\";\n+\tcompatible = \"ibm,swift-bmc\", \"aspeed,ast2500\";\n+\n+\tchosen {\n+\t\tstdout-path = &uart5;\n+\t\tbootargs = \"console=ttyS4,115200 earlyprintk\";\n+\t};\n+\n+\tmemory@80000000 {\n+\t\treg = <0x80000000 0x20000000>;\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tflash_memory: region@98000000 {\n+\t\t\tno-map;\n+\t\t\treg = <0x98000000 0x04000000>; /* 64M */\n+\t\t};\n+\n+\t\tgfx_memory: framebuffer {\n+\t\t\tsize = <0x01000000>;\n+\t\t\talignment = <0x01000000>;\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treusable;\n+\t\t};\n+\t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\n+\t\tair-water {\n+\t\t\tlabel = \"air-water\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <ASPEED_GPIO(B, 5)>;\n+\t\t};\n+\n+\t\tcheckstop {\n+\t\t\tlabel = \"checkstop\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <ASPEED_GPIO(J, 2)>;\n+\t\t};\n+\n+\t\tps0-presence {\n+\t\t\tlabel = \"ps0-presence\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <ASPEED_GPIO(R, 7)>;\n+\t\t};\n+\n+\t\tps1-presence {\n+\t\t\tlabel = \"ps1-presence\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <ASPEED_GPIO(N, 0)>;\n+\t\t};\n+\t};\n+\n+\tiio-hwmon-battery {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 12>;\n+\t};\n+\n+\tgpio-keys-polled {\n+\t\tcompatible = \"gpio-keys-polled\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tpoll-interval = <1000>;\n+\n+\t\tfan0-presence {\n+\t\t\tlabel = \"fan0-presence\";\n+\t\t\tgpios = <&pca0 5 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <5>;\n+\t\t};\n+\n+\t\tfan1-presence {\n+\t\t\tlabel = \"fan1-presence\";\n+\t\t\tgpios = <&pca0 6 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <6>;\n+\t\t};\n+\n+\t\tfan2-presence {\n+\t\t\tlabel = \"fan2-presence\";\n+\t\t\tgpios = <&pca0 7 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <7>;\n+\t\t};\n+\n+\t\tfan3-presence {\n+\t\t\tlabel = \"fan3-presence\";\n+\t\t\tgpios = <&pca0 8 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <8>;\n+\t\t};\n+\n+\t\tfanboost-presence {\n+\t\t\tlabel = \"fanboost-presence\";\n+\t\t\tgpios = <&pca0 9 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <9>;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tfan0 {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca0 0 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfan1 {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca0 1 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfan2 {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca0 2 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfan3 {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca0 3 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfanboost {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca0 4 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfront-fault {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca0 13 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfront-power {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca0 14 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfront-id {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca0 15 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\trear-fault {\n+\t\t\tgpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\trear-id {\n+\t\t\tgpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\trear-power {\n+\t\t\tgpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tfsi: gpio-fsi {\n+\t\tcompatible = \"fsi-master-gpio\", \"fsi-master\";\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <0>;\n+\t\tno-gpio-delays;\n+\n+\t\tclock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;\n+\t\tdata-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;\n+\t\tmux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;\n+\t\tenable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;\n+\t\ttrans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tiio-hwmon-dps310 {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&dps 0>;\n+\t};\n+\n+};\n+\n+/* TODO Update flash layout for 16GB NAND */\n+&fmc {\n+\tstatus = \"okay\";\n+\tflash@0 {\n+\t\tstatus = \"okay\";\n+\t\tm25p,fast-read;\n+\t\tlabel = \"bmc\";\n+\t\tspi-max-frequency = <50000000>;\n+#include \"openbmc-flash-layout.dtsi\"\n+\t};\n+};\n+\n+&spi1 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_spi1_default>;\n+\n+\tflash@0 {\n+\t\tstatus = \"okay\";\n+\t\tlabel = \"pnor\";\n+\t\tm25p,fast-read;\n+\t\tspi-max-frequency = <100000000>;\n+\t};\n+};\n+\n+&uart1 {\n+\t/* Rear RS-232 connector */\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_txd1_default\n+\t\t\t&pinctrl_rxd1_default\n+\t\t\t&pinctrl_nrts1_default\n+\t\t\t&pinctrl_ndtr1_default\n+\t\t\t&pinctrl_ndsr1_default\n+\t\t\t&pinctrl_ncts1_default\n+\t\t\t&pinctrl_ndcd1_default\n+\t\t\t&pinctrl_nri1_default>;\n+};\n+\n+&uart2 {\n+\t/* APSS */\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;\n+};\n+\n+&uart5 {\n+\tstatus = \"okay\";\n+};\n+\n+&lpc_ctrl {\n+\tstatus = \"okay\";\n+\tmemory-region = <&flash_memory>;\n+\tflash = <&spi1>;\n+};\n+\n+&mbox {\n+\tstatus = \"okay\";\n+};\n+\n+&mac0 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_rmii1_default>;\n+\tuse-ncsi;\n+};\n+\n+&i2c2 {\n+\tstatus = \"okay\";\n+\n+\t/* MUX ->\n+\t * Samtec 1\n+\t * Samtec 2\n+\t */\n+};\n+\n+&i2c3 {\n+\tstatus = \"okay\";\n+\n+\tmax31785@52 {\n+\t\tcompatible = \"maxim,max31785a\";\n+\t\treg = <0x52>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tfan@0 {\n+\t\t\tcompatible = \"pmbus-fan\";\n+\t\t\treg = <0>;\n+\t\t\ttach-pulses = <2>;\n+\t\t\tmaxim,fan-rotor-input = \"tach\";\n+\t\t\tmaxim,fan-pwm-freq = <25000>;\n+\t\t\tmaxim,fan-dual-tach;\n+\t\t\tmaxim,fan-no-watchdog;\n+\t\t\tmaxim,fan-no-fault-ramp;\n+\t\t\tmaxim,fan-ramp = <2>;\n+\t\t\tmaxim,fan-fault-pin-mon;\n+\t\t};\n+\n+\t\tfan@1 {\n+\t\t\tcompatible = \"pmbus-fan\";\n+\t\t\treg = <1>;\n+\t\t\ttach-pulses = <2>;\n+\t\t\tmaxim,fan-rotor-input = \"tach\";\n+\t\t\tmaxim,fan-pwm-freq = <25000>;\n+\t\t\tmaxim,fan-dual-tach;\n+\t\t\tmaxim,fan-no-watchdog;\n+\t\t\tmaxim,fan-no-fault-ramp;\n+\t\t\tmaxim,fan-ramp = <2>;\n+\t\t\tmaxim,fan-fault-pin-mon;\n+\t\t};\n+\n+\t\tfan@2 {\n+\t\t\tcompatible = \"pmbus-fan\";\n+\t\t\treg = <2>;\n+\t\t\ttach-pulses = <2>;\n+\t\t\tmaxim,fan-rotor-input = \"tach\";\n+\t\t\tmaxim,fan-pwm-freq = <25000>;\n+\t\t\tmaxim,fan-dual-tach;\n+\t\t\tmaxim,fan-no-watchdog;\n+\t\t\tmaxim,fan-no-fault-ramp;\n+\t\t\tmaxim,fan-ramp = <2>;\n+\t\t\tmaxim,fan-fault-pin-mon;\n+\t\t};\n+\n+\t\tfan@3 {\n+\t\t\tcompatible = \"pmbus-fan\";\n+\t\t\treg = <3>;\n+\t\t\ttach-pulses = <2>;\n+\t\t\tmaxim,fan-rotor-input = \"tach\";\n+\t\t\tmaxim,fan-pwm-freq = <25000>;\n+\t\t\tmaxim,fan-dual-tach;\n+\t\t\tmaxim,fan-no-watchdog;\n+\t\t\tmaxim,fan-no-fault-ramp;\n+\t\t\tmaxim,fan-ramp = <2>;\n+\t\t\tmaxim,fan-fault-pin-mon;\n+\t\t};\n+\n+\t\tfan@4 {\n+\t\t\tcompatible = \"pmbus-fan\";\n+\t\t\treg = <4>;\n+\t\t\ttach-pulses = <2>;\n+\t\t\tmaxim,fan-rotor-input = \"tach\";\n+\t\t\tmaxim,fan-pwm-freq = <25000>;\n+\t\t\tmaxim,fan-dual-tach;\n+\t\t\tmaxim,fan-no-watchdog;\n+\t\t\tmaxim,fan-no-fault-ramp;\n+\t\t\tmaxim,fan-ramp = <2>;\n+\t\t\tmaxim,fan-fault-pin-mon;\n+\t\t};\n+\t};\n+\n+\tpca0: pca9552@60 {\n+\t\tcompatible = \"nxp,pca9552\";\n+\t\treg = <0x60>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\n+\t\tgpio@0 {\n+\t\t\treg = <0>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@1 {\n+\t\t\treg = <1>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@2 {\n+\t\t\treg = <2>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@3 {\n+\t\t\treg = <3>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@4 {\n+\t\t\treg = <4>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@5 {\n+\t\t\treg = <5>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@6 {\n+\t\t\treg = <6>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@7 {\n+\t\t\treg = <7>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@8 {\n+\t\t\treg = <8>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@9 {\n+\t\t\treg = <9>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@10 {\n+\t\t\treg = <10>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@11 {\n+\t\t\treg = <11>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@12 {\n+\t\t\treg = <12>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@13 {\n+\t\t\treg = <13>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@14 {\n+\t\t\treg = <14>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@15 {\n+\t\t\treg = <15>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t};\n+\n+\tpower-supply@68 {\n+\t\tcompatible = \"ibm,cffps1\";\n+\t\treg = <0x68>;\n+\t};\n+\n+\teeprom@50 {\n+\t\tcompatible = \"atmel,24c64\";\n+\t\treg = <0x50>;\n+\t};\n+\n+\tpower-supply@69 {\n+\t\tcompatible = \"ibm,cffps1\";\n+\t\treg = <0x69>;\n+\t};\n+\n+\teeprom@51 {\n+\t\tcompatible = \"atmel,24c64\";\n+\t\treg = <0x51>;\n+\t};\n+};\n+\n+&i2c7 {\n+\tstatus = \"okay\";\n+\n+\tdps: dps310@76 {\n+\t\tcompatible = \"infineon,dps310\";\n+\t\treg = <0x76>;\n+\t\t#io-channel-cells = <0>;\n+\t};\n+\n+\ttmp275@48 {\n+\t\tcompatible = \"ti,tmp275\";\n+\t\treg = <0x48>;\n+\t};\n+\n+\tsi7021a20@20 {\n+\t\tcompatible = \"si,si7021a20\";\n+\t\treg = <0x20>;\n+\t};\n+\n+\teeprom@50 {\n+\t\tcompatible = \"atmel,24c64\";\n+\t\treg = <0x50>;\n+\t};\n+\n+\tpca9551@60 {\n+\t\tcompatible = \"nxp,pca9551\";\n+\t\treg = <0x60>;\n+\t};\n+};\n+\n+&i2c8 {\n+\tstatus = \"okay\";\n+\n+\tpca9552: pca9552@60 {\n+\t\tcompatible = \"nxp,pca9552\";\n+\t\treg = <0x60>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\n+\t\tgpio-line-names = \"PS_SMBUS_RESET_N\", \"APSS_RESET_N\",\n+\t\t\t\"GPU0_TH_OVERT_N_BUFF\",\t\"GPU1_TH_OVERT_N_BUFF\",\n+\t\t\t\"GPU2_TH_OVERT_N_BUFF\", \"GPU3_TH_OVERT_N_BUFF\",\n+\t\t\t\"P9_SCM0_PRES\",\t\"P9_SCM1_PRES\",\n+\t\t\t\"GPU0_PWR_GOOD_BUFF\", \"GPU1_PWR_GOOD_BUFF\",\n+\t\t\t\"GPU2_PWR_GOOD_BUFF\", \"GPU3_PWR_GOOD_BUFF\",\n+\t\t\t\"PRESENT_VRM_CP0_N\", \"PRESENT_VRM_CP1_N\",\n+\t\t\t\"12V_BREAKER_FLT_N\", \"THROTTLE_UNLATCHED_N\";\n+\n+\t\tgpio@0 {\n+\t\t\treg = <0>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@1 {\n+\t\t\treg = <1>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@2 {\n+\t\t\treg = <2>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@3 {\n+\t\t\treg = <3>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@4 {\n+\t\t\treg = <4>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@5 {\n+\t\t\treg = <5>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@6 {\n+\t\t\treg = <6>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@7 {\n+\t\t\treg = <7>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@8 {\n+\t\t\treg = <8>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@9 {\n+\t\t\treg = <9>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@10 {\n+\t\t\treg = <10>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@11 {\n+\t\t\treg = <11>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@12 {\n+\t\t\treg = <12>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@13 {\n+\t\t\treg = <13>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@14 {\n+\t\t\treg = <14>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t\tgpio@15 {\n+\t\t\treg = <15>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t};\n+\n+\trtc@32 {\n+\t\tcompatible = \"epson,rx8900\";\n+\t\treg = <0x32>;\n+\t};\n+\n+\teeprom@51 {\n+\t\tcompatible = \"atmel,24c64\";\n+\t\treg = <0x51>;\n+\t};\n+\n+\tucd90160@64 {\n+\t\tcompatible = \"ti,ucd90160\";\n+\t\treg = <0x64>;\n+\t};\n+};\n+\n+&i2c9 {\n+\tstatus = \"okay\";\n+\n+\ttmp423a@4c {\n+\t\tcompatible = \"ti,tmp423\";\n+\t\treg = <0x4c>;\n+\t};\n+\n+\tir35221@71 {\n+\t\tcompatible = \"infineon,ir35221\";\n+\t\treg = <0x71>;\n+\t};\n+\n+\tir35221@72 {\n+\t\tcompatible = \"infineon,ir35221\";\n+\t\treg = <0x72>;\n+\t};\n+};\n+\n+&i2c10 {\n+\tstatus = \"okay\";\n+\n+\ttmp423a@4c {\n+\t\tcompatible = \"ti,tmp423\";\n+\t\treg = <0x4c>;\n+\t};\n+\n+\tir35221@71 {\n+\t\tcompatible = \"infineon,ir35221\";\n+\t\treg = <0x71>;\n+\t};\n+\n+\tir35221@72 {\n+\t\tcompatible = \"infineon,ir35221\";\n+\t\treg = <0x72>;\n+\t};\n+};\n+\n+&i2c11 {\n+\t/* MUX\n+\t * -> PCIe Slot 0\n+\t * -> PCIe Slot 1\n+\t * -> PCIe Slot 2\n+\t * -> PCIe Slot 3\n+\t */\n+\tstatus = \"okay\";\n+};\n+\n+&i2c12 {\n+\tstatus = \"okay\";\n+\n+\ttmp275@48 {\n+\t\tcompatible = \"ti,tmp275\";\n+\t\treg = <0x48>;\n+\t};\n+\n+\ttmp275@4a {\n+\t\tcompatible = \"ti,tmp275\";\n+\t\treg = <0x4a>;\n+\t};\n+};\n+\n+&i2c13 {\n+\tstatus = \"okay\";\n+};\n+\n+&vuart {\n+\tstatus = \"okay\";\n+};\n+\n+&gfx {\n+\tstatus = \"okay\";\n+\tmemory-region = <&gfx_memory>;\n+};\n+\n+&pinctrl {\n+\taspeed,external-nodes = <&gfx &lhc>;\n+};\n+\n+&wdt1 {\n+\taspeed,reset-type = \"none\";\n+\taspeed,external-signal;\n+\taspeed,ext-push-pull;\n+\taspeed,ext-active-high;\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_wdtrst1_default>;\n+};\n+\n+&wdt2 {\n+\taspeed,alt-boot;\n+};\n+\n+&ibt {\n+\tstatus = \"okay\";\n+};\n+\n+&adc {\n+\tstatus = \"okay\";\n+};\n+\n+#include \"ibm-power9-dual.dtsi\"\n", "prefixes": [] }