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GET /api/patches/1049858/?format=api
{ "id": 1049858, "url": "http://patchwork.ozlabs.org/api/patches/1049858/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190228232603.32156-14-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190228232603.32156-14-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2019-02-28T23:25:59", "name": "[S17,13/17] ice: Add reg_idx variable in ice_q_vector structure", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "8f179373626c76bd7e634d3560adf1a6ed1d4e91", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190228232603.32156-14-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 94829, "url": "http://patchwork.ozlabs.org/api/series/94829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=94829", "date": "2019-02-28T23:25:46", "name": "Implementation updates for ice", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/94829/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1049858/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1049858/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.137; helo=fraxinus.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 449TFj674Gz9s4V\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 1 Mar 2019 10:26:17 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 78D8284516;\n\tThu, 28 Feb 2019 23:26:16 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 0f8B-OxqPPP6; Thu, 28 Feb 2019 23:26:15 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 2A59685E5D;\n\tThu, 28 Feb 2019 23:26:15 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id A1E741BF3EA\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 28 Feb 2019 23:26:10 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 9F1AC813E6\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 28 Feb 2019 23:26:10 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id CemlPUsqZJBd for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 28 Feb 2019 23:26:05 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby whitealder.osuosl.org (Postfix) with ESMTPS id E10CF81426\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 28 Feb 2019 23:26:05 +0000 (UTC)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 Feb 2019 15:26:05 -0800", "from shasta.jf.intel.com ([10.166.241.11])\n\tby FMSMGA003.fm.intel.com with ESMTP; 28 Feb 2019 15:26:05 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.58,425,1544515200\"; d=\"scan'208\";a=\"137128003\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Thu, 28 Feb 2019 15:25:59 -0800", "Message-Id": "<20190228232603.32156-14-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.5", "In-Reply-To": "<20190228232603.32156-1-anirudh.venkataramanan@intel.com>", "References": "<20190228232603.32156-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH S17 13/17] ice: Add reg_idx variable in\n\tice_q_vector structure", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Brett Creeley <brett.creeley@intel.com>\n\nEvery time we want to re-enable interrupts and/or write to a register\nthat requires an interrupt vector's hardware index we do the following:\n\nvsi->hw_base_vector + q_vector->v_idx\n\nThis is a wasteful operation, especially in the hot path. Fix this by\nadding a u16 reg_idx member to the ice_q_vector structure and make the\nnecessary changes to make this work.\n\nSigned-off-by: Brett Creeley <brett.creeley@intel.com>\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice.h | 3 +-\n drivers/net/ethernet/intel/ice/ice_lib.c | 84 ++++++++++++++++++++++++-------\n drivers/net/ethernet/intel/ice/ice_main.c | 13 +++--\n drivers/net/ethernet/intel/ice/ice_txrx.c | 2 +-\n 4 files changed, 76 insertions(+), 26 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h\nindex 878a75182d6d..d66aad49bfd4 100644\n--- a/drivers/net/ethernet/intel/ice/ice.h\n+++ b/drivers/net/ethernet/intel/ice/ice.h\n@@ -297,6 +297,7 @@ struct ice_q_vector {\n \tstruct ice_vsi *vsi;\n \n \tu16 v_idx;\t\t\t/* index in the vsi->q_vector array. */\n+\tu16 reg_idx;\n \tu8 num_ring_rx;\t\t\t/* total number of Rx rings in vector */\n \tu8 num_ring_tx;\t\t\t/* total number of Tx rings in vector */\n \tu8 itr_countdown;\t\t/* when 0 should adjust adaptive ITR */\n@@ -403,7 +404,7 @@ static inline void\n ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,\n \t\t struct ice_q_vector *q_vector)\n {\n-\tu32 vector = (vsi && q_vector) ? vsi->hw_base_vector + q_vector->v_idx :\n+\tu32 vector = (vsi && q_vector) ? q_vector->reg_idx :\n \t\t\t\t((struct ice_pf *)hw->back)->hw_oicr_idx;\n \tint itr = ICE_ITR_NONE;\n \tu32 val;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c\nindex 6d9571c8826d..399905396134 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lib.c\n+++ b/drivers/net/ethernet/intel/ice/ice_lib.c\n@@ -1805,13 +1805,12 @@ static void ice_cfg_itr_gran(struct ice_hw *hw)\n * ice_cfg_itr - configure the initial interrupt throttle values\n * @hw: pointer to the HW structure\n * @q_vector: interrupt vector that's being configured\n- * @vector: HW vector index to apply the interrupt throttling to\n *\n * Configure interrupt throttling values for the ring containers that are\n * associated with the interrupt vector passed in.\n */\n static void\n-ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector, u16 vector)\n+ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector)\n {\n \tice_cfg_itr_gran(hw);\n \n@@ -1825,7 +1824,7 @@ ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector, u16 vector)\n \t\trc->target_itr = ITR_TO_REG(rc->itr_setting);\n \t\trc->next_update = jiffies + 1;\n \t\trc->current_itr = rc->target_itr;\n-\t\twr32(hw, GLINT_ITR(rc->itr_idx, vector),\n+\t\twr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),\n \t\t ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);\n \t}\n \n@@ -1839,7 +1838,7 @@ ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector, u16 vector)\n \t\trc->target_itr = ITR_TO_REG(rc->itr_setting);\n \t\trc->next_update = jiffies + 1;\n \t\trc->current_itr = rc->target_itr;\n-\t\twr32(hw, GLINT_ITR(rc->itr_idx, vector),\n+\t\twr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),\n \t\t ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);\n \t}\n }\n@@ -1851,17 +1850,17 @@ ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector, u16 vector)\n void ice_vsi_cfg_msix(struct ice_vsi *vsi)\n {\n \tstruct ice_pf *pf = vsi->back;\n-\tu16 vector = vsi->hw_base_vector;\n \tstruct ice_hw *hw = &pf->hw;\n \tu32 txq = 0, rxq = 0;\n \tint i, q;\n \n-\tfor (i = 0; i < vsi->num_q_vectors; i++, vector++) {\n+\tfor (i = 0; i < vsi->num_q_vectors; i++) {\n \t\tstruct ice_q_vector *q_vector = vsi->q_vectors[i];\n+\t\tu16 reg_idx = q_vector->reg_idx;\n \n-\t\tice_cfg_itr(hw, q_vector, vector);\n+\t\tice_cfg_itr(hw, q_vector);\n \n-\t\twr32(hw, GLINT_RATE(vector),\n+\t\twr32(hw, GLINT_RATE(reg_idx),\n \t\t ice_intrl_usec_to_reg(q_vector->intrl, hw->intrl_gran));\n \n \t\t/* Both Transmit Queue Interrupt Cause Control register\n@@ -1886,7 +1885,7 @@ void ice_vsi_cfg_msix(struct ice_vsi *vsi)\n \t\t\telse\n \t\t\t\tval = QINT_TQCTL_CAUSE_ENA_M |\n \t\t\t\t (itr_idx << QINT_TQCTL_ITR_INDX_S) |\n-\t\t\t\t (vector << QINT_TQCTL_MSIX_INDX_S);\n+\t\t\t\t (reg_idx << QINT_TQCTL_MSIX_INDX_S);\n \t\t\twr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);\n \t\t\ttxq++;\n \t\t}\n@@ -1902,7 +1901,7 @@ void ice_vsi_cfg_msix(struct ice_vsi *vsi)\n \t\t\telse\n \t\t\t\tval = QINT_RQCTL_CAUSE_ENA_M |\n \t\t\t\t (itr_idx << QINT_RQCTL_ITR_INDX_S) |\n-\t\t\t\t (vector << QINT_RQCTL_MSIX_INDX_S);\n+\t\t\t\t (reg_idx << QINT_RQCTL_MSIX_INDX_S);\n \t\t\twr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);\n \t\t\trxq++;\n \t\t}\n@@ -2065,8 +2064,6 @@ ice_vsi_stop_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,\n \t\t\tbreak;\n \n \t\tfor (i = 0; i < vsi->tc_cfg.tc_info[tc].qcount_tx; i++) {\n-\t\t\tu16 v_idx;\n-\n \t\t\tif (!rings || !rings[q_idx] ||\n \t\t\t !rings[q_idx]->q_vector) {\n \t\t\t\terr = -EINVAL;\n@@ -2088,8 +2085,7 @@ ice_vsi_stop_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,\n \t\t\t/* trigger a software interrupt for the vector\n \t\t\t * associated to the queue to schedule NAPI handler\n \t\t\t */\n-\t\t\tv_idx = rings[i]->q_vector->v_idx;\n-\t\t\twr32(hw, GLINT_DYN_CTL(vsi->hw_base_vector + v_idx),\n+\t\t\twr32(hw, GLINT_DYN_CTL(rings[i]->q_vector->reg_idx),\n \t\t\t GLINT_DYN_CTL_SWINT_TRIG_M |\n \t\t\t GLINT_DYN_CTL_INTENA_MSK_M);\n \t\t\tq_idx++;\n@@ -2208,6 +2204,44 @@ static void ice_vsi_set_tc_cfg(struct ice_vsi *vsi)\n \tvsi->tc_cfg.numtc = ice_dcb_get_num_tc(cfg);\n }\n \n+/**\n+ * ice_vsi_set_q_vectors_reg_idx - set the HW register index for all q_vectors\n+ * @vsi: VSI to set the q_vectors register index on\n+ */\n+static int\n+ice_vsi_set_q_vectors_reg_idx(struct ice_vsi *vsi)\n+{\n+\tu16 i;\n+\n+\tif (!vsi || !vsi->q_vectors)\n+\t\treturn -EINVAL;\n+\n+\tice_for_each_q_vector(vsi, i) {\n+\t\tstruct ice_q_vector *q_vector = vsi->q_vectors[i];\n+\n+\t\tif (!q_vector) {\n+\t\t\tdev_err(&vsi->back->pdev->dev,\n+\t\t\t\t\"Failed to set reg_idx on q_vector %d VSI %d\\n\",\n+\t\t\t\ti, vsi->vsi_num);\n+\t\t\tgoto clear_reg_idx;\n+\t\t}\n+\n+\t\tq_vector->reg_idx = q_vector->v_idx + vsi->hw_base_vector;\n+\t}\n+\n+\treturn 0;\n+\n+clear_reg_idx:\n+\tice_for_each_q_vector(vsi, i) {\n+\t\tstruct ice_q_vector *q_vector = vsi->q_vectors[i];\n+\n+\t\tif (q_vector)\n+\t\t\tq_vector->reg_idx = 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n /**\n * ice_vsi_setup - Set up a VSI by a given type\n * @pf: board private structure\n@@ -2273,6 +2307,10 @@ ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,\n \t\tif (ret)\n \t\t\tgoto unroll_alloc_q_vector;\n \n+\t\tret = ice_vsi_set_q_vectors_reg_idx(vsi);\n+\t\tif (ret)\n+\t\t\tgoto unroll_vector_base;\n+\n \t\tret = ice_vsi_alloc_rings(vsi);\n \t\tif (ret)\n \t\t\tgoto unroll_vector_base;\n@@ -2311,6 +2349,10 @@ ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,\n \t\t} else {\n \t\t\tvsi->hw_base_vector = pf->vf[vf_id].first_vector_idx;\n \t\t}\n+\t\tret = ice_vsi_set_q_vectors_reg_idx(vsi);\n+\t\tif (ret)\n+\t\t\tgoto unroll_vector_base;\n+\n \t\tpf->q_left_tx -= vsi->alloc_txq;\n \t\tpf->q_left_rx -= vsi->alloc_rxq;\n \t\tbreak;\n@@ -2623,11 +2665,11 @@ void ice_vsi_dis_irq(struct ice_vsi *vsi)\n \n \t/* disable each interrupt */\n \tif (test_bit(ICE_FLAG_MSIX_ENA, pf->flags)) {\n-\t\tfor (i = vsi->hw_base_vector;\n-\t\t i < (vsi->num_q_vectors + vsi->hw_base_vector); i++)\n-\t\t\twr32(hw, GLINT_DYN_CTL(i), 0);\n+\t\tice_for_each_q_vector(vsi, i)\n+\t\t\twr32(hw, GLINT_DYN_CTL(vsi->q_vectors[i]->reg_idx), 0);\n \n \t\tice_flush(hw);\n+\n \t\tice_for_each_q_vector(vsi, i)\n \t\t\tsynchronize_irq(pf->msix_entries[i + base].vector);\n \t}\n@@ -2780,6 +2822,10 @@ int ice_vsi_rebuild(struct ice_vsi *vsi)\n \t\tif (ret)\n \t\t\tgoto err_vectors;\n \n+\t\tret = ice_vsi_set_q_vectors_reg_idx(vsi);\n+\t\tif (ret)\n+\t\t\tgoto err_vectors;\n+\n \t\tret = ice_vsi_alloc_rings(vsi);\n \t\tif (ret)\n \t\t\tgoto err_vectors;\n@@ -2801,6 +2847,10 @@ int ice_vsi_rebuild(struct ice_vsi *vsi)\n \t\tif (ret)\n \t\t\tgoto err_vectors;\n \n+\t\tret = ice_vsi_set_q_vectors_reg_idx(vsi);\n+\t\tif (ret)\n+\t\t\tgoto err_vectors;\n+\n \t\tret = ice_vsi_alloc_rings(vsi);\n \t\tif (ret)\n \t\t\tgoto err_vectors;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c\nindex 94b2aa6b4c3d..a0d2c337fede 100644\n--- a/drivers/net/ethernet/intel/ice/ice_main.c\n+++ b/drivers/net/ethernet/intel/ice/ice_main.c\n@@ -1592,23 +1592,23 @@ static void ice_free_irq_msix_misc(struct ice_pf *pf)\n /**\n * ice_ena_ctrlq_interrupts - enable control queue interrupts\n * @hw: pointer to HW structure\n- * @v_idx: HW vector index to associate the control queue interrupts with\n+ * @reg_idx: HW vector index to associate the control queue interrupts with\n */\n-static void ice_ena_ctrlq_interrupts(struct ice_hw *hw, u16 v_idx)\n+static void ice_ena_ctrlq_interrupts(struct ice_hw *hw, u16 reg_idx)\n {\n \tu32 val;\n \n-\tval = ((v_idx & PFINT_OICR_CTL_MSIX_INDX_M) |\n+\tval = ((reg_idx & PFINT_OICR_CTL_MSIX_INDX_M) |\n \t PFINT_OICR_CTL_CAUSE_ENA_M);\n \twr32(hw, PFINT_OICR_CTL, val);\n \n \t/* enable Admin queue Interrupt causes */\n-\tval = ((v_idx & PFINT_FW_CTL_MSIX_INDX_M) |\n+\tval = ((reg_idx & PFINT_FW_CTL_MSIX_INDX_M) |\n \t PFINT_FW_CTL_CAUSE_ENA_M);\n \twr32(hw, PFINT_FW_CTL, val);\n \n \t/* enable Mailbox queue Interrupt causes */\n-\tval = ((v_idx & PFINT_MBX_CTL_MSIX_INDX_M) |\n+\tval = ((reg_idx & PFINT_MBX_CTL_MSIX_INDX_M) |\n \t PFINT_MBX_CTL_CAUSE_ENA_M);\n \twr32(hw, PFINT_MBX_CTL, val);\n \n@@ -4214,8 +4214,7 @@ static void ice_tx_timeout(struct net_device *netdev)\n \t\t/* Read interrupt register */\n \t\tif (test_bit(ICE_FLAG_MSIX_ENA, pf->flags))\n \t\t\tval = rd32(hw,\n-\t\t\t\t GLINT_DYN_CTL(tx_ring->q_vector->v_idx +\n-\t\t\t\t\t\t tx_ring->vsi->hw_base_vector));\n+\t\t\t\t GLINT_DYN_CTL(tx_ring->q_vector->reg_idx));\n \n \t\tnetdev_info(netdev, \"tx_timeout: VSI_num: %d, Q %d, NTC: 0x%x, HW_HEAD: 0x%x, NTU: 0x%x, INT: 0x%x\\n\",\n \t\t\t vsi->vsi_num, hung_queue, tx_ring->next_to_clean,\ndiff --git a/drivers/net/ethernet/intel/ice/ice_txrx.c b/drivers/net/ethernet/intel/ice/ice_txrx.c\nindex fabee3e59eff..99f1a18af4ac 100644\n--- a/drivers/net/ethernet/intel/ice/ice_txrx.c\n+++ b/drivers/net/ethernet/intel/ice/ice_txrx.c\n@@ -1391,7 +1391,7 @@ ice_update_ena_itr(struct ice_vsi *vsi, struct ice_q_vector *q_vector)\n \n \tif (!test_bit(__ICE_DOWN, vsi->state))\n \t\twr32(&vsi->back->hw,\n-\t\t GLINT_DYN_CTL(vsi->hw_base_vector + q_vector->v_idx),\n+\t\t GLINT_DYN_CTL(q_vector->reg_idx),\n \t\t itr_val);\n }\n \n", "prefixes": [ "S17", "13/17" ] }