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GET /api/patches/1049838/?format=api
{ "id": 1049838, "url": "http://patchwork.ozlabs.org/api/patches/1049838/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190228232432.31659-4-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190228232432.31659-4-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2019-02-28T23:24:24", "name": "[S16,03/11] ice: Add code for DCB initialization part 3/4", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "9bfb450027c4eb2fd4dd316187435aab0aec6446", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190228232432.31659-4-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 94826, "url": "http://patchwork.ozlabs.org/api/series/94826/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=94826", "date": "2019-02-28T23:24:25", "name": "Add support for Data Center Bridging (DCB)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/94826/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1049838/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1049838/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.137; helo=fraxinus.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 449TCy11C1z9s70\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 1 Mar 2019 10:24:46 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id B768D85F08;\n\tThu, 28 Feb 2019 23:24:44 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id k8KUmPz9CBCs; Thu, 28 Feb 2019 23:24:41 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 0F70885E43;\n\tThu, 28 Feb 2019 23:24:41 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 71BA61BF410\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 28 Feb 2019 23:24:37 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 646B187A2F\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 28 Feb 2019 23:24:37 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id IErPp3vATmi5 for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 28 Feb 2019 23:24:35 +0000 (UTC)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id D393587695\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 28 Feb 2019 23:24:34 +0000 (UTC)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 Feb 2019 15:24:33 -0800", "from shasta.jf.intel.com ([10.166.241.11])\n\tby FMSMGA003.fm.intel.com with ESMTP; 28 Feb 2019 15:24:33 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.58,425,1544515200\"; d=\"scan'208\";a=\"137127720\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Thu, 28 Feb 2019 15:24:24 -0800", "Message-Id": "<20190228232432.31659-4-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.5", "In-Reply-To": "<20190228232432.31659-1-anirudh.venkataramanan@intel.com>", "References": "<20190228232432.31659-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH S16 03/11] ice: Add code for DCB\n\tinitialization part 3/4", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "This patch adds a new function ice_pf_dcb_cfg (and related helpers)\nwhich applies the DCB configuration obtained from the firmware. As\npart of this, VSIs/netdevs are updated with traffic class information.\n\nThis patch requires a bit of a refactor of existing code.\n\n1. For a MIB change event, the associated VSI is closed and brought up\n again. The gap between closing and opening the VSI can cause a race\n condition. Fix this by grabbing the rtnl_lock prior to closing the\n VSI and then only free it after re-opening the VSI during a MIB\n change event.\n\n2. ice_sched_query_elem is used in ice_sched.c and with this patch, in\n ice_dcb.c as well. However, ice_dcb.c is not built when CONFIG_DCB is\n unset. This results in namespace warnings (ice_sched.o: Externally\n defined symbols with no external references) when CONFIG_DCB is unset.\n To avoid this move ice_sched_query_elem from ice_sched.c to\n ice_common.c.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice.h | 13 +-\n drivers/net/ethernet/intel/ice/ice_adminq_cmd.h | 47 +++\n drivers/net/ethernet/intel/ice/ice_common.c | 25 ++\n drivers/net/ethernet/intel/ice/ice_common.h | 3 +\n drivers/net/ethernet/intel/ice/ice_dcb.c | 463 ++++++++++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_dcb.h | 17 +\n drivers/net/ethernet/intel/ice/ice_dcb_lib.c | 204 ++++++++++-\n drivers/net/ethernet/intel/ice/ice_dcb_lib.h | 13 +\n drivers/net/ethernet/intel/ice/ice_lib.c | 135 +++++++\n drivers/net/ethernet/intel/ice/ice_lib.h | 8 +\n drivers/net/ethernet/intel/ice/ice_main.c | 118 +++---\n drivers/net/ethernet/intel/ice/ice_sched.c | 27 +-\n drivers/net/ethernet/intel/ice/ice_sched.h | 4 +\n drivers/net/ethernet/intel/ice/ice_type.h | 2 +\n 14 files changed, 997 insertions(+), 82 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h\nindex d76333c808a3..6ca1094cb24a 100644\n--- a/drivers/net/ethernet/intel/ice/ice.h\n+++ b/drivers/net/ethernet/intel/ice/ice.h\n@@ -378,6 +378,9 @@ struct ice_pf {\n \tstruct ice_hw_port_stats stats_prev;\n \tstruct ice_hw hw;\n \tu8 stat_prev_loaded;\t/* has previous stats been loaded */\n+#ifdef CONFIG_DCB\n+\tu16 dcbx_cap;\n+#endif /* CONFIG_DCB */\n \tu32 tx_timeout_count;\n \tunsigned long tx_timeout_last_recovery;\n \tu32 tx_timeout_recovery_level;\n@@ -414,12 +417,6 @@ ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,\n \twr32(hw, GLINT_DYN_CTL(vector), val);\n }\n \n-static inline void ice_vsi_set_tc_cfg(struct ice_vsi *vsi)\n-{\n-\tvsi->tc_cfg.ena_tc = ICE_DFLT_TRAFFIC_CLASS;\n-\tvsi->tc_cfg.numtc = 1;\n-}\n-\n void ice_set_ethtool_ops(struct net_device *netdev);\n int ice_up(struct ice_vsi *vsi);\n int ice_down(struct ice_vsi *vsi);\n@@ -428,5 +425,9 @@ int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);\n void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);\n void ice_print_link_msg(struct ice_vsi *vsi, bool isup);\n void ice_napi_del(struct ice_vsi *vsi);\n+#ifdef CONFIG_DCB\n+int ice_pf_ena_all_vsi(struct ice_pf *pf, bool locked);\n+void ice_pf_dis_all_vsi(struct ice_pf *pf, bool locked);\n+#endif /* CONFIG_DCB */\n \n #endif /* _ICE_H_ */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\nindex bbceaca11541..cda93826a065 100644\n--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n@@ -747,6 +747,32 @@ struct ice_aqc_delete_elem {\n \t__le32 teid[1];\n };\n \n+/* Query Port ETS (indirect 0x040E)\n+ *\n+ * This indirect command is used to query port TC node configuration.\n+ */\n+struct ice_aqc_query_port_ets {\n+\t__le32 port_teid;\n+\t__le32 reserved;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+struct ice_aqc_port_ets_elem {\n+\tu8 tc_valid_bits;\n+\tu8 reserved[3];\n+\t/* 3 bits for UP per TC 0-7, 4th byte reserved */\n+\t__le32 up2tc;\n+\tu8 tc_bw_share[8];\n+\t__le32 port_eir_prof_id;\n+\t__le32 port_cir_prof_id;\n+\t/* 3 bits per Node priority to TC 0-7, 4th byte reserved */\n+\t__le32 tc_node_prio;\n+#define ICE_TC_NODE_PRIO_S\t0x4\n+\tu8 reserved1[4];\n+\t__le32 tc_node_teid[8]; /* Used for response, reserved in command */\n+};\n+\n /* Query Scheduler Resource Allocation (indirect 0x0412)\n * This indirect command retrieves the scheduler resources allocated by\n * EMP Firmware to the given PF.\n@@ -1212,6 +1238,23 @@ struct ice_aqc_get_cee_dcb_cfg_resp {\n \tu8 reserved[12];\n };\n \n+/* Set Local LLDP MIB (indirect 0x0A08)\n+ * Used to replace the local MIB of a given LLDP agent. e.g. DCBx\n+ */\n+struct ice_aqc_lldp_set_local_mib {\n+\tu8 type;\n+#define SET_LOCAL_MIB_TYPE_DCBX_M\t\tBIT(0)\n+#define SET_LOCAL_MIB_TYPE_LOCAL_MIB\t\t0\n+#define SET_LOCAL_MIB_TYPE_CEE_M\t\tBIT(1)\n+#define SET_LOCAL_MIB_TYPE_CEE_WILLING\t\t0\n+#define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING\tSET_LOCAL_MIB_TYPE_CEE_M\n+\tu8 reserved0;\n+\t__le16 length;\n+\tu8 reserved1[4];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n /* Stop/Start LLDP Agent (direct 0x0A09)\n * Used for stopping/starting specific LLDP agent. e.g. DCBx.\n * The same structure is used for the response, with the command field\n@@ -1481,11 +1524,13 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_get_topo get_topo;\n \t\tstruct ice_aqc_sched_elem_cmd sched_elem_cmd;\n \t\tstruct ice_aqc_query_txsched_res query_sched_res;\n+\t\tstruct ice_aqc_query_port_ets port_ets;\n \t\tstruct ice_aqc_nvm nvm;\n \t\tstruct ice_aqc_pf_vf_msg virt;\n \t\tstruct ice_aqc_lldp_get_mib lldp_get_mib;\n \t\tstruct ice_aqc_lldp_set_mib_change lldp_set_event;\n \t\tstruct ice_aqc_lldp_start lldp_start;\n+\t\tstruct ice_aqc_lldp_set_local_mib lldp_set_mib;\n \t\tstruct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;\n \t\tstruct ice_aqc_get_set_rss_lut get_set_rss_lut;\n \t\tstruct ice_aqc_get_set_rss_key get_set_rss_key;\n@@ -1573,6 +1618,7 @@ enum ice_adminq_opc {\n \tice_aqc_opc_get_sched_elems\t\t\t= 0x0404,\n \tice_aqc_opc_suspend_sched_elems\t\t\t= 0x0409,\n \tice_aqc_opc_resume_sched_elems\t\t\t= 0x040A,\n+\tice_aqc_opc_query_port_ets\t\t\t= 0x040E,\n \tice_aqc_opc_delete_sched_elems\t\t\t= 0x040F,\n \tice_aqc_opc_query_sched_res\t\t\t= 0x0412,\n \n@@ -1595,6 +1641,7 @@ enum ice_adminq_opc {\n \tice_aqc_opc_lldp_set_mib_change\t\t\t= 0x0A01,\n \tice_aqc_opc_lldp_start\t\t\t\t= 0x0A06,\n \tice_aqc_opc_get_cee_dcb_cfg\t\t\t= 0x0A07,\n+\tice_aqc_opc_lldp_set_local_mib\t\t\t= 0x0A08,\n \tice_aqc_opc_lldp_stop_start_specific_agent\t= 0x0A09,\n \n \t/* RSS commands */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex 3730daf1bc1a..2937c6be1aee 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -3106,3 +3106,28 @@ ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,\n \t\t/* to manage the potential roll-over */\n \t\t*cur_stat = (new_data + BIT_ULL(32)) - *prev_stat;\n }\n+\n+/**\n+ * ice_sched_query_elem - query element information from HW\n+ * @hw: pointer to the HW struct\n+ * @node_teid: node TEID to be queried\n+ * @buf: buffer to element information\n+ *\n+ * This function queries HW element information\n+ */\n+enum ice_status\n+ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,\n+\t\t struct ice_aqc_get_elem *buf)\n+{\n+\tu16 buf_size, num_elem_ret = 0;\n+\tenum ice_status status;\n+\n+\tbuf_size = sizeof(*buf);\n+\tmemset(buf, 0, buf_size);\n+\tbuf->generic[0].node_teid = cpu_to_le32(node_teid);\n+\tstatus = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,\n+\t\t\t\t\t NULL);\n+\tif (status || num_elem_ret != 1)\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"query element failed\\n\");\n+\treturn status;\n+}\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h\nindex fbdfdee353bc..faefc45e4a1e 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.h\n+++ b/drivers/net/ethernet/intel/ice/ice_common.h\n@@ -118,4 +118,7 @@ ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,\n void\n ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,\n \t\t u64 *prev_stat, u64 *cur_stat);\n+enum ice_status\n+ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,\n+\t\t struct ice_aqc_get_elem *buf);\n #endif /* _ICE_COMMON_H_ */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_dcb.c b/drivers/net/ethernet/intel/ice/ice_dcb.c\nindex b59c145fb958..1ad36b40974a 100644\n--- a/drivers/net/ethernet/intel/ice/ice_dcb.c\n+++ b/drivers/net/ethernet/intel/ice/ice_dcb.c\n@@ -98,6 +98,39 @@ enum ice_status ice_aq_start_lldp(struct ice_hw *hw, struct ice_sq_cd *cd)\n \treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n }\n \n+/**\n+ * ice_aq_set_lldp_mib - Set the LLDP MIB\n+ * @hw: pointer to the HW struct\n+ * @mib_type: Local, Remote or both Local and Remote MIBs\n+ * @buf: pointer to the caller-supplied buffer to store the MIB block\n+ * @buf_size: size of the buffer (in bytes)\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Set the LLDP MIB. (0x0A08)\n+ */\n+static enum ice_status\n+ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,\n+\t\t struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_lldp_set_local_mib *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.lldp_set_mib;\n+\n+\tif (buf_size == 0 || !buf)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);\n+\n+\tdesc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD);\n+\tdesc.datalen = cpu_to_le16(buf_size);\n+\n+\tcmd->type = mib_type;\n+\tcmd->length = cpu_to_le16(buf_size);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+}\n+\n /**\n * ice_get_dcbx_status\n * @hw: pointer to the HW struct\n@@ -902,3 +935,433 @@ enum ice_status ice_init_dcb(struct ice_hw *hw)\n \n \treturn ret;\n }\n+\n+/**\n+ * ice_add_ieee_ets_common_tlv\n+ * @buf: Data buffer to be populated with ice_dcb_ets_cfg data\n+ * @ets_cfg: Container for ice_dcb_ets_cfg data\n+ *\n+ * Populate the TLV buffer with ice_dcb_ets_cfg data\n+ */\n+static void\n+ice_add_ieee_ets_common_tlv(u8 *buf, struct ice_dcb_ets_cfg *ets_cfg)\n+{\n+\tu8 priority0, priority1;\n+\tu8 offset = 0;\n+\tint i;\n+\n+\t/* Priority Assignment Table (4 octets)\n+\t * Octets:| 1 | 2 | 3 | 4 |\n+\t * -----------------------------------------\n+\t * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|\n+\t * -----------------------------------------\n+\t * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|\n+\t * -----------------------------------------\n+\t */\n+\tfor (i = 0; i < ICE_MAX_TRAFFIC_CLASS / 2; i++) {\n+\t\tpriority0 = ets_cfg->prio_table[i * 2] & 0xF;\n+\t\tpriority1 = ets_cfg->prio_table[i * 2 + 1] & 0xF;\n+\t\tbuf[offset] = (priority0 << ICE_IEEE_ETS_PRIO_1_S) | priority1;\n+\t\toffset++;\n+\t}\n+\n+\t/* TC Bandwidth Table (8 octets)\n+\t * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |\n+\t * ---------------------------------\n+\t * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|\n+\t * ---------------------------------\n+\t *\n+\t * TSA Assignment Table (8 octets)\n+\t * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |\n+\t * ---------------------------------\n+\t * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|\n+\t * ---------------------------------\n+\t */\n+\tice_for_each_traffic_class(i) {\n+\t\tbuf[offset] = ets_cfg->tcbwtable[i];\n+\t\tbuf[ICE_MAX_TRAFFIC_CLASS + offset] = ets_cfg->tsatable[i];\n+\t\toffset++;\n+\t}\n+}\n+\n+/**\n+ * ice_add_ieee_ets_tlv - Prepare ETS TLV in IEEE format\n+ * @tlv: Fill the ETS config data in IEEE format\n+ * @dcbcfg: Local store which holds the DCB Config\n+ *\n+ * Prepare IEEE 802.1Qaz ETS CFG TLV\n+ */\n+static void\n+ice_add_ieee_ets_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)\n+{\n+\tstruct ice_dcb_ets_cfg *etscfg;\n+\tu8 *buf = tlv->tlvinfo;\n+\tu8 maxtcwilling = 0;\n+\tu32 ouisubtype;\n+\tu16 typelen;\n+\n+\ttypelen = ((ICE_TLV_TYPE_ORG << ICE_LLDP_TLV_TYPE_S) |\n+\t\t ICE_IEEE_ETS_TLV_LEN);\n+\ttlv->typelen = htons(typelen);\n+\n+\touisubtype = ((ICE_IEEE_8021QAZ_OUI << ICE_LLDP_TLV_OUI_S) |\n+\t\t ICE_IEEE_SUBTYPE_ETS_CFG);\n+\ttlv->ouisubtype = htonl(ouisubtype);\n+\n+\t/* First Octet post subtype\n+\t * --------------------------\n+\t * |will-|CBS | Re- | Max |\n+\t * |ing | |served| TCs |\n+\t * --------------------------\n+\t * |1bit | 1bit|3 bits|3bits|\n+\t */\n+\tetscfg = &dcbcfg->etscfg;\n+\tif (etscfg->willing)\n+\t\tmaxtcwilling = BIT(ICE_IEEE_ETS_WILLING_S);\n+\tmaxtcwilling |= etscfg->maxtcs & ICE_IEEE_ETS_MAXTC_M;\n+\tbuf[0] = maxtcwilling;\n+\n+\t/* Begin adding at Priority Assignment Table (offset 1 in buf) */\n+\tice_add_ieee_ets_common_tlv(&buf[1], etscfg);\n+}\n+\n+/**\n+ * ice_add_ieee_etsrec_tlv - Prepare ETS Recommended TLV in IEEE format\n+ * @tlv: Fill ETS Recommended TLV in IEEE format\n+ * @dcbcfg: Local store which holds the DCB Config\n+ *\n+ * Prepare IEEE 802.1Qaz ETS REC TLV\n+ */\n+static void\n+ice_add_ieee_etsrec_tlv(struct ice_lldp_org_tlv *tlv,\n+\t\t\tstruct ice_dcbx_cfg *dcbcfg)\n+{\n+\tstruct ice_dcb_ets_cfg *etsrec;\n+\tu8 *buf = tlv->tlvinfo;\n+\tu32 ouisubtype;\n+\tu16 typelen;\n+\n+\ttypelen = ((ICE_TLV_TYPE_ORG << ICE_LLDP_TLV_TYPE_S) |\n+\t\t ICE_IEEE_ETS_TLV_LEN);\n+\ttlv->typelen = htons(typelen);\n+\n+\touisubtype = ((ICE_IEEE_8021QAZ_OUI << ICE_LLDP_TLV_OUI_S) |\n+\t\t ICE_IEEE_SUBTYPE_ETS_REC);\n+\ttlv->ouisubtype = htonl(ouisubtype);\n+\n+\tetsrec = &dcbcfg->etsrec;\n+\n+\t/* First Octet is reserved */\n+\t/* Begin adding at Priority Assignment Table (offset 1 in buf) */\n+\tice_add_ieee_ets_common_tlv(&buf[1], etsrec);\n+}\n+\n+/**\n+ * ice_add_ieee_pfc_tlv - Prepare PFC TLV in IEEE format\n+ * @tlv: Fill PFC TLV in IEEE format\n+ * @dcbcfg: Local store which holds the PFC CFG data\n+ *\n+ * Prepare IEEE 802.1Qaz PFC CFG TLV\n+ */\n+static void\n+ice_add_ieee_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)\n+{\n+\tu8 *buf = tlv->tlvinfo;\n+\tu32 ouisubtype;\n+\tu16 typelen;\n+\n+\ttypelen = ((ICE_TLV_TYPE_ORG << ICE_LLDP_TLV_TYPE_S) |\n+\t\t ICE_IEEE_PFC_TLV_LEN);\n+\ttlv->typelen = htons(typelen);\n+\n+\touisubtype = ((ICE_IEEE_8021QAZ_OUI << ICE_LLDP_TLV_OUI_S) |\n+\t\t ICE_IEEE_SUBTYPE_PFC_CFG);\n+\ttlv->ouisubtype = htonl(ouisubtype);\n+\n+\t/* ----------------------------------------\n+\t * |will-|MBC | Re- | PFC | PFC Enable |\n+\t * |ing | |served| cap | |\n+\t * -----------------------------------------\n+\t * |1bit | 1bit|2 bits|4bits| 1 octet |\n+\t */\n+\tif (dcbcfg->pfc.willing)\n+\t\tbuf[0] = BIT(ICE_IEEE_PFC_WILLING_S);\n+\n+\tif (dcbcfg->pfc.mbc)\n+\t\tbuf[0] |= BIT(ICE_IEEE_PFC_MBC_S);\n+\n+\tbuf[0] |= dcbcfg->pfc.pfccap & 0xF;\n+\tbuf[1] = dcbcfg->pfc.pfcena;\n+}\n+\n+/**\n+ * ice_add_ieee_app_pri_tlv - Prepare APP TLV in IEEE format\n+ * @tlv: Fill APP TLV in IEEE format\n+ * @dcbcfg: Local store which holds the APP CFG data\n+ *\n+ * Prepare IEEE 802.1Qaz APP CFG TLV\n+ */\n+static void\n+ice_add_ieee_app_pri_tlv(struct ice_lldp_org_tlv *tlv,\n+\t\t\t struct ice_dcbx_cfg *dcbcfg)\n+{\n+\tu16 typelen, len, offset = 0;\n+\tu8 priority, selector, i = 0;\n+\tu8 *buf = tlv->tlvinfo;\n+\tu32 ouisubtype;\n+\n+\t/* No APP TLVs then just return */\n+\tif (dcbcfg->numapps == 0)\n+\t\treturn;\n+\touisubtype = ((ICE_IEEE_8021QAZ_OUI << ICE_LLDP_TLV_OUI_S) |\n+\t\t ICE_IEEE_SUBTYPE_APP_PRI);\n+\ttlv->ouisubtype = htonl(ouisubtype);\n+\n+\t/* Move offset to App Priority Table */\n+\toffset++;\n+\t/* Application Priority Table (3 octets)\n+\t * Octets:| 1 | 2 | 3 |\n+\t * -----------------------------------------\n+\t * |Priority|Rsrvd| Sel | Protocol ID |\n+\t * -----------------------------------------\n+\t * Bits:|23 21|20 19|18 16|15 0|\n+\t * -----------------------------------------\n+\t */\n+\twhile (i < dcbcfg->numapps) {\n+\t\tpriority = dcbcfg->app[i].priority & 0x7;\n+\t\tselector = dcbcfg->app[i].selector & 0x7;\n+\t\tbuf[offset] = (priority << ICE_IEEE_APP_PRIO_S) | selector;\n+\t\tbuf[offset + 1] = (dcbcfg->app[i].prot_id >> 0x8) & 0xFF;\n+\t\tbuf[offset + 2] = dcbcfg->app[i].prot_id & 0xFF;\n+\t\t/* Move to next app */\n+\t\toffset += 3;\n+\t\ti++;\n+\t\tif (i >= ICE_DCBX_MAX_APPS)\n+\t\t\tbreak;\n+\t}\n+\t/* len includes size of ouisubtype + 1 reserved + 3*numapps */\n+\tlen = sizeof(tlv->ouisubtype) + 1 + (i * 3);\n+\ttypelen = ((ICE_TLV_TYPE_ORG << ICE_LLDP_TLV_TYPE_S) | (len & 0x1FF));\n+\ttlv->typelen = htons(typelen);\n+}\n+\n+/**\n+ * ice_add_dcb_tlv - Add all IEEE TLVs\n+ * @tlv: Fill TLV data in IEEE format\n+ * @dcbcfg: Local store which holds the DCB Config\n+ * @tlvid: Type of IEEE TLV\n+ *\n+ * Add tlv information\n+ */\n+static void\n+ice_add_dcb_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg,\n+\t\tu16 tlvid)\n+{\n+\tswitch (tlvid) {\n+\tcase ICE_IEEE_TLV_ID_ETS_CFG:\n+\t\tice_add_ieee_ets_tlv(tlv, dcbcfg);\n+\t\tbreak;\n+\tcase ICE_IEEE_TLV_ID_ETS_REC:\n+\t\tice_add_ieee_etsrec_tlv(tlv, dcbcfg);\n+\t\tbreak;\n+\tcase ICE_IEEE_TLV_ID_PFC_CFG:\n+\t\tice_add_ieee_pfc_tlv(tlv, dcbcfg);\n+\t\tbreak;\n+\tcase ICE_IEEE_TLV_ID_APP_PRI:\n+\t\tice_add_ieee_app_pri_tlv(tlv, dcbcfg);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * ice_dcb_cfg_to_lldp - Convert DCB configuration to MIB format\n+ * @lldpmib: pointer to the HW struct\n+ * @miblen: length of LLDP MIB\n+ * @dcbcfg: Local store which holds the DCB Config\n+ *\n+ * Convert the DCB configuration to MIB format\n+ */\n+static void\n+ice_dcb_cfg_to_lldp(u8 *lldpmib, u16 *miblen, struct ice_dcbx_cfg *dcbcfg)\n+{\n+\tu16 len, offset = 0, tlvid = ICE_TLV_ID_START;\n+\tstruct ice_lldp_org_tlv *tlv;\n+\tu16 typelen;\n+\n+\ttlv = (struct ice_lldp_org_tlv *)lldpmib;\n+\twhile (1) {\n+\t\tice_add_dcb_tlv(tlv, dcbcfg, tlvid++);\n+\t\ttypelen = ntohs(tlv->typelen);\n+\t\tlen = (typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S;\n+\t\tif (len)\n+\t\t\toffset += len + 2;\n+\t\t/* END TLV or beyond LLDPDU size */\n+\t\tif (tlvid >= ICE_TLV_ID_END_OF_LLDPPDU ||\n+\t\t offset > ICE_LLDPDU_SIZE)\n+\t\t\tbreak;\n+\t\t/* Move to next TLV */\n+\t\tif (len)\n+\t\t\ttlv = (struct ice_lldp_org_tlv *)\n+\t\t\t\t((char *)tlv + sizeof(tlv->typelen) + len);\n+\t}\n+\t*miblen = offset;\n+}\n+\n+/**\n+ * ice_set_dcb_cfg - Set the local LLDP MIB to FW\n+ * @pi: port information structure\n+ *\n+ * Set DCB configuration to the Firmware\n+ */\n+enum ice_status ice_set_dcb_cfg(struct ice_port_info *pi)\n+{\n+\tu8 mib_type, *lldpmib = NULL;\n+\tstruct ice_dcbx_cfg *dcbcfg;\n+\tenum ice_status ret;\n+\tstruct ice_hw *hw;\n+\tu16 miblen;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\thw = pi->hw;\n+\n+\t/* update the HW local config */\n+\tdcbcfg = &pi->local_dcbx_cfg;\n+\t/* Allocate the LLDPDU */\n+\tlldpmib = devm_kzalloc(ice_hw_to_dev(hw), ICE_LLDPDU_SIZE, GFP_KERNEL);\n+\tif (!lldpmib)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tmib_type = SET_LOCAL_MIB_TYPE_LOCAL_MIB;\n+\tif (dcbcfg->app_mode == ICE_DCBX_APPS_NON_WILLING)\n+\t\tmib_type |= SET_LOCAL_MIB_TYPE_CEE_NON_WILLING;\n+\n+\tice_dcb_cfg_to_lldp(lldpmib, &miblen, dcbcfg);\n+\tret = ice_aq_set_lldp_mib(hw, mib_type, (void *)lldpmib, miblen,\n+\t\t\t\t NULL);\n+\n+\tdevm_kfree(ice_hw_to_dev(hw), lldpmib);\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * ice_aq_query_port_ets - query port ets configuration\n+ * @pi: port information structure\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * query current port ets configuration\n+ */\n+static enum ice_status\n+ice_aq_query_port_ets(struct ice_port_info *pi,\n+\t\t struct ice_aqc_port_ets_elem *buf, u16 buf_size,\n+\t\t struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_query_port_ets *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\tcmd = &desc.params.port_ets;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_port_ets);\n+\tcmd->port_teid = pi->root->info.node_teid;\n+\n+\tstatus = ice_aq_send_cmd(pi->hw, &desc, buf, buf_size, cd);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_update_port_tc_tree_cfg - update TC tree configuration\n+ * @pi: port information structure\n+ * @buf: pointer to buffer\n+ *\n+ * update the SW DB with the new TC changes\n+ */\n+static enum ice_status\n+ice_update_port_tc_tree_cfg(struct ice_port_info *pi,\n+\t\t\t struct ice_aqc_port_ets_elem *buf)\n+{\n+\tstruct ice_sched_node *node, *tc_node;\n+\tstruct ice_aqc_get_elem elem;\n+\tenum ice_status status = 0;\n+\tu32 teid1, teid2;\n+\tu8 i, j;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\t/* suspend the missing TC nodes */\n+\tfor (i = 0; i < pi->root->num_children; i++) {\n+\t\tteid1 = le32_to_cpu(pi->root->children[i]->info.node_teid);\n+\t\tice_for_each_traffic_class(j) {\n+\t\t\tteid2 = le32_to_cpu(buf->tc_node_teid[j]);\n+\t\t\tif (teid1 == teid2)\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tif (j < ICE_MAX_TRAFFIC_CLASS)\n+\t\t\tcontinue;\n+\t\t/* TC is missing */\n+\t\tpi->root->children[i]->in_use = false;\n+\t}\n+\t/* add the new TC nodes */\n+\tice_for_each_traffic_class(j) {\n+\t\tteid2 = le32_to_cpu(buf->tc_node_teid[j]);\n+\t\tif (teid2 == ICE_INVAL_TEID)\n+\t\t\tcontinue;\n+\t\t/* Is it already present in the tree ? */\n+\t\tfor (i = 0; i < pi->root->num_children; i++) {\n+\t\t\ttc_node = pi->root->children[i];\n+\t\t\tif (!tc_node)\n+\t\t\t\tcontinue;\n+\t\t\tteid1 = le32_to_cpu(tc_node->info.node_teid);\n+\t\t\tif (teid1 == teid2) {\n+\t\t\t\ttc_node->tc_num = j;\n+\t\t\t\ttc_node->in_use = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tif (i < pi->root->num_children)\n+\t\t\tcontinue;\n+\t\t/* new TC */\n+\t\tstatus = ice_sched_query_elem(pi->hw, teid2, &elem);\n+\t\tif (!status)\n+\t\t\tstatus = ice_sched_add_node(pi, 1, &elem.generic[0]);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t\t/* update the TC number */\n+\t\tnode = ice_sched_find_node_by_teid(pi->root, teid2);\n+\t\tif (node)\n+\t\t\tnode->tc_num = j;\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_query_port_ets - query port ets configuration\n+ * @pi: port information structure\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * query current port ets configuration and update the\n+ * SW DB with the TC changes\n+ */\n+enum ice_status\n+ice_query_port_ets(struct ice_port_info *pi,\n+\t\t struct ice_aqc_port_ets_elem *buf, u16 buf_size,\n+\t\t struct ice_sq_cd *cd)\n+{\n+\tenum ice_status status;\n+\n+\tmutex_lock(&pi->sched_lock);\n+\tstatus = ice_aq_query_port_ets(pi, buf, buf_size, cd);\n+\tif (!status)\n+\t\tstatus = ice_update_port_tc_tree_cfg(pi, buf);\n+\tmutex_unlock(&pi->sched_lock);\n+\treturn status;\n+}\ndiff --git a/drivers/net/ethernet/intel/ice/ice_dcb.h b/drivers/net/ethernet/intel/ice/ice_dcb.h\nindex f0f47567113b..068ec5b98708 100644\n--- a/drivers/net/ethernet/intel/ice/ice_dcb.h\n+++ b/drivers/net/ethernet/intel/ice/ice_dcb.h\n@@ -70,6 +70,18 @@\n #define ICE_IEEE_APP_PRIO_S\t\t5\n #define ICE_IEEE_APP_PRIO_M\t\t(0x7 << ICE_IEEE_APP_PRIO_S)\n \n+/* TLV definitions for preparing MIB */\n+#define ICE_IEEE_TLV_ID_ETS_CFG\t\t3\n+#define ICE_IEEE_TLV_ID_ETS_REC\t\t4\n+#define ICE_IEEE_TLV_ID_PFC_CFG\t\t5\n+#define ICE_IEEE_TLV_ID_APP_PRI\t\t6\n+#define ICE_TLV_ID_END_OF_LLDPPDU\t7\n+#define ICE_TLV_ID_START\t\tICE_IEEE_TLV_ID_ETS_CFG\n+\n+#define ICE_IEEE_ETS_TLV_LEN\t\t25\n+#define ICE_IEEE_PFC_TLV_LEN\t\t6\n+#define ICE_IEEE_APP_TLV_LEN\t\t11\n+\n /* IEEE 802.1AB LLDP Organization specific TLV */\n struct ice_lldp_org_tlv {\n \t__be16 typelen;\n@@ -108,7 +120,12 @@ struct ice_cee_app_prio {\n } __packed;\n \n u8 ice_get_dcbx_status(struct ice_hw *hw);\n+enum ice_status ice_set_dcb_cfg(struct ice_port_info *pi);\n enum ice_status ice_init_dcb(struct ice_hw *hw);\n+enum ice_status\n+ice_query_port_ets(struct ice_port_info *pi,\n+\t\t struct ice_aqc_port_ets_elem *buf, u16 buf_size,\n+\t\t struct ice_sq_cd *cmd_details);\n #ifdef CONFIG_DCB\n enum ice_status ice_aq_start_lldp(struct ice_hw *hw, struct ice_sq_cd *cd);\n enum ice_status\ndiff --git a/drivers/net/ethernet/intel/ice/ice_dcb_lib.c b/drivers/net/ethernet/intel/ice/ice_dcb_lib.c\nindex 9f7c3d4d3f01..102a9d7efb3c 100644\n--- a/drivers/net/ethernet/intel/ice/ice_dcb_lib.c\n+++ b/drivers/net/ethernet/intel/ice/ice_dcb_lib.c\n@@ -3,6 +3,189 @@\n \n #include \"ice_dcb_lib.h\"\n \n+/**\n+ * ice_dcb_get_ena_tc - return bitmap of enabled TCs\n+ * @dcbcfg: DCB config to evaluate for enabled TCs\n+ */\n+u8 ice_dcb_get_ena_tc(struct ice_dcbx_cfg *dcbcfg)\n+{\n+\tu8 i, num_tc, ena_tc = 1;\n+\n+\tnum_tc = ice_dcb_get_num_tc(dcbcfg);\n+\n+\tfor (i = 0; i < num_tc; i++)\n+\t\tena_tc |= BIT(i);\n+\n+\treturn ena_tc;\n+}\n+\n+/**\n+ * ice_dcb_get_num_tc - Get the number of TCs from DCBX config\n+ * @dcbcfg: config to retrieve number of TCs from\n+ */\n+u8 ice_dcb_get_num_tc(struct ice_dcbx_cfg *dcbcfg)\n+{\n+\tbool tc_unused = false;\n+\tu8 num_tc = 0;\n+\tu8 ret = 0;\n+\tint i;\n+\n+\t/* Scan the ETS Config Priority Table to find traffic classes\n+\t * enabled and create a bitmask of enabled TCs\n+\t */\n+\tfor (i = 0; i < CEE_DCBX_MAX_PRIO; i++)\n+\t\tnum_tc |= BIT(dcbcfg->etscfg.prio_table[i]);\n+\n+\t/* Scan bitmask for contiguous TCs starting with TC0 */\n+\tfor (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {\n+\t\tif (num_tc & BIT(i)) {\n+\t\t\tif (!tc_unused) {\n+\t\t\t\tret++;\n+\t\t\t} else {\n+\t\t\t\tpr_err(\"Non-contiguous TCs - Disabling DCB\\n\");\n+\t\t\t\treturn 1;\n+\t\t\t}\n+\t\t} else {\n+\t\t\ttc_unused = true;\n+\t\t}\n+\t}\n+\n+\t/* There is always at least 1 TC */\n+\tif (!ret)\n+\t\tret = 1;\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * ice_pf_dcb_recfg - Reconfigure all VEBs and VSIs\n+ * @pf: pointer to the PF struct\n+ *\n+ * Assumed caller has already disabled all VSIs before\n+ * calling this function. Reconfiguring DCB based on\n+ * local_dcbx_cfg.\n+ */\n+static void ice_pf_dcb_recfg(struct ice_pf *pf)\n+{\n+\tstruct ice_dcbx_cfg *dcbcfg = &pf->hw.port_info->local_dcbx_cfg;\n+\tu8 tc_map = 0;\n+\tint v, ret;\n+\n+\t/* Update each VSI */\n+\tice_for_each_vsi(pf, v) {\n+\t\tif (!pf->vsi[v])\n+\t\t\tcontinue;\n+\n+\t\tif (pf->vsi[v]->type == ICE_VSI_PF)\n+\t\t\ttc_map = ice_dcb_get_ena_tc(dcbcfg);\n+\t\telse\n+\t\t\ttc_map = ICE_DFLT_TRAFFIC_CLASS;\n+\n+\t\tret = ice_vsi_cfg_tc(pf->vsi[v], tc_map);\n+\t\tif (ret)\n+\t\t\tdev_err(&pf->pdev->dev,\n+\t\t\t\t\"Failed to config TC for VSI index: %d\\n\",\n+\t\t\t\tpf->vsi[v]->idx);\n+\t\telse\n+\t\t\tice_vsi_map_rings_to_vectors(pf->vsi[v]);\n+\t}\n+}\n+\n+/**\n+ * ice_pf_dcb_cfg - Apply new DCB configuration\n+ * @pf: pointer to the PF struct\n+ * @new_cfg: DCBX config to apply\n+ */\n+static int ice_pf_dcb_cfg(struct ice_pf *pf, struct ice_dcbx_cfg *new_cfg)\n+{\n+\tstruct ice_dcbx_cfg *old_cfg, *curr_cfg;\n+\tstruct ice_aqc_port_ets_elem buf = { 0 };\n+\tint ret = 0;\n+\n+\tcurr_cfg = &pf->hw.port_info->local_dcbx_cfg;\n+\n+\t/* Enable DCB tagging only when more than one TC */\n+\tif (ice_dcb_get_num_tc(new_cfg) > 1) {\n+\t\tdev_dbg(&pf->pdev->dev, \"DCB tagging enabled (num TC > 1)\\n\");\n+\t\tset_bit(ICE_FLAG_DCB_ENA, pf->flags);\n+\t} else {\n+\t\tdev_dbg(&pf->pdev->dev, \"DCB tagging disabled (num TC = 1)\\n\");\n+\t\tclear_bit(ICE_FLAG_DCB_ENA, pf->flags);\n+\t}\n+\n+\tif (!memcmp(new_cfg, curr_cfg, sizeof(*new_cfg))) {\n+\t\tdev_dbg(&pf->pdev->dev, \"No change in DCB config required\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* Store old config in case FW config fails */\n+\told_cfg = devm_kzalloc(&pf->pdev->dev, sizeof(*old_cfg), GFP_KERNEL);\n+\tmemcpy(old_cfg, curr_cfg, sizeof(*old_cfg));\n+\n+\t/* avoid race conditions by holding the lock while disabling and\n+\t * re-enabling the VSI\n+\t */\n+\trtnl_lock();\n+\tice_pf_dis_all_vsi(pf, true);\n+\n+\tmemcpy(curr_cfg, new_cfg, sizeof(*curr_cfg));\n+\tmemcpy(&curr_cfg->etsrec, &curr_cfg->etscfg, sizeof(curr_cfg->etsrec));\n+\n+\t/* Only send new config to HW if we are in SW LLDP mode. Otherwise,\n+\t * the new config came from the HW in the first place.\n+\t */\n+\tif (pf->hw.port_info->is_sw_lldp) {\n+\t\tret = ice_set_dcb_cfg(pf->hw.port_info);\n+\t\tif (ret) {\n+\t\t\tdev_err(&pf->pdev->dev, \"Set DCB Config failed\\n\");\n+\t\t\t/* Restore previous settings to local config */\n+\t\t\tmemcpy(curr_cfg, old_cfg, sizeof(*curr_cfg));\n+\t\t\tgoto out;\n+\t\t}\n+\t}\n+\n+\tret = ice_query_port_ets(pf->hw.port_info, &buf, sizeof(buf), NULL);\n+\tif (ret) {\n+\t\tdev_err(&pf->pdev->dev, \"Query Port ETS failed\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tice_pf_dcb_recfg(pf);\n+\n+out:\n+\tice_pf_ena_all_vsi(pf, true);\n+\trtnl_unlock();\n+\tdevm_kfree(&pf->pdev->dev, old_cfg);\n+\treturn ret;\n+}\n+\n+/**\n+ * ice_dcb_init_cfg - set the initial DCB config in SW\n+ * @pf: pf to apply config to\n+ */\n+static int ice_dcb_init_cfg(struct ice_pf *pf)\n+{\n+\tstruct ice_dcbx_cfg *newcfg;\n+\tstruct ice_port_info *pi;\n+\tint ret = 0;\n+\n+\tpi = pf->hw.port_info;\n+\tnewcfg = devm_kzalloc(&pf->pdev->dev, sizeof(*newcfg), GFP_KERNEL);\n+\tif (!newcfg)\n+\t\treturn -ENOMEM;\n+\n+\tmemcpy(newcfg, &pi->local_dcbx_cfg, sizeof(*newcfg));\n+\tmemset(&pi->local_dcbx_cfg, 0, sizeof(*newcfg));\n+\n+\tdev_info(&pf->pdev->dev, \"Configuring initial DCB values\\n\");\n+\tif (ice_pf_dcb_cfg(pf, newcfg))\n+\t\tret = -EINVAL;\n+\n+\tdevm_kfree(&pf->pdev->dev, newcfg);\n+\n+\treturn ret;\n+}\n+\n /**\n * ice_init_pf_dcb - initialize DCB for a PF\n * @pf: pf to initiialize DCB for\n@@ -12,6 +195,7 @@ int ice_init_pf_dcb(struct ice_pf *pf)\n \tstruct device *dev = &pf->pdev->dev;\n \tstruct ice_port_info *port_info;\n \tstruct ice_hw *hw = &pf->hw;\n+\tint err;\n \n \tport_info = hw->port_info;\n \n@@ -38,5 +222,23 @@ int ice_init_pf_dcb(struct ice_pf *pf)\n \t\tice_aq_start_stop_dcbx(hw, true, &dcbx_status, NULL);\n \t}\n \n-\treturn ice_init_dcb(hw);\n+\terr = ice_init_dcb(hw);\n+\tif (err)\n+\t\tgoto dcb_init_err;\n+\n+\t/* DCBX in FW and LLDP enabled in FW */\n+\tpf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED | DCB_CAP_DCBX_VER_IEEE;\n+\n+\tset_bit(ICE_FLAG_DCB_CAPABLE, pf->flags);\n+\n+\terr = ice_dcb_init_cfg(pf);\n+\tif (err)\n+\t\tgoto dcb_init_err;\n+\n+\tdev_info(&pf->pdev->dev, \"DCBX offload supported\\n\");\n+\treturn err;\n+\n+dcb_init_err:\n+\tdev_err(dev, \"DCB init failed\\n\");\n+\treturn err;\n }\ndiff --git a/drivers/net/ethernet/intel/ice/ice_dcb_lib.h b/drivers/net/ethernet/intel/ice/ice_dcb_lib.h\nindex 592811b7c61a..1c60bf4ca593 100644\n--- a/drivers/net/ethernet/intel/ice/ice_dcb_lib.h\n+++ b/drivers/net/ethernet/intel/ice/ice_dcb_lib.h\n@@ -8,12 +8,25 @@\n #include \"ice_lib.h\"\n \n #ifdef CONFIG_DCB\n+u8 ice_dcb_get_ena_tc(struct ice_dcbx_cfg *dcbcfg);\n+u8 ice_dcb_get_num_tc(struct ice_dcbx_cfg *dcbcfg);\n int ice_init_pf_dcb(struct ice_pf *pf);\n #else\n+static inline u8 ice_dcb_get_ena_tc(struct ice_dcbx_cfg __always_unused *dcbcfg)\n+{\n+\treturn ICE_DFLT_TRAFFIC_CLASS;\n+}\n+\n+static inline u8 ice_dcb_get_num_tc(struct ice_dcbx_cfg __always_unused *dcbcfg)\n+{\n+\treturn 1;\n+}\n+\n static inline int ice_init_pf_dcb(struct ice_pf *pf)\n {\n \tdev_dbg(&pf->pdev->dev, \"DCB not supported\\n\");\n \treturn -EOPNOTSUPP;\n }\n+\n #endif /* CONFIG_DCB */\n #endif /* _ICE_DCB_LIB_H_ */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c\nindex d24da511b775..f3574daa147c 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lib.c\n+++ b/drivers/net/ethernet/intel/ice/ice_lib.c\n@@ -3,6 +3,7 @@\n \n #include \"ice.h\"\n #include \"ice_lib.h\"\n+#include \"ice_dcb_lib.h\"\n \n /**\n * ice_setup_rx_ctx - Configure a receive ring context\n@@ -1301,7 +1302,11 @@ static int ice_vsi_alloc_rings(struct ice_vsi *vsi)\n * through the MSI-X enabling code. On a constrained vector budget, we map Tx\n * and Rx rings to the vector as \"efficiently\" as possible.\n */\n+#ifdef CONFIG_DCB\n+void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)\n+#else\n static void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)\n+#endif /* CONFIG_DCB */\n {\n \tint q_vectors = vsi->num_q_vectors;\n \tint tx_rings_rem, rx_rings_rem;\n@@ -2172,6 +2177,14 @@ int ice_cfg_vlan_pruning(struct ice_vsi *vsi, bool ena, bool vlan_promisc)\n \treturn -EIO;\n }\n \n+static void ice_vsi_set_tc_cfg(struct ice_vsi *vsi)\n+{\n+\tstruct ice_dcbx_cfg *cfg = &vsi->port_info->local_dcbx_cfg;\n+\n+\tvsi->tc_cfg.ena_tc = ice_dcb_get_ena_tc(cfg);\n+\tvsi->tc_cfg.numtc = ice_dcb_get_num_tc(cfg);\n+}\n+\n /**\n * ice_vsi_setup - Set up a VSI by a given type\n * @pf: board private structure\n@@ -2815,3 +2828,125 @@ bool ice_is_reset_in_progress(unsigned long *state)\n \t test_bit(__ICE_CORER_REQ, state) ||\n \t test_bit(__ICE_GLOBR_REQ, state);\n }\n+\n+#ifdef CONFIG_DCB\n+/**\n+ * ice_vsi_update_q_map - update our copy of the VSI info with new queue map\n+ * @vsi: VSI being configured\n+ * @ctx: the context buffer returned from AQ VSI update command\n+ */\n+static void ice_vsi_update_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctx)\n+{\n+\tvsi->info.mapping_flags = ctx->info.mapping_flags;\n+\tmemcpy(&vsi->info.q_mapping, &ctx->info.q_mapping,\n+\t sizeof(vsi->info.q_mapping));\n+\tmemcpy(&vsi->info.tc_mapping, ctx->info.tc_mapping,\n+\t sizeof(vsi->info.tc_mapping));\n+}\n+\n+/**\n+ * ice_vsi_cfg_netdev_tc - Setup the netdev TC configuration\n+ * @vsi: the VSI being configured\n+ * @ena_tc: TC map to be enabled\n+ */\n+static void ice_vsi_cfg_netdev_tc(struct ice_vsi *vsi, u8 ena_tc)\n+{\n+\tstruct net_device *netdev = vsi->netdev;\n+\tstruct ice_pf *pf = vsi->back;\n+\tstruct ice_dcbx_cfg *dcbcfg;\n+\tu8 netdev_tc;\n+\tint i;\n+\n+\tif (!netdev)\n+\t\treturn;\n+\n+\tif (!ena_tc) {\n+\t\tnetdev_reset_tc(netdev);\n+\t\treturn;\n+\t}\n+\n+\tif (netdev_set_num_tc(netdev, vsi->tc_cfg.numtc))\n+\t\treturn;\n+\n+\tdcbcfg = &pf->hw.port_info->local_dcbx_cfg;\n+\n+\tice_for_each_traffic_class(i)\n+\t\tif (vsi->tc_cfg.ena_tc & BIT(i))\n+\t\t\tnetdev_set_tc_queue(netdev,\n+\t\t\t\t\t vsi->tc_cfg.tc_info[i].netdev_tc,\n+\t\t\t\t\t vsi->tc_cfg.tc_info[i].qcount_tx,\n+\t\t\t\t\t vsi->tc_cfg.tc_info[i].qoffset);\n+\n+\tfor (i = 0; i < ICE_MAX_USER_PRIORITY; i++) {\n+\t\tu8 ets_tc = dcbcfg->etscfg.prio_table[i];\n+\n+\t\t/* Get the mapped netdev TC# for the UP */\n+\t\tnetdev_tc = vsi->tc_cfg.tc_info[ets_tc].netdev_tc;\n+\t\tnetdev_set_prio_tc_map(netdev, i, netdev_tc);\n+\t}\n+}\n+\n+/**\n+ * ice_vsi_cfg_tc - Configure VSI Tx Sched for given TC map\n+ * @vsi: VSI to be configured\n+ * @ena_tc: TC bitmap\n+ *\n+ * VSI queues expected to be quiesced before calling this function\n+ */\n+int ice_vsi_cfg_tc(struct ice_vsi *vsi, u8 ena_tc)\n+{\n+\tu16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };\n+\tstruct ice_vsi_ctx *ctx;\n+\tstruct ice_pf *pf = vsi->back;\n+\tenum ice_status status;\n+\tint i, ret = 0;\n+\tu8 num_tc = 0;\n+\n+\tice_for_each_traffic_class(i) {\n+\t\t/* build bitmap of enabled TCs */\n+\t\tif (ena_tc & BIT(i))\n+\t\t\tnum_tc++;\n+\t\t/* populate max_txqs per TC */\n+\t\tmax_txqs[i] = pf->num_lan_tx;\n+\t}\n+\n+\tvsi->tc_cfg.ena_tc = ena_tc;\n+\tvsi->tc_cfg.numtc = num_tc;\n+\n+\tctx = devm_kzalloc(&pf->pdev->dev, sizeof(*ctx), GFP_KERNEL);\n+\tif (!ctx)\n+\t\treturn -ENOMEM;\n+\n+\tctx->vf_num = 0;\n+\tctx->info = vsi->info;\n+\n+\tice_vsi_setup_q_map(vsi, ctx);\n+\n+\t/* must to indicate which section of VSI context are being modified */\n+\tctx->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);\n+\tstatus = ice_update_vsi(&pf->hw, vsi->idx, ctx, NULL);\n+\tif (status) {\n+\t\tdev_info(&pf->pdev->dev, \"Failed VSI Update\\n\");\n+\t\tret = -EIO;\n+\t\tgoto out;\n+\t}\n+\n+\tstatus = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,\n+\t\t\t\t max_txqs);\n+\n+\tif (status) {\n+\t\tdev_err(&pf->pdev->dev,\n+\t\t\t\"VSI %d failed TC config, error %d\\n\",\n+\t\t\tvsi->vsi_num, status);\n+\t\tret = -EIO;\n+\t\tgoto out;\n+\t}\n+\tice_vsi_update_q_map(vsi, ctx);\n+\tvsi->info.valid_sections = 0;\n+\n+\tice_vsi_cfg_netdev_tc(vsi, ena_tc);\n+out:\n+\tdevm_kfree(&pf->pdev->dev, ctx);\n+\treturn ret;\n+}\n+#endif /* CONFIG_DCB */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_lib.h b/drivers/net/ethernet/intel/ice/ice_lib.h\nindex 519ef59e9e43..714ace077796 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lib.h\n+++ b/drivers/net/ethernet/intel/ice/ice_lib.h\n@@ -41,6 +41,10 @@ void ice_vsi_delete(struct ice_vsi *vsi);\n \n int ice_vsi_clear(struct ice_vsi *vsi);\n \n+#ifdef CONFIG_DCB\n+int ice_vsi_cfg_tc(struct ice_vsi *vsi, u8 ena_tc);\n+#endif /* CONFIG_DCB */\n+\n struct ice_vsi *\n ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,\n \t enum ice_vsi_type type, u16 vf_id);\n@@ -62,6 +66,10 @@ void ice_vsi_free_q_vectors(struct ice_vsi *vsi);\n \n void ice_vsi_put_qs(struct ice_vsi *vsi);\n \n+#ifdef CONFIG_DCB\n+void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi);\n+#endif /* CONFIG_DCB */\n+\n void ice_vsi_dis_irq(struct ice_vsi *vsi);\n \n void ice_vsi_free_irq(struct ice_vsi *vsi);\ndiff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c\nindex 72fc6e702ab5..158339769097 100644\n--- a/drivers/net/ethernet/intel/ice/ice_main.c\n+++ b/drivers/net/ethernet/intel/ice/ice_main.c\n@@ -31,7 +31,6 @@ MODULE_PARM_DESC(debug, \"netif level (0=none,...,16=all)\");\n static struct workqueue_struct *ice_wq;\n static const struct net_device_ops ice_netdev_ops;\n \n-static void ice_pf_dis_all_vsi(struct ice_pf *pf);\n static void ice_rebuild(struct ice_pf *pf);\n \n static void ice_vsi_release_all(struct ice_pf *pf);\n@@ -397,6 +396,51 @@ static void ice_sync_fltr_subtask(struct ice_pf *pf)\n \t\t}\n }\n \n+/**\n+ * ice_dis_vsi - pause a VSI\n+ * @vsi: the VSI being paused\n+ * @locked: is the rtnl_lock already held\n+ */\n+static void ice_dis_vsi(struct ice_vsi *vsi, bool locked)\n+{\n+\tif (test_bit(__ICE_DOWN, vsi->state))\n+\t\treturn;\n+\n+\tset_bit(__ICE_NEEDS_RESTART, vsi->state);\n+\n+\tif (vsi->type == ICE_VSI_PF && vsi->netdev) {\n+\t\tif (netif_running(vsi->netdev)) {\n+\t\t\tif (!locked) {\n+\t\t\t\trtnl_lock();\n+\t\t\t\tvsi->netdev->netdev_ops->ndo_stop(vsi->netdev);\n+\t\t\t\trtnl_unlock();\n+\t\t\t} else {\n+\t\t\t\tvsi->netdev->netdev_ops->ndo_stop(vsi->netdev);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tice_vsi_close(vsi);\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * ice_pf_dis_all_vsi - Pause all VSIs on a PF\n+ * @pf: the PF\n+ * @locked: is the rtnl_lock already held\n+ */\n+#ifdef CONFIG_DCB\n+void ice_pf_dis_all_vsi(struct ice_pf *pf, bool locked)\n+#else\n+static void ice_pf_dis_all_vsi(struct ice_pf *pf, bool locked)\n+#endif /* CONFIG_DCB */\n+{\n+\tint v;\n+\n+\tice_for_each_vsi(pf, v)\n+\t\tif (pf->vsi[v])\n+\t\t\tice_dis_vsi(pf->vsi[v], locked);\n+}\n+\n /**\n * ice_prepare_for_reset - prep for the core to reset\n * @pf: board private structure\n@@ -417,7 +461,7 @@ ice_prepare_for_reset(struct ice_pf *pf)\n \t\tice_vc_notify_reset(pf);\n \n \t/* disable the VSIs and their queues that are not already DOWN */\n-\tice_pf_dis_all_vsi(pf);\n+\tice_pf_dis_all_vsi(pf, false);\n \n \tif (hw->port_info)\n \t\tice_sched_clear_port(hw->port_info);\n@@ -3581,46 +3625,30 @@ static void ice_vsi_release_all(struct ice_pf *pf)\n }\n \n /**\n- * ice_dis_vsi - pause a VSI\n- * @vsi: the VSI being paused\n+ * ice_ena_vsi - resume a VSI\n+ * @vsi: the VSI being resume\n * @locked: is the rtnl_lock already held\n */\n-static void ice_dis_vsi(struct ice_vsi *vsi, bool locked)\n+static int ice_ena_vsi(struct ice_vsi *vsi, bool locked)\n {\n-\tif (test_bit(__ICE_DOWN, vsi->state))\n-\t\treturn;\n+\tint err = 0;\n \n-\tset_bit(__ICE_NEEDS_RESTART, vsi->state);\n+\tif (!test_bit(__ICE_NEEDS_RESTART, vsi->state))\n+\t\treturn err;\n+\n+\tclear_bit(__ICE_NEEDS_RESTART, vsi->state);\n+\n+\tif (vsi->netdev && vsi->type == ICE_VSI_PF) {\n+\t\tstruct net_device *netd = vsi->netdev;\n \n-\tif (vsi->type == ICE_VSI_PF && vsi->netdev) {\n \t\tif (netif_running(vsi->netdev)) {\n-\t\t\tif (!locked) {\n+\t\t\tif (locked) {\n+\t\t\t\terr = netd->netdev_ops->ndo_open(netd);\n+\t\t\t} else {\n \t\t\t\trtnl_lock();\n-\t\t\t\tvsi->netdev->netdev_ops->ndo_stop(vsi->netdev);\n+\t\t\t\terr = netd->netdev_ops->ndo_open(netd);\n \t\t\t\trtnl_unlock();\n-\t\t\t} else {\n-\t\t\t\tvsi->netdev->netdev_ops->ndo_stop(vsi->netdev);\n \t\t\t}\n-\t\t} else {\n-\t\t\tice_vsi_close(vsi);\n-\t\t}\n-\t}\n-}\n-\n-/**\n- * ice_ena_vsi - resume a VSI\n- * @vsi: the VSI being resume\n- */\n-static int ice_ena_vsi(struct ice_vsi *vsi)\n-{\n-\tint err = 0;\n-\n-\tif (test_and_clear_bit(__ICE_NEEDS_RESTART, vsi->state) &&\n-\t vsi->netdev) {\n-\t\tif (netif_running(vsi->netdev)) {\n-\t\t\trtnl_lock();\n-\t\t\terr = vsi->netdev->netdev_ops->ndo_open(vsi->netdev);\n-\t\t\trtnl_unlock();\n \t\t} else {\n \t\t\terr = ice_vsi_open(vsi);\n \t\t}\n@@ -3629,30 +3657,22 @@ static int ice_ena_vsi(struct ice_vsi *vsi)\n \treturn err;\n }\n \n-/**\n- * ice_pf_dis_all_vsi - Pause all VSIs on a PF\n- * @pf: the PF\n- */\n-static void ice_pf_dis_all_vsi(struct ice_pf *pf)\n-{\n-\tint v;\n-\n-\tice_for_each_vsi(pf, v)\n-\t\tif (pf->vsi[v])\n-\t\t\tice_dis_vsi(pf->vsi[v], false);\n-}\n-\n /**\n * ice_pf_ena_all_vsi - Resume all VSIs on a PF\n * @pf: the PF\n+ * @locked: is the rtnl_lock already held\n */\n-static int ice_pf_ena_all_vsi(struct ice_pf *pf)\n+#ifdef CONFIG_DCB\n+int ice_pf_ena_all_vsi(struct ice_pf *pf, bool locked)\n+#else\n+static int ice_pf_ena_all_vsi(struct ice_pf *pf, bool locked)\n+#endif /* CONFIG_DCB */\n {\n \tint v;\n \n \tice_for_each_vsi(pf, v)\n \t\tif (pf->vsi[v])\n-\t\t\tif (ice_ena_vsi(pf->vsi[v]))\n+\t\t\tif (ice_ena_vsi(pf->vsi[v], locked))\n \t\t\t\treturn -EIO;\n \n \treturn 0;\n@@ -3800,7 +3820,7 @@ static void ice_rebuild(struct ice_pf *pf)\n \t}\n \n \t/* restart the VSIs that were rebuilt and running before the reset */\n-\terr = ice_pf_ena_all_vsi(pf);\n+\terr = ice_pf_ena_all_vsi(pf, false);\n \tif (err) {\n \t\tdev_err(&pf->pdev->dev, \"error enabling VSIs\\n\");\n \t\t/* no need to disable VSIs in tear down path in ice_rebuild()\ndiff --git a/drivers/net/ethernet/intel/ice/ice_sched.c b/drivers/net/ethernet/intel/ice/ice_sched.c\nindex 3d1c941a938e..124feaf0e730 100644\n--- a/drivers/net/ethernet/intel/ice/ice_sched.c\n+++ b/drivers/net/ethernet/intel/ice/ice_sched.c\n@@ -127,7 +127,7 @@ ice_aqc_send_sched_elem_cmd(struct ice_hw *hw, enum ice_adminq_opc cmd_opc,\n *\n * Query scheduling elements (0x0404)\n */\n-static enum ice_status\n+enum ice_status\n ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,\n \t\t\t struct ice_aqc_get_elem *buf, u16 buf_size,\n \t\t\t u16 *elems_ret, struct ice_sq_cd *cd)\n@@ -137,31 +137,6 @@ ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,\n \t\t\t\t\t elems_ret, cd);\n }\n \n-/**\n- * ice_sched_query_elem - query element information from HW\n- * @hw: pointer to the HW struct\n- * @node_teid: node TEID to be queried\n- * @buf: buffer to element information\n- *\n- * This function queries HW element information\n- */\n-static enum ice_status\n-ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,\n-\t\t struct ice_aqc_get_elem *buf)\n-{\n-\tu16 buf_size, num_elem_ret = 0;\n-\tenum ice_status status;\n-\n-\tbuf_size = sizeof(*buf);\n-\tmemset(buf, 0, buf_size);\n-\tbuf->generic[0].node_teid = cpu_to_le32(node_teid);\n-\tstatus = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,\n-\t\t\t\t\t NULL);\n-\tif (status || num_elem_ret != 1)\n-\t\tice_debug(hw, ICE_DBG_SCHED, \"query element failed\\n\");\n-\treturn status;\n-}\n-\n /**\n * ice_sched_add_node - Insert the Tx scheduler node in SW DB\n * @pi: port information structure\ndiff --git a/drivers/net/ethernet/intel/ice/ice_sched.h b/drivers/net/ethernet/intel/ice/ice_sched.h\nindex bee8221ad146..3902a8ad3025 100644\n--- a/drivers/net/ethernet/intel/ice/ice_sched.h\n+++ b/drivers/net/ethernet/intel/ice/ice_sched.h\n@@ -24,6 +24,10 @@ struct ice_sched_agg_info {\n };\n \n /* FW AQ command calls */\n+enum ice_status\n+ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,\n+\t\t\t struct ice_aqc_get_elem *buf, u16 buf_size,\n+\t\t\t u16 *elems_ret, struct ice_sq_cd *cd);\n enum ice_status ice_sched_init_port(struct ice_port_info *pi);\n enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw);\n void ice_sched_clear_port(struct ice_port_info *pi);\ndiff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h\nindex d276e9a952db..c4cdfb2e0c4b 100644\n--- a/drivers/net/ethernet/intel/ice/ice_type.h\n+++ b/drivers/net/ethernet/intel/ice/ice_type.h\n@@ -215,6 +215,8 @@ struct ice_nvm_info {\n #define ice_for_each_traffic_class(_i)\t\\\n \tfor ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)\n \n+#define ICE_INVAL_TEID 0xFFFFFFFF\n+\n struct ice_sched_node {\n \tstruct ice_sched_node *parent;\n \tstruct ice_sched_node *sibling; /* next sibling in the same layer */\n", "prefixes": [ "S16", "03/11" ] }