Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1048242/?format=api
{ "id": 1048242, "url": "http://patchwork.ozlabs.org/api/patches/1048242/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190226111834.26677-2-laurentiu.tudor@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190226111834.26677-2-laurentiu.tudor@nxp.com>", "list_archive_url": null, "date": "2019-02-26T11:18:33", "name": "[U-Boot,v2,2/3] armv8: fsl-layerscape: fix SEC QI ICID setup", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "1635d5c90bc8de5eb439b603b2f93ccaf2ae1926", "submitter": { "id": 71003, "url": "http://patchwork.ozlabs.org/api/people/71003/?format=api", "name": "Laurentiu Tudor", "email": "laurentiu.tudor@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190226111834.26677-2-laurentiu.tudor@nxp.com/mbox/", "series": [ { "id": 94219, "url": "http://patchwork.ozlabs.org/api/series/94219/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=94219", "date": "2019-02-26T11:18:32", "name": "[U-Boot,v2,1/3] fsl_sec: fix register layout on Layerscape architectures", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/94219/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1048242/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1048242/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 447xD32mzRz9sBL\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 26 Feb 2019 22:19:31 +1100 (AEDT)", "by lists.denx.de (Postfix, from userid 105)\n\tid 1012DC21DAF; Tue, 26 Feb 2019 11:18:54 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 45062C21D65;\n\tTue, 26 Feb 2019 11:18:39 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid D423FC21C2F; Tue, 26 Feb 2019 11:18:37 +0000 (UTC)", "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n\tby lists.denx.de (Postfix) with ESMTPS id 86F09C21C38\n\tfor <u-boot@lists.denx.de>; Tue, 26 Feb 2019 11:18:37 +0000 (UTC)", "from inva020.nxp.com (localhost [127.0.0.1])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id EFA8D1A02F5;\n\tTue, 26 Feb 2019 12:18:36 +0100 (CET)", "from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com\n\t[134.27.226.22])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E3ADF1A02F0;\n\tTue, 26 Feb 2019 12:18:36 +0100 (CET)", "from fsr-ub1864-101.ea.freescale.net\n\t(fsr-ub1864-101.ea.freescale.net [10.171.82.46])\n\tby inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 91DCA205EB;\n\tTue, 26 Feb 2019 12:18:36 +0100 (CET)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "laurentiu.tudor@nxp.com", "To": "u-boot@lists.denx.de,\n\tprabhakar.kushwaha@nxp.com", "Date": "Tue, 26 Feb 2019 13:18:33 +0200", "Message-Id": "<20190226111834.26677-2-laurentiu.tudor@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190226111834.26677-1-laurentiu.tudor@nxp.com>", "References": "<20190226111834.26677-1-laurentiu.tudor@nxp.com>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Subject": "[U-Boot] [PATCH v2 2/3] armv8: fsl-layerscape: fix SEC QI ICID setup", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Laurentiu Tudor <laurentiu.tudor@nxp.com>\n\nThe SEC QI ICID setup in the QIIC_LS register is actually an offset\nthat is being added to the ICID coming from the qman portal. Setting\nit with a non-zero value breaks SMMU setup as the resulting ICID is\nnot known. On top of that, the SEC QI ICID must match the qman portal\nICIDs in order to share the isolation context.\n\nSigned-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>\nReviewed-by: Horia Geanta <horia.geanta@nxp.com>\nReviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>\n---\nv2:\n - added Reviewed-by tags\n\n arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +-\n arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +-\n arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 3 +--\n 3 files changed, 3 insertions(+), 4 deletions(-)", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c\nindex 0e8649427e..3bd993bebf 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c\n@@ -43,7 +43,7 @@ struct icid_id_table icid_tbl[] = {\n \tSET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),\n \tSET_QE_ICID(FSL_QE_STREAM_ID),\n #ifdef CONFIG_FSL_CAAM\n-\tSET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),\n+\tSET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),\n \tSET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),\n \tSET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),\n \tSET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c\nindex 2da9adab5b..abd847b5be 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c\n@@ -41,7 +41,7 @@ struct icid_id_table icid_tbl[] = {\n \tSET_ETR_ICID(FSL_ETR_STREAM_ID),\n \tSET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),\n #ifdef CONFIG_FSL_CAAM\n-\tSET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),\n+\tSET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),\n \tSET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),\n \tSET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),\n \tSET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h\nindex f375fe7115..e7a8801262 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h\n@@ -93,8 +93,7 @@ void fdt_fixup_icid(void *blob);\n \n #define SET_SEC_QI_ICID(streamid) \\\n \tSET_ICID_ENTRY(\"fsl,sec-v4.0\", streamid, \\\n-\t\t(((streamid) << 16) | (streamid)), \\\n-\t\toffsetof(ccsr_sec_t, qilcr_ls) + \\\n+\t\t0, offsetof(ccsr_sec_t, qilcr_ls) + \\\n \t\tCONFIG_SYS_FSL_SEC_ADDR, \\\n \t\tCONFIG_SYS_FSL_SEC_ADDR)\n \n", "prefixes": [ "U-Boot", "v2", "2/3" ] }