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GET /api/patches/1048240/?format=api
{ "id": 1048240, "url": "http://patchwork.ozlabs.org/api/patches/1048240/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190226111834.26677-1-laurentiu.tudor@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190226111834.26677-1-laurentiu.tudor@nxp.com>", "list_archive_url": null, "date": "2019-02-26T11:18:32", "name": "[U-Boot,v2,1/3] fsl_sec: fix register layout on Layerscape architectures", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "f2184600ab19c5f16a1d6d3a663c179a6227cde0", "submitter": { "id": 71003, "url": "http://patchwork.ozlabs.org/api/people/71003/?format=api", "name": "Laurentiu Tudor", "email": "laurentiu.tudor@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190226111834.26677-1-laurentiu.tudor@nxp.com/mbox/", "series": [ { "id": 94219, "url": "http://patchwork.ozlabs.org/api/series/94219/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=94219", "date": "2019-02-26T11:18:32", "name": "[U-Boot,v2,1/3] fsl_sec: fix register layout on Layerscape architectures", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/94219/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1048240/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1048240/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 447xCF0DFWz9sBL\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 26 Feb 2019 22:18:46 +1100 (AEDT)", "by lists.denx.de (Postfix, from userid 105)\n\tid EF936C21E42; Tue, 26 Feb 2019 11:18:40 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id E8D32C21C38;\n\tTue, 26 Feb 2019 11:18:38 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid C5C00C21CB1; Tue, 26 Feb 2019 11:18:37 +0000 (UTC)", "from inva021.nxp.com (inva021.nxp.com [92.121.34.21])\n\tby lists.denx.de (Postfix) with ESMTPS id 6FD12C21C2F\n\tfor <u-boot@lists.denx.de>; Tue, 26 Feb 2019 11:18:37 +0000 (UTC)", "from inva021.nxp.com (localhost [127.0.0.1])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 8EDFB200300;\n\tTue, 26 Feb 2019 12:18:36 +0100 (CET)", "from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com\n\t[134.27.226.22])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 81BEA2001DE;\n\tTue, 26 Feb 2019 12:18:36 +0100 (CET)", "from fsr-ub1864-101.ea.freescale.net\n\t(fsr-ub1864-101.ea.freescale.net [10.171.82.46])\n\tby inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 263B7205EB;\n\tTue, 26 Feb 2019 12:18:36 +0100 (CET)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "laurentiu.tudor@nxp.com", "To": "u-boot@lists.denx.de,\n\tprabhakar.kushwaha@nxp.com", "Date": "Tue, 26 Feb 2019 13:18:32 +0200", "Message-Id": "<20190226111834.26677-1-laurentiu.tudor@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Subject": "[U-Boot] [PATCH v2 1/3] fsl_sec: fix register layout on Layerscape\n\tarchitectures", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Laurentiu Tudor <laurentiu.tudor@nxp.com>\n\nOn Layerscape architectures the SEC memory map is 1MB and the\nregister blocks contained in it are 64KB aligned, not 4KB as\nthe ccsr_sec structure currently assumes. Fix the layout of\nthe structure for these architectures.\n\nSigned-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>\nReviewed-by: Horia Geanta <horia.geanta@nxp.com>\nReviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>\n---\nv2:\n - added Reviewed-by tags\n\n include/fsl_sec.h | 8 ++++++++\n 1 file changed, 8 insertions(+)", "diff": "diff --git a/include/fsl_sec.h b/include/fsl_sec.h\nindex 16e3fcb5a1..be08a2b88b 100644\n--- a/include/fsl_sec.h\n+++ b/include/fsl_sec.h\n@@ -121,10 +121,18 @@ typedef struct ccsr_sec {\n \tu32\tchanum_ls;\t/* CHA Number Register, LS */\n \tu32\tsecvid_ms;\t/* SEC Version ID Register, MS */\n \tu32\tsecvid_ls;\t/* SEC Version ID Register, LS */\n+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)\n+\tu8\tres9[0x6f020];\n+#else\n \tu8\tres9[0x6020];\n+#endif\n \tu32\tqilcr_ms;\t/* Queue Interface LIODN CFG Register, MS */\n \tu32\tqilcr_ls;\t/* Queue Interface LIODN CFG Register, LS */\n+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)\n+\tu8\tres10[0x8ffd8];\n+#else\n \tu8\tres10[0x8fd8];\n+#endif\n } ccsr_sec_t;\n \n #define SEC_CTPR_MS_AXI_LIODN\t\t0x08000000\n", "prefixes": [ "U-Boot", "v2", "1/3" ] }