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GET /api/patches/1038960/?format=api
{ "id": 1038960, "url": "http://patchwork.ozlabs.org/api/patches/1038960/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190208205101.12078-6-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190208205101.12078-6-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2019-02-08T20:50:52", "name": "[S12,05/14] ice : Ensure only valid bits are set in ice_aq_set_phy_cfg", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "8882855922c2724a443a2d2acf89440af09b00e7", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190208205101.12078-6-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 90914, "url": "http://patchwork.ozlabs.org/api/series/90914/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=90914", "date": "2019-02-08T20:50:49", "name": "Bug fixes and minor feature updates for ice", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/90914/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1038960/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1038960/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 43x6pW5D4qz9sN8\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 9 Feb 2019 07:53:23 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 5D09223509;\n\tFri, 8 Feb 2019 20:53:22 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id TEQK7m78sFhc; Fri, 8 Feb 2019 20:53:21 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 9BEEC228AE;\n\tFri, 8 Feb 2019 20:53:21 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id E2F191BF97B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 8 Feb 2019 20:51:10 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id F0F5788178\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 8 Feb 2019 20:51:06 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 4EZTsyapy3VZ for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 8 Feb 2019 20:51:04 +0000 (UTC)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n\tby whitealder.osuosl.org (Postfix) with ESMTPS id 3B47388166\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 8 Feb 2019 20:51:04 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t08 Feb 2019 12:51:02 -0800", "from shasta.jf.intel.com ([10.166.241.11])\n\tby fmsmga002.fm.intel.com with ESMTP; 08 Feb 2019 12:51:01 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.58,348,1544515200\"; d=\"scan'208\";a=\"141869788\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Fri, 8 Feb 2019 12:50:52 -0800", "Message-Id": "<20190208205101.12078-6-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.5", "In-Reply-To": "<20190208205101.12078-1-anirudh.venkataramanan@intel.com>", "References": "<20190208205101.12078-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH S12 05/14] ice : Ensure only valid bits\n\tare set in ice_aq_set_phy_cfg", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Chinh T Cao <chinh.t.cao@intel.com>\n\nIn the ice_aq_set_phy_cfg AQ command, the 16.4 bit is reserved. This\npatch will make sure that this bit will never be set to 1.\n\nSigned-off-by: Chinh T Cao <chinh.t.cao@intel.com>\nReviewed-by: Bruce Allan <bruce.w.allan@intel.com>\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice_adminq_cmd.h | 5 +++--\n drivers/net/ethernet/intel/ice/ice_common.c | 11 +++++++++++\n drivers/net/ethernet/intel/ice/ice_type.h | 1 +\n 3 files changed, 15 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\nindex 242c78469181..8ff438968199 100644\n--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n@@ -953,8 +953,9 @@ struct ice_aqc_set_phy_cfg_data {\n \t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n \t__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */\n \tu8 caps;\n-#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY\t\tBIT(0)\n-#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY\t\tBIT(1)\n+#define ICE_AQ_PHY_ENA_VALID_MASK\tICE_M(0xef, 0)\n+#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY\tBIT(0)\n+#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY\tBIT(1)\n #define ICE_AQ_PHY_ENA_LOW_POWER\tBIT(2)\n #define ICE_AQ_PHY_ENA_LINK\t\tBIT(3)\n #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT\tBIT(5)\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex 63f003441300..2dc5c3249e12 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -1929,6 +1929,15 @@ ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,\n \tif (!cfg)\n \t\treturn ICE_ERR_PARAM;\n \n+\t/* Ensure that only valid bits of cfg->caps can be turned on. */\n+\tif (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {\n+\t\tice_debug(hw, ICE_DBG_PHY,\n+\t\t\t \"Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\\n\",\n+\t\t\t cfg->caps);\n+\n+\t\tcfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;\n+\t}\n+\n \tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);\n \tdesc.params.set_phy.lport_num = lport;\n \tdesc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);\n@@ -2027,8 +2036,10 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n \t/* clear the old pause settings */\n \tcfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |\n \t\t\t\t ICE_AQC_PHY_EN_RX_LINK_PAUSE);\n+\n \t/* set the new capabilities */\n \tcfg.caps |= pause_mask;\n+\n \t/* If the capabilities have changed, then set the new config */\n \tif (cfg.caps != pcaps->caps) {\n \t\tint retry_count, retry_max = 10;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h\nindex 17086d5b5c33..560b0d2d46ff 100644\n--- a/drivers/net/ethernet/intel/ice/ice_type.h\n+++ b/drivers/net/ethernet/intel/ice/ice_type.h\n@@ -24,6 +24,7 @@ static inline bool ice_is_tc_ena(u8 bitmap, u8 tc)\n /* debug masks - set these bits in hw->debug_mask to control output */\n #define ICE_DBG_INIT\t\tBIT_ULL(1)\n #define ICE_DBG_LINK\t\tBIT_ULL(4)\n+#define ICE_DBG_PHY\t\tBIT_ULL(5)\n #define ICE_DBG_QCTX\t\tBIT_ULL(6)\n #define ICE_DBG_NVM\t\tBIT_ULL(7)\n #define ICE_DBG_LAN\t\tBIT_ULL(8)\n", "prefixes": [ "S12", "05/14" ] }