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GET /api/patches/1038558/?format=api
{ "id": 1038558, "url": "http://patchwork.ozlabs.org/api/patches/1038558/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190208155443.17030-1-pankaj.bansal@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190208155443.17030-1-pankaj.bansal@nxp.com>", "list_archive_url": null, "date": "2019-02-08T10:29:58", "name": "[U-Boot,v6] lx2160aqds : Add support for LX2160AQDS platform", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "09c7a1ea9ea081c21c53d3ae90d33fcf1fb77ad6", "submitter": { "id": 72787, "url": "http://patchwork.ozlabs.org/api/people/72787/?format=api", "name": "Pankaj Bansal", "email": "pankaj.bansal@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190208155443.17030-1-pankaj.bansal@nxp.com/mbox/", "series": [ { "id": 90750, "url": "http://patchwork.ozlabs.org/api/series/90750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=90750", "date": "2019-02-08T10:29:58", "name": "[U-Boot,v6] lx2160aqds : Add support for LX2160AQDS platform", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/90750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1038558/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1038558/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Fri, 8 Feb 2019 10:30:00 +0000 (UTC)", "from AM5PR0401MB2481.eurprd04.prod.outlook.com (10.169.244.137) by\n\tAM5PR0401MB2673.eurprd04.prod.outlook.com (10.169.240.151) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1580.20; Fri, 8 Feb 2019 10:29:58 +0000", "from AM5PR0401MB2481.eurprd04.prod.outlook.com\n\t([fe80::a4ed:f8c5:3da7:f8bc]) by\n\tAM5PR0401MB2481.eurprd04.prod.outlook.com\n\t([fe80::a4ed:f8c5:3da7:f8bc%8]) with mapi id 15.20.1580.019;\n\tFri, 8 Feb 2019 10:29:58 +0000" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tSPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=lpqYve5poxN1FbuHORyvG6fTK3PtuaphcNOU66KNWJU=;\n\tb=hlQVy89X8whzgwAV/h25QO+7bgRJwM1DaWKbVOIWkmqWQg91dySKPGxv1YCZjJRjbWMvVLTqbOqBecK5NGFA4BkCVH5LXPwFkaKK3Vu6tP0STPrPkOBhBECiRoaAOvv/eUmInv49Lr8coZr5uey9aLt20WhtY3ae6+zLkLEREYQ=", "From": "Pankaj Bansal <pankaj.bansal@nxp.com>", "To": "Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>, Prabhakar Kushwaha\n\t<prabhakar.kushwaha@nxp.com>", "Thread-Topic": "[PATCH v6] lx2160aqds : Add support for LX2160AQDS platform", "Thread-Index": "AQHUv5k99PNTZUmedEujNkG6D+ZwFQ==", "Date": "Fri, 8 Feb 2019 10:29:58 +0000", "Message-ID": "<20190208155443.17030-1-pankaj.bansal@nxp.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "BM1PR0101CA0064.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:19::26) To AM5PR0401MB2481.eurprd04.prod.outlook.com\n\t(2603:10a6:203:36::9)", "authentication-results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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SFP:1101; SCL:1; SRVR:AM5PR0401MB2673;\n\tH:AM5PR0401MB2481.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; \n\tPTR:InfoNoRecords; A:1; MX:1; ", "received-spf": "None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)", "x-ms-exchange-senderadcheck": "1", "x-microsoft-antispam-message-info": "5auuuEWgOtIpgrrKKQLrte7b1/RZgt6r24ahDIOeFgBerP3ltehfu62pQHT1VQiMwqFTUuY2XscqPSeya55NJzwWNyBANdXl9RqvttdTTAPzbRb1SITloUur/Sfwfcc0YQ+Dej81rPmZXayIaNvXqDtRy6XzUyQqx0zcz36VZ6zL4lrqC5QHI8g93fcVtdCzVHyda14TcGfhKJKwXSn1eV6cnsf2hZSYMaGMsxviJ8E8NPpV94XuEDkVgJpve6+WrCVDSsdeFJvopXjqvOuotEsEZ9vxzND/cibKZ57atSpejLiUwJ/n0o6/LTNtesJUK4KAL+Mjhlrid2fx5XUbfyFz3nYPPVJ0Zldo2f3uZRKX2d0bWsJkZaxnkxvvjlKGFGQt0m79jcT6w9HWktyO+ynGku1cZr64vYew/Dg7tDs=", "MIME-Version": "1.0", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "70ab0977-a33b-4458-d0a9-08d68db05f8e", "X-MS-Exchange-CrossTenant-originalarrivaltime": "08 Feb 2019 10:29:56.3558\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM5PR0401MB2673", "Cc": "\"u-boot@lists.denx.de\" <u-boot@lists.denx.de>,\n\tWasim Khan <wasim.khan@nxp.com>, Sriram Dash <sriram.dash@nxp.com>", "Subject": "[U-Boot] [PATCH v6] lx2160aqds : Add support for LX2160AQDS platform", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "LX2160AQDS is a development board that supports LX2160A\nfamily SoCs. This patch add base support for this board.\n\nSigned-off-by: Wasim Khan <wasim.khan@nxp.com>\nSigned-off-by: Sriram Dash <sriram.dash@nxp.com>\nSigned-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>\n---\n\nNotes:\n This patch depends on following patches:\n \thttp://patchwork.ozlabs.org/patch/1030280/\n V6\n - Rebased on latest LX2160ARDB distro boot support patch\n - Added 2019 in copyright\n - Fixed some formatting errors.\n V5\n - Add \"ethernet-phy-ieee802.3-c22\" or \"ethernet-phy-ieee802.3-c45\" in phy\n nodes for PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45\n specifications.\n V4\n - changed the LX2160ARDB to LX2160AQDS in dts file description\n Also removed the Author info from dts file header\n dts file : arch/arm/dts/fsl-lx2160a-qds.dts\n V3\n - modified the fdt phy fixup function as per fdt.\n refer https://patchwork.codeaurora.org/patch/657515/\n V2:\n - removed checkpatch warnings about line over 80 chars\n - Added CONFIG_FSL_MC_ENET macro in eth_lx2160aqds.c file\n to avoid compilation errors if this macro is not defined\n V1:\n The checkpatch script reported 28 warnings about line over 80\n characters, that i have not corrected. as IMO doing so, makes\n the code less legible.\n\n arch/arm/Kconfig | 13 +\n arch/arm/cpu/armv8/Kconfig | 1 +\n arch/arm/dts/Makefile | 3 +-\n arch/arm/dts/fsl-lx2160a-qds.dts | 17 +\n .../asm/arch-fsl-layerscape/immap_lsch3.h | 10 +-\n board/freescale/lx2160a/Kconfig | 18 +\n board/freescale/lx2160a/MAINTAINERS | 9 +\n board/freescale/lx2160a/Makefile | 1 +\n board/freescale/lx2160a/README | 118 +++\n board/freescale/lx2160a/eth_lx2160aqds.c | 805 +++++++++++++++++\n board/freescale/lx2160a/lx2160a.c | 279 +++++-\n configs/lx2160aqds_tfa_defconfig | 72 ++\n include/configs/lx2160aqds.h | 140 +++\n 13 files changed, 1483 insertions(+), 3 deletions(-)", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex 6fb8e74f56..787695d3bd 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -1090,6 +1090,19 @@ config TARGET_LX2160ARDB\n \t is a high-performance development platform that supports the\n \t QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.\n \n+config TARGET_LX2160AQDS\n+\tbool \"Support lx2160aqds\"\n+\tselect ARCH_LX2160A\n+\tselect ARCH_MISC_INIT\n+\tselect ARM64\n+\tselect ARMV8_MULTIENTRY\n+\tselect BOARD_LATE_INIT\n+\thelp\n+\t Support for NXP LX2160AQDS platform.\n+\t The lx2160aqds (LX2160A QorIQ Development System (QDS)\n+\t is a high-performance development platform that supports the\n+\t QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.\n+\n config TARGET_HIKEY\n \tbool \"Support HiKey 96boards Consumer Edition Platform\"\n \tselect ARM64\ndiff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig\nindex cc6d07832d..f0536038d6 100644\n--- a/arch/arm/cpu/armv8/Kconfig\n+++ b/arch/arm/cpu/armv8/Kconfig\n@@ -107,6 +107,7 @@ config PSCI_RESET\n \t\t !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \\\n \t\t !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \\\n \t\t !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \\\n+\t\t !TARGET_LX2160AQDS && \\\n \t\t !ARCH_UNIPHIER && !TARGET_S32V234EVB\n \thelp\n \t Most armv8 systems have PSCI support enabled in EL3, either through\ndiff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex dea689fdd3..276579c497 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -242,7 +242,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \\\n \tfsl-ls2088a-rdb-qspi.dtb \\\n \tfsl-ls1088a-rdb.dtb \\\n \tfsl-ls1088a-qds.dtb \\\n-\tfsl-lx2160a-rdb.dtb\n+\tfsl-lx2160a-rdb.dtb \\\n+\tfsl-lx2160a-qds.dtb\n dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \\\n \tfsl-ls1043a-qds-lpuart.dtb \\\n \tfsl-ls1043a-rdb.dtb \\\ndiff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts\nnew file mode 100644\nindex 0000000000..6192156fc3\n--- /dev/null\n+++ b/arch/arm/dts/fsl-lx2160a-qds.dts\n@@ -0,0 +1,17 @@\n+// SPDX-License-Identifier: GPL-2.0+ OR X11\n+/*\n+ * NXP LX2160AQDS device tree source\n+ *\n+ * Copyright 2018-2019 NXP\n+ *\n+ */\n+\n+/dts-v1/;\n+\n+#include \"fsl-lx2160a.dtsi\"\n+\n+/ {\n+\tmodel = \"NXP Layerscape LX2160AQDS Board\";\n+\tcompatible = \"fsl,lx2160aqds\", \"fsl,lx2160a\";\n+};\n+\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 0535224646..9fab88ab2f 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -2,7 +2,7 @@\n /*\n * LayerScape Internal Memory Map\n *\n- * Copyright 2017-2018 NXP\n+ * Copyright 2017-2019 NXP\n * Copyright 2014 Freescale Semiconductor, Inc.\n */\n \n@@ -350,6 +350,14 @@ struct ccsr_gur {\n #define FSL_CHASSIS3_SRDS1_REGSR\t29\n #define FSL_CHASSIS3_SRDS2_REGSR\t29\n #define FSL_CHASSIS3_SRDS3_REGSR\t29\n+#define FSL_CHASSIS3_RCWSR12_REGSR 12\n+#define FSL_CHASSIS3_RCWSR13_REGSR 13\n+#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000\n+#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24\n+#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038\n+#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3\n+#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00\n+#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9\n #elif defined(CONFIG_ARCH_LS1088A)\n #define FSL_CHASSIS3_EC1_REGSR 26\n #define FSL_CHASSIS3_EC2_REGSR 26\ndiff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig\nindex 5562c3ec45..122a385100 100644\n--- a/board/freescale/lx2160a/Kconfig\n+++ b/board/freescale/lx2160a/Kconfig\n@@ -14,3 +14,21 @@ config SYS_CONFIG_NAME\n \n source \"board/freescale/common/Kconfig\"\n endif\n+\n+if TARGET_LX2160AQDS\n+\n+config SYS_BOARD\n+\tdefault \"lx2160a\"\n+\n+config SYS_VENDOR\n+\tdefault \"freescale\"\n+\n+config SYS_SOC\n+\tdefault \"fsl-layerscape\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"lx2160aqds\"\n+\n+source \"board/freescale/common/Kconfig\"\n+endif\n+\ndiff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS\nindex b4dd842afc..f2170a1772 100644\n--- a/board/freescale/lx2160a/MAINTAINERS\n+++ b/board/freescale/lx2160a/MAINTAINERS\n@@ -6,3 +6,12 @@ F:\tinclude/configs/lx2160a_common.h\n F:\tinclude/configs/lx2160ardb.h\n F:\tconfigs/lx2160ardb_defconfig\n F:\tarch/arm/dts/fsl-lx2160a-rdb.dts\n+\n+LX2160AQDS BOARD\n+M:\tPankaj Bansal <pankaj.bansal@nxp.com>\n+S:\tMaintained\n+F:\tboard/freescale/lx2160a/eth_lx2160aqds.h\n+F:\tinclude/configs/lx2160aqds.h\n+F:\tconfigs/lx2160aqds_tfa_defconfig\n+F:\tarch/arm/dts/fsl-lx2160a-qds.dts\n+\ndiff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile\nindex be3709d449..d1a621b682 100644\n--- a/board/freescale/lx2160a/Makefile\n+++ b/board/freescale/lx2160a/Makefile\n@@ -7,3 +7,4 @@\n obj-y += lx2160a.o\n obj-y += ddr.o\n obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o\n+obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o\ndiff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README\nindex 618c40b6fa..62fb9eab15 100644\n--- a/board/freescale/lx2160a/README\n+++ b/board/freescale/lx2160a/README\n@@ -77,3 +77,121 @@ DPAA2 MC Firmware\t\t\t\t\t0x05000\n DPAA2 DPL\t\t\t\t\t\t0x06800\n DPAA2 DPC\t\t\t\t\t\t0x07000\n Kernel.itb\t\t\t\t\t\t0x08000\n+\n+LX2160AQDS board Overview\n+----------------------\n+Various Mezzanine cards and their connection for different SERDES protocols is\n+as below:\n+\n+SERDES1\t|CARDS\n+-----------------------------------------------------------------------\n+1\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)\n+\t|Connect I/O cable to IO_SLOT1(J110)\n+\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)\n+\t|Connect I/O cable to IO_SLOT2(J113)\n+------------------------------------------------------------------------\n+3\t|Mezzanine:X-M11-USXGMII (29828)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)\n+\t|Connect I/O cable to IO_SLOT1(J110)\n+\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)\n+\t|Connect I/O cable to IO_SLOT2(J113)\n+------------------------------------------------------------------------\n+7\t|Mezzanine:X-M11-USXGMII (29828)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)\n+\t|Connect I/O cable to IO_SLOT1(J110)\n+\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)\n+\t|Connect I/O cable to IO_SLOT2(J113)\n+------------------------------------------------------------------------\n+8\t|Mezzanine:X-M12-XFI (29829)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)\n+\t|Connect I/O cable to IO_SLOT1(J110)\n+\t|Mezzanine:X-M12-XFI (29829)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)\n+\t|Connect I/O cable to IO_SLOT2(J113)\n+------------------------------------------------------------------------\n+13\t|Mezzanine:X-M8-100G (29734)\n+\t|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)\n+\t|Connect I/O cable to IO_SLOT1(J110)\n+\t|Mezzanine:X-M8-100G (29734)\n+\t|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT2(J111)\n+\t|Connect I/O cable to IO_SLOT2(J113)\n+------------------------------------------------------------------------\n+15\t|Mezzanine:X-M8-100G (29734)\n+\t|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)\n+\t|Connect I/O cable to IO_SLOT1(J110)\n+\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)\n+\t|Connect I/O cable to IO_SLOT2(J113)\n+------------------------------------------------------------------------\n+17\t|Mezzanine:X-M13-25G (32133)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)\n+\t|Connect I/O cable to IO_SLOT1(J110)\n+\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)\n+\t|Connect I/O cable to IO_SLOT2(J113)\n+------------------------------------------------------------------------\n+19\t|Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)\n+\t|Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125)\n+\t|Mezzanine:X-M7-40G (29738)\n+\t|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)\n+\t|Connect I/O cable to IO_SLOT2(J113)\n+------------------------------------------------------------------------\n+20\t|Mezzanine:X-M7-40G (29738)\n+\t|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)\n+\t|Connect I/O cable to IO_SLOT1(J108)\n+\t|Mezzanine:X-M7-40G (29738)\n+\t|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)\n+\t|Connect I/O cable to IO_SLOT2(J113)\n+------------------------------------------------------------------------\n+\n+\n+SERDES2\t|CARDS\n+-----------------------------------------------------------------------\n+2\t|Mezzanine:X-M6-PCIE-X8 (29737) *\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)\n+\t|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117)\n+\t|Connect I/O cable to IO_SLOT3(J116)\n+------------------------------------------------------------------------\n+3\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)\n+\t|Connect I/O cable to IO_SLOT3(J116)\n+\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)\n+\t|Connect I/O cable to IO_SLOT4(J119)\n+------------------------------------------------------------------------\n+5\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)\n+\t|Connect I/O cable to IO_SLOT3(J116)\n+\t|Mezzanine:X-M5-SATA (29687)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)\n+\t|Connect I/O cable to IO_SLOT4(J119)\n+------------------------------------------------------------------------\n+11\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)\n+\t|Connect I/O cable to IO_SLOT7(J127)\n+\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)\n+\t|Connect I/O cable to IO_SLOT8(J131)\n+------------------------------------------------------------------------\n+\n+\n+SERDES3\t|CARDS\n+-----------------------------------------------------------------------\n+2\t|Mezzanine:X-M6-PCIE-X8 (29737) *\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)\n+\t|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT6 (J123)\n+\t|Connect I/O cable to IO_SLOT5(J122)\n+-------------------------------------------------------------------------\n+3\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)\n+\t|Connect I/O cable to IO_SLOT5(J122)\n+\t|Mezzanine:X-M4-PCIE-SGMII (29733)\n+\t|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT6 (J123)\n+\t|Connect I/O cable to IO_SLOT6(J125)\n+-------------------------------------------------------------------------\n+\ndiff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c\nnew file mode 100644\nindex 0000000000..1e98d0c1f9\n--- /dev/null\n+++ b/board/freescale/lx2160a/eth_lx2160aqds.c\n@@ -0,0 +1,805 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2018-2019 NXP\n+ *\n+ */\n+\n+#include <common.h>\n+#include <hwconfig.h>\n+#include <command.h>\n+#include <netdev.h>\n+#include <malloc.h>\n+#include <fsl_mdio.h>\n+#include <miiphy.h>\n+#include <phy.h>\n+#include <fm_eth.h>\n+#include <asm/io.h>\n+#include <exports.h>\n+#include <asm/arch/fsl_serdes.h>\n+#include <fsl-mc/fsl_mc.h>\n+#include <fsl-mc/ldpaa_wriop.h>\n+\n+#include \"../common/qixis.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#define EMI_NONE\t0\n+#define EMI1\t\t1 /* Mdio Bus 1 */\n+#define EMI2\t\t2 /* Mdio Bus 2 */\n+\n+#if defined(CONFIG_FSL_MC_ENET)\n+enum io_slot {\n+\tIO_SLOT_NONE = 0,\n+\tIO_SLOT_1,\n+\tIO_SLOT_2,\n+\tIO_SLOT_3,\n+\tIO_SLOT_4,\n+\tIO_SLOT_5,\n+\tIO_SLOT_6,\n+\tIO_SLOT_7,\n+\tIO_SLOT_8,\n+\tEMI1_RGMII1,\n+\tEMI1_RGMII2,\n+\tIO_SLOT_MAX\n+};\n+\n+struct lx2160a_qds_mdio {\n+\tenum io_slot ioslot : 4;\n+\tu8 realbusnum : 4;\n+\tstruct mii_dev *realbus;\n+};\n+\n+/* structure explaining the phy configuration on 8 lanes of a serdes*/\n+struct serdes_phy_config {\n+\tu8 serdes; /* serdes protocol */\n+\tstruct phy_config {\n+\t\tu8 dpmacid;\n+\t\t/* -1 terminated array */\n+\t\tint phy_address[WRIOP_MAX_PHY_NUM + 1];\n+\t\tu8 mdio_bus;\n+\t\tenum io_slot ioslot;\n+\t} phy_config[SRDS_MAX_LANES];\n+};\n+\n+/* Table defining the phy configuration on 8 lanes of a serdes.\n+ * Various assumptions have been made while defining this table.\n+ * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII\n+ * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)\n+ * And also that this card is connected to IO Slot 1 (could have been connected\n+ * to any of the 8 IO slots (IO slot 1 - IO slot 8)).\n+ * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card\n+ * used in serdes1 protocol 19 (could have selected MDIO 2)\n+ * To override these settings \"dpmac\" environment variable can be used after\n+ * defining \"dpmac_override\" in hwconfig environment variable.\n+ * This table has limited serdes protocol entries. It can be expanded as per\n+ * requirement.\n+ */\n+static const struct serdes_phy_config serdes1_phy_config[] = {\n+\t{3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},\n+\t EMI1, IO_SLOT_1} } },\n+\t{7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},\n+\t EMI1, IO_SLOT_2},\n+\t {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},\n+\t EMI1, IO_SLOT_2},\n+\t {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},\n+\t EMI1, IO_SLOT_2},\n+\t {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},\n+\t EMI1, IO_SLOT_2} } },\n+\t{8, {} },\n+\t{13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_2} } },\n+\t{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_1} } },\n+\t{17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_1} } },\n+\t{19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},\n+\t EMI1, IO_SLOT_2},\n+\t {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_6},\n+\t {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},\n+\t EMI1, IO_SLOT_6} } },\n+\t{20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},\n+\t EMI1, IO_SLOT_1},\n+\t {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},\n+\t EMI1, IO_SLOT_2} } }\n+};\n+\n+static const struct serdes_phy_config serdes2_phy_config[] = {\n+\t{2, {} },\n+\t{3, {} },\n+\t{5, {} },\n+\t{11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},\n+\t EMI1, IO_SLOT_7},\n+\t {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},\n+\t EMI1, IO_SLOT_7},\n+\t {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},\n+\t EMI1, IO_SLOT_7},\n+\t {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},\n+\t EMI1, IO_SLOT_8},\n+\t {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},\n+\t EMI1, IO_SLOT_8},\n+\t {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},\n+\t EMI1, IO_SLOT_8} } },\n+};\n+\n+static const struct serdes_phy_config serdes3_phy_config[] = {\n+\t{2, {} },\n+\t{3, {} }\n+};\n+\n+static inline\n+const struct phy_config *get_phy_config(u8 serdes,\n+\t\t\t\t\tconst struct serdes_phy_config *table,\n+\t\t\t\t\tu8 table_size)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < table_size; i++) {\n+\t\tif (table[i].serdes == serdes)\n+\t\t\treturn table[i].phy_config;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+/* BRDCFG4 controls EMI routing for the board.\n+ * Bits Function\n+ * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):\n+ * EMI1 00= On-board PHY #1\n+ * 01= On-board PHY #2\n+ * 10= (reserved)\n+ * 11= Slots 1..8 multiplexer and translator.\n+ * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):\n+ * EMI1X 000= Slot #1\n+ * 001= Slot #2\n+ * 010= Slot #3\n+ * 011= Slot #4\n+ * 100= Slot #5\n+ * 101= Slot #6\n+ * 110= Slot #7\n+ * 111= Slot #8\n+ * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):\n+ * EMI2 000= Slot #1 (secondary EMI)\n+ * 001= Slot #2 (secondary EMI)\n+ * 010= Slot #3 (secondary EMI)\n+ * 011= Slot #4 (secondary EMI)\n+ * 100= Slot #5 (secondary EMI)\n+ * 101= Slot #6 (secondary EMI)\n+ * 110= Slot #7 (secondary EMI)\n+ * 111= Slot #8 (secondary EMI)\n+ */\n+static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)\n+{\n+\tswitch (realbusnum) {\n+\tcase EMI1:\n+\t\tswitch (ioslot) {\n+\t\tcase EMI1_RGMII1:\n+\t\t\treturn 0;\n+\t\tcase EMI1_RGMII2:\n+\t\t\treturn 0x40;\n+\t\tdefault:\n+\t\t\treturn (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);\n+\t\t}\n+\t\tbreak;\n+\tcase EMI2:\n+\t\treturn ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);\n+\tdefault:\n+\t\treturn -1;\n+\t}\n+}\n+\n+static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)\n+{\n+\tu8 brdcfg4, mux_val, reg;\n+\n+\tbrdcfg4 = QIXIS_READ(brdcfg[4]);\n+\treg = brdcfg4;\n+\tmux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);\n+\n+\tswitch (priv->realbusnum) {\n+\tcase EMI1:\n+\t\tbrdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;\n+\t\tbrdcfg4 |= mux_val;\n+\t\tbreak;\n+\tcase EMI2:\n+\t\tbrdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;\n+\t\tbrdcfg4 |= mux_val;\n+\t\tbreak;\n+\t}\n+\n+\tif (brdcfg4 ^ reg)\n+\t\tQIXIS_WRITE(brdcfg[4], brdcfg4);\n+}\n+\n+static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,\n+\t\t\t\t int devad, int regnum)\n+{\n+\tstruct lx2160a_qds_mdio *priv = bus->priv;\n+\n+\tlx2160a_qds_mux_mdio(priv);\n+\n+\treturn priv->realbus->read(priv->realbus, addr, devad, regnum);\n+}\n+\n+static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,\n+\t\t\t\t int regnum, u16 value)\n+{\n+\tstruct lx2160a_qds_mdio *priv = bus->priv;\n+\n+\tlx2160a_qds_mux_mdio(priv);\n+\n+\treturn priv->realbus->write(priv->realbus, addr, devad, regnum, value);\n+}\n+\n+static int lx2160a_qds_mdio_reset(struct mii_dev *bus)\n+{\n+\tstruct lx2160a_qds_mdio *priv = bus->priv;\n+\n+\treturn priv->realbus->reset(priv->realbus);\n+}\n+\n+static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)\n+{\n+\tstruct lx2160a_qds_mdio *pmdio;\n+\tstruct mii_dev *bus;\n+\t/*should be within MDIO_NAME_LEN*/\n+\tchar dummy_mdio_name[] = \"LX2160A_QDS_MDIO1_IOSLOT1\";\n+\n+\tif (realbusnum == EMI2) {\n+\t\tif (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {\n+\t\t\tprintf(\"invalid ioslot %d\\n\", ioslot);\n+\t\t\treturn NULL;\n+\t\t}\n+\t} else if (realbusnum == EMI1) {\n+\t\tif (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {\n+\t\t\tprintf(\"invalid ioslot %d\\n\", ioslot);\n+\t\t\treturn NULL;\n+\t\t}\n+\t} else {\n+\t\tprintf(\"not supported real mdio bus %d\\n\", realbusnum);\n+\t\treturn NULL;\n+\t}\n+\n+\tif (ioslot == EMI1_RGMII1)\n+\t\tstrcpy(dummy_mdio_name, \"LX2160A_QDS_MDIO1_RGMII1\");\n+\telse if (ioslot == EMI1_RGMII2)\n+\t\tstrcpy(dummy_mdio_name, \"LX2160A_QDS_MDIO1_RGMII2\");\n+\telse\n+\t\tsprintf(dummy_mdio_name, \"LX2160A_QDS_MDIO%d_IOSLOT%d\",\n+\t\t\trealbusnum, ioslot);\n+\tbus = miiphy_get_dev_by_name(dummy_mdio_name);\n+\n+\tif (bus)\n+\t\treturn bus;\n+\n+\tbus = mdio_alloc();\n+\tif (!bus) {\n+\t\tprintf(\"Failed to allocate %s bus\\n\", dummy_mdio_name);\n+\t\treturn NULL;\n+\t}\n+\n+\tpmdio = malloc(sizeof(*pmdio));\n+\tif (!pmdio) {\n+\t\tprintf(\"Failed to allocate %s private data\\n\", dummy_mdio_name);\n+\t\tfree(bus);\n+\t\treturn NULL;\n+\t}\n+\n+\tswitch (realbusnum) {\n+\tcase EMI1:\n+\t\tpmdio->realbus =\n+\t\t miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);\n+\t\tbreak;\n+\tcase EMI2:\n+\t\tpmdio->realbus =\n+\t\t miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);\n+\t\tbreak;\n+\t}\n+\n+\tif (!pmdio->realbus) {\n+\t\tprintf(\"No real mdio bus num %d found\\n\", realbusnum);\n+\t\tfree(bus);\n+\t\tfree(pmdio);\n+\t\treturn NULL;\n+\t}\n+\n+\tpmdio->realbusnum = realbusnum;\n+\tpmdio->ioslot = ioslot;\n+\tbus->read = lx2160a_qds_mdio_read;\n+\tbus->write = lx2160a_qds_mdio_write;\n+\tbus->reset = lx2160a_qds_mdio_reset;\n+\tstrcpy(bus->name, dummy_mdio_name);\n+\tbus->priv = pmdio;\n+\n+\tif (!mdio_register(bus))\n+\t\treturn bus;\n+\n+\tprintf(\"No bus with name %s\\n\", dummy_mdio_name);\n+\tfree(bus);\n+\tfree(pmdio);\n+\treturn NULL;\n+}\n+\n+static inline void do_phy_config(const struct phy_config *phy_config)\n+{\n+\tstruct mii_dev *bus;\n+\tint i, phy_num, phy_address;\n+\n+\tfor (i = 0; i < SRDS_MAX_LANES; i++) {\n+\t\tif (!phy_config[i].dpmacid)\n+\t\t\tcontinue;\n+\n+\t\tfor (phy_num = 0;\n+\t\t phy_num < ARRAY_SIZE(phy_config[i].phy_address);\n+\t\t phy_num++) {\n+\t\t\tphy_address = phy_config[i].phy_address[phy_num];\n+\t\t\tif (phy_address == -1)\n+\t\t\t\tbreak;\n+\t\t\twriop_set_phy_address(phy_config[i].dpmacid,\n+\t\t\t\t\t phy_num, phy_address);\n+\t\t}\n+\t\t/*Register the muxing front-ends to the MDIO buses*/\n+\t\tbus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,\n+\t\t\t\t\t phy_config[i].ioslot);\n+\t\tif (!bus)\n+\t\t\tprintf(\"could not get bus for mdio %d ioslot %d\\n\",\n+\t\t\t phy_config[i].mdio_bus,\n+\t\t\t phy_config[i].ioslot);\n+\t\telse\n+\t\t\twriop_set_mdio(phy_config[i].dpmacid, bus);\n+\t}\n+}\n+\n+static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,\n+\t\t\t\t char *env_dpmac)\n+{\n+\tconst char *ret;\n+\tsize_t len;\n+\tu8 realbusnum, ioslot;\n+\tstruct mii_dev *bus;\n+\tint phy_num;\n+\tchar *phystr = \"phy00\";\n+\n+\t/*search phy in dpmac arg*/\n+\tfor (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {\n+\t\tsprintf(phystr, \"phy%d\", phy_num + 1);\n+\t\tret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);\n+\t\tif (!ret) {\n+\t\t\t/*look for phy instead of phy1*/\n+\t\t\tif (!phy_num)\n+\t\t\t\tret = hwconfig_subarg_f(arg_dpmacid, \"phy\",\n+\t\t\t\t\t\t\t&len, env_dpmac);\n+\t\t\tif (!ret)\n+\t\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (len != 4 || strncmp(ret, \"0x\", 2))\n+\t\t\tprintf(\"invalid phy format in %s variable.\\n\"\n+\t\t\t \"specify phy%d for %s in hex format e.g. 0x12\\n\",\n+\t\t\t env_dpmac, phy_num + 1, arg_dpmacid);\n+\t\telse\n+\t\t\twriop_set_phy_address(dpmac, phy_num,\n+\t\t\t\t\t simple_strtoul(ret, NULL, 16));\n+\t}\n+\n+\t/*search mdio in dpmac arg*/\n+\tret = hwconfig_subarg_f(arg_dpmacid, \"mdio\", &len, env_dpmac);\n+\tif (ret)\n+\t\trealbusnum = *ret - '0';\n+\telse\n+\t\trealbusnum = EMI_NONE;\n+\n+\tif (realbusnum) {\n+\t\t/*search io in dpmac arg*/\n+\t\tret = hwconfig_subarg_f(arg_dpmacid, \"io\", &len, env_dpmac);\n+\t\tif (ret)\n+\t\t\tioslot = *ret - '0';\n+\t\telse\n+\t\t\tioslot = IO_SLOT_NONE;\n+\t\t/*Register the muxing front-ends to the MDIO buses*/\n+\t\tbus = lx2160a_qds_mdio_init(realbusnum, ioslot);\n+\t\tif (!bus)\n+\t\t\tprintf(\"could not get bus for mdio %d ioslot %d\\n\",\n+\t\t\t realbusnum, ioslot);\n+\t\telse\n+\t\t\twriop_set_mdio(dpmac, bus);\n+\t}\n+}\n+\n+#endif\n+\n+int board_eth_init(bd_t *bis)\n+{\n+#if defined(CONFIG_FSL_MC_ENET)\n+\tstruct memac_mdio_info mdio_info;\n+\tstruct memac_mdio_controller *regs;\n+\tint i;\n+\tconst char *ret;\n+\tchar *env_dpmac;\n+\tchar dpmacid[] = \"dpmac00\", srds[] = \"00_00_00\";\n+\tsize_t len;\n+\tstruct mii_dev *bus;\n+\tconst struct phy_config *phy_config;\n+\tstruct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n+\tu32 srds_s1, srds_s2, srds_s3;\n+\n+\tsrds_s1 = in_le32(&gur->rcwsr[28]) &\n+\t\t FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;\n+\tsrds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;\n+\n+\tsrds_s2 = in_le32(&gur->rcwsr[28]) &\n+\t\t FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;\n+\tsrds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;\n+\n+\tsrds_s3 = in_le32(&gur->rcwsr[28]) &\n+\t\t FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;\n+\tsrds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;\n+\n+\tsprintf(srds, \"%d_%d_%d\", srds_s1, srds_s2, srds_s3);\n+\n+\tregs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;\n+\tmdio_info.regs = regs;\n+\tmdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;\n+\n+\t/*Register the EMI 1*/\n+\tfm_memac_mdio_init(bis, &mdio_info);\n+\n+\tregs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;\n+\tmdio_info.regs = regs;\n+\tmdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;\n+\n+\t/*Register the EMI 2*/\n+\tfm_memac_mdio_init(bis, &mdio_info);\n+\n+\t/* \"dpmac\" environment variable can be used after\n+\t * defining \"dpmac_override\" in hwconfig environment variable.\n+\t */\n+\tif (hwconfig(\"dpmac_override\")) {\n+\t\tenv_dpmac = env_get(\"dpmac\");\n+\t\tif (env_dpmac) {\n+\t\t\tret = hwconfig_arg_f(\"srds\", &len, env_dpmac);\n+\t\t\tif (ret) {\n+\t\t\t\tif (strncmp(ret, srds, strlen(srds))) {\n+\t\t\t\t\tprintf(\"SERDES configuration changed.\\n\"\n+\t\t\t\t\t \"previous: %.*s, current: %s.\\n\"\n+\t\t\t\t\t \"update dpmac variable.\\n\",\n+\t\t\t\t\t (int)len, ret, srds);\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tprintf(\"SERDES configuration not found.\\n\"\n+\t\t\t\t \"Please add srds:%s in dpmac variable\\n\",\n+\t\t\t\t srds);\n+\t\t\t}\n+\n+\t\t\tfor (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {\n+\t\t\t\t/* Look for dpmac1 to dpmac24(current max) arg\n+\t\t\t\t * in dpmac environment variable\n+\t\t\t\t */\n+\t\t\t\tsprintf(dpmacid, \"dpmac%d\", i);\n+\t\t\t\tret = hwconfig_arg_f(dpmacid, &len, env_dpmac);\n+\t\t\t\tif (ret)\n+\t\t\t\t\tdo_dpmac_config(i, dpmacid, env_dpmac);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tprintf(\"Warning: environment dpmac not found.\\n\"\n+\t\t\t \"DPAA network interfaces may not work\\n\");\n+\t\t}\n+\t} else {\n+\t\t/*Look for phy config for serdes1 in phy config table*/\n+\t\tphy_config = get_phy_config(srds_s1, serdes1_phy_config,\n+\t\t\t\t\t ARRAY_SIZE(serdes1_phy_config));\n+\t\tif (!phy_config) {\n+\t\t\tprintf(\"%s WRIOP: Unsupported SerDes1 Protocol %d\\n\",\n+\t\t\t __func__, srds_s1);\n+\t\t} else {\n+\t\t\tdo_phy_config(phy_config);\n+\t\t}\n+\t\tphy_config = get_phy_config(srds_s2, serdes2_phy_config,\n+\t\t\t\t\t ARRAY_SIZE(serdes2_phy_config));\n+\t\tif (!phy_config) {\n+\t\t\tprintf(\"%s WRIOP: Unsupported SerDes2 Protocol %d\\n\",\n+\t\t\t __func__, srds_s2);\n+\t\t} else {\n+\t\t\tdo_phy_config(phy_config);\n+\t\t}\n+\t\tphy_config = get_phy_config(srds_s3, serdes3_phy_config,\n+\t\t\t\t\t ARRAY_SIZE(serdes3_phy_config));\n+\t\tif (!phy_config) {\n+\t\t\tprintf(\"%s WRIOP: Unsupported SerDes3 Protocol %d\\n\",\n+\t\t\t __func__, srds_s3);\n+\t\t} else {\n+\t\t\tdo_phy_config(phy_config);\n+\t\t}\n+\t}\n+\n+\tif (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {\n+\t\twriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);\n+\t\tbus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);\n+\t\tif (!bus)\n+\t\t\tprintf(\"could not get bus for RGMII1\\n\");\n+\t\telse\n+\t\t\twriop_set_mdio(WRIOP1_DPMAC17, bus);\n+\t}\n+\n+\tif (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {\n+\t\twriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);\n+\t\tbus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);\n+\t\tif (!bus)\n+\t\t\tprintf(\"could not get bus for RGMII2\\n\");\n+\t\telse\n+\t\t\twriop_set_mdio(WRIOP1_DPMAC18, bus);\n+\t}\n+\n+\tcpu_eth_init(bis);\n+#endif /* CONFIG_FMAN_ENET */\n+\n+#ifdef CONFIG_PHY_AQUANTIA\n+\t/*\n+\t * Export functions to be used by AQ firmware\n+\t * upload application\n+\t */\n+\tgd->jt->strcpy = strcpy;\n+\tgd->jt->mdelay = mdelay;\n+\tgd->jt->mdio_get_current_dev = mdio_get_current_dev;\n+\tgd->jt->phy_find_by_mask = phy_find_by_mask;\n+\tgd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;\n+\tgd->jt->miiphy_set_current_dev = miiphy_set_current_dev;\n+#endif\n+\treturn pci_eth_init(bis);\n+}\n+\n+#if defined(CONFIG_RESET_PHY_R)\n+void reset_phy(void)\n+{\n+#if defined(CONFIG_FSL_MC_ENET)\n+\tmc_env_boot();\n+#endif\n+}\n+#endif /* CONFIG_RESET_PHY_R */\n+\n+#if defined(CONFIG_FSL_MC_ENET)\n+int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)\n+{\n+\tint offset;\n+\tint ret;\n+\tchar dpmac_str[] = \"dpmacs@00\";\n+\tconst char *phy_string;\n+\n+\toffset = fdt_path_offset(fdt, \"/soc/fsl-mc/dpmacs\");\n+\n+\tif (offset < 0)\n+\t\toffset = fdt_path_offset(fdt, \"/fsl-mc/dpmacs\");\n+\n+\tif (offset < 0) {\n+\t\tprintf(\"dpmacs node not found in device tree\\n\");\n+\t\treturn offset;\n+\t}\n+\n+\tsprintf(dpmac_str, \"dpmac@%x\", dpmac_id);\n+\tdebug(\"dpmac_str = %s\\n\", dpmac_str);\n+\n+\toffset = fdt_subnode_offset(fdt, offset, dpmac_str);\n+\tif (offset < 0) {\n+\t\tprintf(\"%s node not found in device tree\\n\", dpmac_str);\n+\t\treturn offset;\n+\t}\n+\n+\tret = fdt_appendprop_cell(fdt, offset, \"phy-handle\", node_phandle);\n+\tif (ret)\n+\t\tprintf(\"%d@%s %d\\n\", __LINE__, __func__, ret);\n+\n+\tphy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));\n+\tret = fdt_setprop_string(fdt, offset, \"phy-connection-type\",\n+\t\t\t\t phy_string);\n+\tif (ret)\n+\t\tprintf(\"%d@%s %d\\n\", __LINE__, __func__, ret);\n+\n+\treturn ret;\n+}\n+\n+int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)\n+{\n+\tchar mdio_ioslot_str[] = \"mdio@00\";\n+\tchar mdio_mux_str[] = \"mdio-mux-0\";\n+\tstruct lx2160a_qds_mdio *priv;\n+\tint offset, mux_val;\n+\n+\t/*Test if the MDIO bus is real mdio bus or muxing front end ?*/\n+\tif (strncmp(mii_dev->name, \"LX2160A_QDS_MDIO\",\n+\t\t strlen(\"LX2160A_QDS_MDIO\")))\n+\t\treturn -1;\n+\n+\t/*Get the real MDIO bus num and ioslot info from bus's priv data*/\n+\tpriv = mii_dev->priv;\n+\n+\tdebug(\"real_bus_num = %d, ioslot = %d\\n\",\n+\t priv->realbusnum, priv->ioslot);\n+\n+\tsprintf(mdio_mux_str, \"mdio-mux-%1d\", priv->realbusnum);\n+\toffset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str);\n+\tif (offset < 0) {\n+\t\tprintf(\"%s node not found under node %s in device tree\\n\",\n+\t\t mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL));\n+\t\treturn offset;\n+\t}\n+\n+\tmux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);\n+\tsprintf(mdio_ioslot_str, \"mdio@%x\", (u8)mux_val);\n+\n+\toffset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);\n+\tif (offset < 0) {\n+\t\tprintf(\"%s node not found in device tree\\n\", mdio_ioslot_str);\n+\t\treturn offset;\n+\t}\n+\n+\treturn offset;\n+}\n+\n+int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,\n+\t\t\tstruct phy_device *phy_dev, int phandle)\n+{\n+\tchar phy_node_name[] = \"ethernet-phy@00\";\n+\tchar phy_id_compatible_str[] = \"ethernet-phy-id0000.0000\";\n+\tint ret;\n+\n+\tsprintf(phy_node_name, \"ethernet-phy@%x\", phyaddr);\n+\tdebug(\"phy_node_name = %s\\n\", phy_node_name);\n+\n+\t*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);\n+\tif (*subnodeoffset <= 0) {\n+\t\tprintf(\"Could not add subnode %s\\n\", phy_node_name);\n+\t\treturn *subnodeoffset;\n+\t}\n+\n+\tsprintf(phy_id_compatible_str, \"ethernet-phy-id%04x.%04x\",\n+\t\tphy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);\n+\tdebug(\"phy_id_compatible_str %s\\n\", phy_id_compatible_str);\n+\n+\tret = fdt_setprop_string(fdt, *subnodeoffset, \"compatible\",\n+\t\t\t\t phy_id_compatible_str);\n+\tif (ret) {\n+\t\tprintf(\"%d@%s %d\\n\", __LINE__, __func__, ret);\n+\t\tgoto out;\n+\t}\n+\n+\tif (phy_dev->is_c45) {\n+\t\tret = fdt_appendprop_string(fdt, *subnodeoffset, \"compatible\",\n+\t\t\t\t\t \"ethernet-phy-ieee802.3-c45\");\n+\t\tif (ret) {\n+\t\t\tprintf(\"%d@%s %d\\n\", __LINE__, __func__, ret);\n+\t\t\tgoto out;\n+\t\t}\n+\t} else {\n+\t\tret = fdt_appendprop_string(fdt, *subnodeoffset, \"compatible\",\n+\t\t\t\t\t \"ethernet-phy-ieee802.3-c22\");\n+\t\tif (ret) {\n+\t\t\tprintf(\"%d@%s %d\\n\", __LINE__, __func__, ret);\n+\t\t\tgoto out;\n+\t\t}\n+\t}\n+\n+\tret = fdt_setprop_cell(fdt, *subnodeoffset, \"reg\", phyaddr);\n+\tif (ret) {\n+\t\tprintf(\"%d@%s %d\\n\", __LINE__, __func__, ret);\n+\t\tgoto out;\n+\t}\n+\n+\tret = fdt_set_phandle(fdt, *subnodeoffset, phandle);\n+\tif (ret) {\n+\t\tprintf(\"%d@%s %d\\n\", __LINE__, __func__, ret);\n+\t\tgoto out;\n+\t}\n+\n+out:\n+\tif (ret)\n+\t\tfdt_del_node(fdt, *subnodeoffset);\n+\n+\treturn ret;\n+}\n+\n+int fdt_fixup_board_phy(void *fdt)\n+{\n+\tint fpga_offset, offset, subnodeoffset;\n+\tstruct mii_dev *mii_dev;\n+\tstruct list_head *mii_devs, *entry;\n+\tint ret, dpmac_id, phandle, i;\n+\tstruct phy_device *phy_dev;\n+\tchar ethname[ETH_NAME_LEN];\n+\tphy_interface_t\tphy_iface;\n+\n+\tret = 0;\n+\t/* we know FPGA is connected to i2c0, therefore search path directly,\n+\t * instead of compatible property, as it saves time\n+\t */\n+\tfpga_offset = fdt_path_offset(fdt, \"/soc/i2c@2000000/fpga\");\n+\n+\tif (fpga_offset < 0)\n+\t\tfpga_offset = fdt_path_offset(fdt, \"/i2c@2000000/fpga\");\n+\n+\tif (fpga_offset < 0) {\n+\t\tprintf(\"i2c@2000000/fpga node not found in device tree\\n\");\n+\t\treturn fpga_offset;\n+\t}\n+\n+\tphandle = fdt_alloc_phandle(fdt);\n+\tmii_devs = mdio_get_list_head();\n+\n+\tlist_for_each(entry, mii_devs) {\n+\t\tmii_dev = list_entry(entry, struct mii_dev, link);\n+\t\tdebug(\"mii_dev name : %s\\n\", mii_dev->name);\n+\t\toffset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);\n+\t\tif (offset < 0)\n+\t\t\tcontinue;\n+\n+\t\t// Look for phy devices attached to MDIO bus muxing front end\n+\t\t// and create their entries with compatible being the device id\n+\t\tfor (i = 0; i < PHY_MAX_ADDR; i++) {\n+\t\t\tphy_dev = mii_dev->phymap[i];\n+\t\t\tif (!phy_dev)\n+\t\t\t\tcontinue;\n+\n+\t\t\t// TODO: use sscanf instead of loop\n+\t\t\tdpmac_id = WRIOP1_DPMAC1;\n+\t\t\twhile (dpmac_id < NUM_WRIOP_PORTS) {\n+\t\t\t\tphy_iface = wriop_get_enet_if(dpmac_id);\n+\t\t\t\tsnprintf(ethname, ETH_NAME_LEN, \"DPMAC%d@%s\",\n+\t\t\t\t\t dpmac_id,\n+\t\t\t\t\t phy_string_for_interface(phy_iface));\n+\t\t\t\tif (strcmp(ethname, phy_dev->dev->name) == 0)\n+\t\t\t\t\tbreak;\n+\t\t\t\tdpmac_id++;\n+\t\t\t}\n+\t\t\tif (dpmac_id == NUM_WRIOP_PORTS)\n+\t\t\t\tcontinue;\n+\n+\t\t\tret = fdt_create_phy_node(fdt, offset, i,\n+\t\t\t\t\t\t &subnodeoffset,\n+\t\t\t\t\t\t phy_dev, phandle);\n+\t\t\tif (ret)\n+\t\t\t\tbreak;\n+\n+\t\t\tret = fdt_fixup_dpmac_phy_handle(fdt,\n+\t\t\t\t\t\t\t dpmac_id, phandle);\n+\t\t\tif (ret) {\n+\t\t\t\tfdt_del_node(fdt, subnodeoffset);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tphandle++;\n+\t\t}\n+\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+#endif // CONFIG_FSL_MC_ENET\n+\ndiff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c\nindex a62222e25c..2cbfe4806b 100644\n--- a/board/freescale/lx2160a/lx2160a.c\n+++ b/board/freescale/lx2160a/lx2160a.c\n@@ -26,6 +26,18 @@\n #include \"../common/vid.h\"\n #include <fsl_immap.h>\n \n+#ifdef CONFIG_TARGET_LX2160AQDS\n+#define CFG_MUX_I2C_SDHC(reg, value)\t\t((reg & 0x3f) | value)\n+#define SET_CFG_MUX1_SDHC1_SDHC(reg)\t\t(reg & 0x3f)\n+#define SET_CFG_MUX2_SDHC1_SPI(reg, value)\t((reg & 0xcf) | value)\n+#define SET_CFG_MUX3_SDHC1_SPI(reg, value)\t((reg & 0xf8) | value)\n+#define SET_CFG_MUX_SDHC2_DSPI(reg, value)\t((reg & 0xf8) | value)\n+#define SET_CFG_MUX1_SDHC1_DSPI(reg, value)\t((reg & 0x3f) | value)\n+#define SDHC1_BASE_PMUX_DSPI\t\t\t2\n+#define SDHC2_BASE_PMUX_DSPI\t\t\t2\n+#define IIC5_PMUX_SPI3\t\t\t\t3\n+#endif /* CONFIG_TARGET_LX2160AQDS */\n+\n DECLARE_GLOBAL_DATA_PTR;\n \n static struct pl01x_serial_platdata serial0 = {\n@@ -85,12 +97,80 @@ int board_early_init_f(void)\n \treturn 0;\n }\n \n+#if defined(CONFIG_TARGET_LX2160AQDS)\n+void esdhc_dspi_status_fixup(void *blob)\n+{\n+\tconst char esdhc0_path[] = \"/soc/esdhc@2140000\";\n+\tconst char esdhc1_path[] = \"/soc/esdhc@2150000\";\n+\tconst char dspi0_path[] = \"/soc/dspi@2100000\";\n+\tconst char dspi1_path[] = \"/soc/dspi@2110000\";\n+\tconst char dspi2_path[] = \"/soc/dspi@2120000\";\n+\n+\tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n+\tu32 sdhc1_base_pmux;\n+\tu32 sdhc2_base_pmux;\n+\tu32 iic5_pmux;\n+\n+\t/* Check RCW field sdhc1_base_pmux to enable/disable\n+\t * esdhc0/dspi0 DT node\n+\t */\n+\tsdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])\n+\t\t& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;\n+\tsdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;\n+\n+\tif (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {\n+\t\tdo_fixup_by_path(blob, dspi0_path, \"status\", \"okay\",\n+\t\t\t\t sizeof(\"okay\"), 1);\n+\t\tdo_fixup_by_path(blob, esdhc0_path, \"status\", \"disabled\",\n+\t\t\t\t sizeof(\"disabled\"), 1);\n+\t} else {\n+\t\tdo_fixup_by_path(blob, esdhc0_path, \"status\", \"okay\",\n+\t\t\t\t sizeof(\"okay\"), 1);\n+\t\tdo_fixup_by_path(blob, dspi0_path, \"status\", \"disabled\",\n+\t\t\t\t sizeof(\"disabled\"), 1);\n+\t}\n+\n+\t/* Check RCW field sdhc2_base_pmux to enable/disable\n+\t * esdhc1/dspi1 DT node\n+\t */\n+\tsdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])\n+\t\t& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;\n+\tsdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;\n+\n+\tif (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {\n+\t\tdo_fixup_by_path(blob, dspi1_path, \"status\", \"okay\",\n+\t\t\t\t sizeof(\"okay\"), 1);\n+\t\tdo_fixup_by_path(blob, esdhc1_path, \"status\", \"disabled\",\n+\t\t\t\t sizeof(\"disabled\"), 1);\n+\t} else {\n+\t\tdo_fixup_by_path(blob, esdhc1_path, \"status\", \"okay\",\n+\t\t\t\t sizeof(\"okay\"), 1);\n+\t\tdo_fixup_by_path(blob, dspi1_path, \"status\", \"disabled\",\n+\t\t\t\t sizeof(\"disabled\"), 1);\n+\t}\n+\n+\t/* Check RCW field IIC5 to enable dspi2 DT node */\n+\tiic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])\n+\t\t& FSL_CHASSIS3_IIC5_PMUX_MASK;\n+\tiic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;\n+\n+\tif (iic5_pmux == IIC5_PMUX_SPI3) {\n+\t\tdo_fixup_by_path(blob, dspi2_path, \"status\", \"okay\",\n+\t\t\t\t sizeof(\"okay\"), 1);\n+\t}\n+}\n+#endif\n+\n int esdhc_status_fixup(void *blob, const char *compat)\n {\n+#if defined(CONFIG_TARGET_LX2160AQDS)\n+\t/* Enable esdhc and dspi DT nodes based on RCW fields */\n+\tesdhc_dspi_status_fixup(blob);\n+#else\n \t/* Enable both esdhc DT nodes for LX2160ARDB */\n \tdo_fixup_by_compat(blob, compat, \"status\", \"okay\",\n \t\t\t sizeof(\"okay\"), 1);\n-\n+#endif\n \treturn 0;\n }\n \n@@ -107,9 +187,20 @@ int checkboard(void)\n \tenum boot_src src = get_boot_src();\n \tchar buf[64];\n \tu8 sw;\n+#ifdef CONFIG_TARGET_LX2160AQDS\n+\tint clock;\n+\tstatic const char *const freq[] = {\"100\", \"125\", \"156.25\",\n+\t\t\t\t\t \"161.13\", \"322.26\", \"\", \"\", \"\",\n+\t\t\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t\t\t\t \"100 separate SSCG\"};\n+#endif\n \n \tcpu_name(buf);\n+#ifdef CONFIG_TARGET_LX2160AQDS\n+\tprintf(\"Board: %s-QDS, \", buf);\n+#else\n \tprintf(\"Board: %s-RDB, \", buf);\n+#endif\n \n \tsw = QIXIS_READ(arch);\n \tprintf(\"Board version: %c, boot from \", (sw & 0xf) - 1 + 'A');\n@@ -136,22 +227,206 @@ int checkboard(void)\n \t\t\tbreak;\n \t\t}\n \t}\n+#ifdef CONFIG_TARGET_LX2160AQDS\n+\tprintf(\"FPGA: v%d (%s), build %d\",\n+\t (int)QIXIS_READ(scver), qixis_read_tag(buf),\n+\t (int)qixis_read_minor());\n+\t/* the timestamp string contains \"\\n\" at the end */\n+\tprintf(\" on %s\", qixis_read_time(buf));\n+\n+\tputs(\"SERDES1 Reference : \");\n+\tsw = QIXIS_READ(brdcfg[2]);\n+\tclock = sw >> 4;\n+\tprintf(\"Clock1 = %sMHz \", freq[clock]);\n+\tclock = sw & 0x0f;\n+\tprintf(\"Clock2 = %sMHz\", freq[clock]);\n+\n+\tsw = QIXIS_READ(brdcfg[3]);\n+\tputs(\"\\nSERDES2 Reference : \");\n+\tclock = sw >> 4;\n+\tprintf(\"Clock1 = %sMHz \", freq[clock]);\n+\tclock = sw & 0x0f;\n+\tprintf(\"Clock2 = %sMHz\", freq[clock]);\n+\n+\tsw = QIXIS_READ(brdcfg[12]);\n+\tputs(\"\\nSERDES3 Reference : \");\n+\tclock = sw >> 4;\n+\tprintf(\"Clock1 = %sMHz Clock2 = %sMHz\\n\", freq[clock], freq[clock]);\n+#else\n \tprintf(\"FPGA: v%d.%d\\n\", QIXIS_READ(scver), QIXIS_READ(tagdata));\n \n \tputs(\"SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\\n\");\n \tputs(\"SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\\n\");\n \tputs(\"SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\\n\");\n+#endif\n \treturn 0;\n }\n \n+#ifdef CONFIG_TARGET_LX2160AQDS\n+/*\n+ * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.\n+ */\n+u8 qixis_esdhc_detect_quirk(void)\n+{\n+\t/* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)\n+\t * SDHC1 Card ID:\n+\t * Specifies the type of card installed in the SDHC1 adapter slot.\n+\t * 000= (reserved)\n+\t * 001= eMMC V4.5 adapter is installed.\n+\t * 010= SD/MMC 3.3V adapter is installed.\n+\t * 011= eMMC V4.4 adapter is installed.\n+\t * 100= eMMC V5.0 adapter is installed.\n+\t * 101= MMC card/Legacy (3.3V) adapter is installed.\n+\t * 110= SDCard V2/V3 adapter installed.\n+\t * 111= no adapter is installed.\n+\t */\n+\treturn ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=\n+\t\t QIXIS_ESDHC_NO_ADAPTER);\n+}\n+\n+int config_board_mux(void)\n+{\n+\tu8 reg11, reg5, reg13;\n+\tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n+\tu32 sdhc1_base_pmux;\n+\tu32 sdhc2_base_pmux;\n+\tu32 iic5_pmux;\n+\n+\t/* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.\n+\t * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.\n+\t * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.\n+\t * Qixis and remote systems are isolated from the I2C1 bus.\n+\t * Processor connections are still available.\n+\t * SPI2 CS2_B controls EN25S64 SPI memory device.\n+\t * SPI3 CS2_B controls EN25S64 SPI memory device.\n+\t * EC2 connects to PHY #2 using RGMII protocol.\n+\t * CLK_OUT connects to FPGA for clock measurement.\n+\t */\n+\n+\treg5 = QIXIS_READ(brdcfg[5]);\n+\treg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);\n+\tQIXIS_WRITE(brdcfg[5], reg5);\n+\n+\t/* Check RCW field sdhc1_base_pmux\n+\t * esdhc0 : sdhc1_base_pmux = 0\n+\t * dspi0 : sdhc1_base_pmux = 2\n+\t */\n+\tsdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])\n+\t\t& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;\n+\tsdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;\n+\n+\tif (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {\n+\t\treg11 = QIXIS_READ(brdcfg[11]);\n+\t\treg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);\n+\t\tQIXIS_WRITE(brdcfg[11], reg11);\n+\t} else {\n+\t\t/* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.\n+\t\t * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.\n+\t\t * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.\n+\t\t */\n+\t\treg11 = QIXIS_READ(brdcfg[11]);\n+\t\treg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);\n+\t\tQIXIS_WRITE(brdcfg[11], reg11);\n+\t}\n+\n+\t/* Check RCW field sdhc2_base_pmux\n+\t * esdhc1 : sdhc2_base_pmux = 0 (default)\n+\t * dspi1 : sdhc2_base_pmux = 2\n+\t */\n+\tsdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])\n+\t\t& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;\n+\tsdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;\n+\n+\tif (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {\n+\t\treg13 = QIXIS_READ(brdcfg[13]);\n+\t\treg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);\n+\t\tQIXIS_WRITE(brdcfg[13], reg13);\n+\t} else {\n+\t\treg13 = QIXIS_READ(brdcfg[13]);\n+\t\treg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);\n+\t\tQIXIS_WRITE(brdcfg[13], reg13);\n+\t}\n+\n+\t/* Check RCW field IIC5 to enable dspi2 DT nodei\n+\t * dspi2: IIC5 = 3\n+\t */\n+\tiic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])\n+\t\t& FSL_CHASSIS3_IIC5_PMUX_MASK;\n+\tiic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;\n+\n+\tif (iic5_pmux == IIC5_PMUX_SPI3) {\n+\t\t/* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */\n+\t\treg11 = QIXIS_READ(brdcfg[11]);\n+\t\treg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);\n+\t\tQIXIS_WRITE(brdcfg[11], reg11);\n+\n+\t\t/* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.\n+\t\t * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.\n+\t\t * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.\n+\t\t */\n+\t\treg11 = QIXIS_READ(brdcfg[11]);\n+\t\treg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);\n+\t\tQIXIS_WRITE(brdcfg[11], reg11);\n+\t} else {\n+\t\t/* Routes {SDHC1_DAT4} to SDHC1 adapter slot */\n+\t\treg11 = QIXIS_READ(brdcfg[11]);\n+\t\treg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);\n+\t\tQIXIS_WRITE(brdcfg[11], reg11);\n+\n+\t\t/* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.\n+\t\t * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.\n+\t\t * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.\n+\t\t */\n+\t\treg11 = QIXIS_READ(brdcfg[11]);\n+\t\treg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);\n+\t\tQIXIS_WRITE(brdcfg[11], reg11);\n+\t}\n+\n+\treturn 0;\n+}\n+#else\n+int config_board_mux(void)\n+{\n+\treturn 0;\n+}\n+#endif\n+\n unsigned long get_board_sys_clk(void)\n {\n+#ifdef CONFIG_TARGET_LX2160AQDS\n+\tu8 sysclk_conf = QIXIS_READ(brdcfg[1]);\n+\n+\tswitch (sysclk_conf & 0x03) {\n+\tcase QIXIS_SYSCLK_100:\n+\t\treturn 100000000;\n+\tcase QIXIS_SYSCLK_125:\n+\t\treturn 125000000;\n+\tcase QIXIS_SYSCLK_133:\n+\t\treturn 133333333;\n+\t}\n+\treturn 100000000;\n+#else\n \treturn 100000000;\n+#endif\n }\n \n unsigned long get_board_ddr_clk(void)\n {\n+#ifdef CONFIG_TARGET_LX2160AQDS\n+\tu8 ddrclk_conf = QIXIS_READ(brdcfg[1]);\n+\n+\tswitch ((ddrclk_conf & 0x30) >> 4) {\n+\tcase QIXIS_DDRCLK_100:\n+\t\treturn 100000000;\n+\tcase QIXIS_DDRCLK_125:\n+\t\treturn 125000000;\n+\tcase QIXIS_DDRCLK_133:\n+\t\treturn 133333333;\n+\t}\n+\treturn 100000000;\n+#else\n \treturn 100000000;\n+#endif\n }\n \n int board_init(void)\n@@ -184,6 +459,8 @@ void detail_board_ddr_info(void)\n #if defined(CONFIG_ARCH_MISC_INIT)\n int arch_misc_init(void)\n {\n+\tconfig_board_mux();\n+\n \treturn 0;\n }\n #endif\ndiff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig\nnew file mode 100644\nindex 0000000000..7914dbecd5\n--- /dev/null\n+++ b/configs/lx2160aqds_tfa_defconfig\n@@ -0,0 +1,72 @@\n+CONFIG_ARM=y\n+CONFIG_TARGET_LX2160AQDS=y\n+CONFIG_SYS_TEXT_BASE=0x82000000\n+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y\n+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"fsl-lx2160a-qds\"\n+CONFIG_NR_DRAM_BANKS=3\n+CONFIG_DM=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_OF_BOARD_SETUP=y\n+CONFIG_OF_STDOUT_VIA_ALIAS=y\n+CONFIG_TFABOOT=y\n+CONFIG_BOOTDELAY=10\n+CONFIG_USE_BOOTARGS=y\n+CONFIG_BOOTARGS=\"console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf\"\n+# CONFIG_USE_BOOTCOMMAND is not set\n+CONFIG_CMD_GREPENV=y\n+CONFIG_CMD_EEPROM=y\n+CONFIG_CMD_GPT=y\n+CONFIG_CMD_I2C=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_SF=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_CACHE=y\n+CONFIG_MP=y\n+CONFIG_OF_CONTROL=y\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_DM_SERIAL=y\n+CONFIG_CONS_INDEX=0\n+CONFIG_FSL_CAAM=y\n+CONFIG_FSL_ESDHC=y\n+CONFIG_SPI=y\n+CONFIG_DM_SPI=y\n+CONFIG_DM_SPI_FLASH=y\n+CONFIG_SPI_FLASH=y\n+CONFIG_SPI_FLASH_STMICRO=y\n+CONFIG_SPI_FLASH_USE_4K_SECTORS=n\n+CONFIG_SPI_FLASH_SPANSION=y\n+CONFIG_NXP_FSPI=y\n+CONFIG_FSPI_AHB_EN_4BYTE=y\n+CONFIG_SYS_FSPI_AHB_INIT=y\n+CONFIG_PHYLIB=y\n+CONFIG_NETDEVICES=y\n+CONFIG_PHY_GIGE=y\n+CONFIG_CMD_NET=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_PXE=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_EXT2=y\n+CONFIG_NET=y\n+CONFIG_USB=y\n+CONFIG_DM_USB=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_DWC3=y\n+CONFIG_USB_STORAGE=y\n+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y\n+CONFIG_SCSI_AHCI=y\n+CONFIG_SCSI=y\n+# CONFIG_SYS_FSL_DDR_PHY is not set\n+CONFIG_SYS_GEN2_DDR_PHY=y\n+CONFIG_SYS_MALLOC_F=y\n+CONFIG_SYS_MALLOC_F_LEN=0x6000\n+CONFIG_PHYLIB_10G=y\n+CONFIG_PHY_AQUANTIA=y # X-M11-USXGMII\n+CONFIG_PHY_CORTINA=y # X-M7-40G\n+CONFIG_PHY_REALTEK=y # RGMII\n+CONFIG_PHY_INPHI=y # X-M8-100G\n+CONFIG_PHY_VITESSE=y # SGMII PEX RISER\n+CONFIG_HUSH_PARSER=y\ndiff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h\nnew file mode 100644\nindex 0000000000..82cd471a8e\n--- /dev/null\n+++ b/include/configs/lx2160aqds.h\n@@ -0,0 +1,140 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2018-2019 NXP\n+ */\n+\n+#ifndef __LX2_QDS_H\n+#define __LX2_QDS_H\n+\n+#include \"lx2160a_common.h\"\n+\n+/* Qixis */\n+#define QIXIS_XMAP_MASK\t\t\t0x07\n+#define QIXIS_XMAP_SHIFT\t\t5\n+#define QIXIS_RST_CTL_RESET_EN\t\t0x30\n+#define QIXIS_LBMAP_DFLTBANK\t\t0x00\n+#define QIXIS_LBMAP_ALTBANK\t\t0x20\n+#define QIXIS_LBMAP_QSPI\t\t0x00\n+#define QIXIS_RCW_SRC_QSPI\t\t0xff\n+#define QIXIS_RST_CTL_RESET\t\t0x31\n+#define QIXIS_RCFG_CTL_RECONFIG_IDLE\t0x20\n+#define QIXIS_RCFG_CTL_RECONFIG_START\t0x21\n+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE\t0x08\n+#define QIXIS_LBMAP_MASK\t\t0x0f\n+#define QIXIS_LBMAP_SD\n+#define QIXIS_RCW_SRC_SD \t0x08\n+#define NON_EXTENDED_DUTCFG\n+#define QIXIS_SDID_MASK\t\t\t0x07\n+#define QIXIS_ESDHC_NO_ADAPTER\t\t0x7\n+\n+/* SYSCLK */\n+#define QIXIS_SYSCLK_100\t\t0x0\n+#define QIXIS_SYSCLK_125\t\t0x1\n+#define QIXIS_SYSCLK_133\t\t0x2\n+\n+/* DDRCLK */\n+#define QIXIS_DDRCLK_100\t\t0x0\n+#define QIXIS_DDRCLK_125\t\t0x1\n+#define QIXIS_DDRCLK_133\t\t0x2\n+\n+#define BRDCFG4_EMI1SEL_MASK\t\t0xF8\n+#define BRDCFG4_EMI1SEL_SHIFT\t\t3\n+#define BRDCFG4_EMI2SEL_MASK\t\t0x07\n+#define BRDCFG4_EMI2SEL_SHIFT\t\t0\n+\n+/* VID */\n+\n+#define I2C_MUX_CH_VOL_MONITOR\t\t0xA\n+/* Voltage monitor on channel 2*/\n+#define I2C_VOL_MONITOR_ADDR\t\t0x63\n+#define I2C_VOL_MONITOR_BUS_V_OFFSET\t0x2\n+#define I2C_VOL_MONITOR_BUS_V_OVF\t0x1\n+#define I2C_VOL_MONITOR_BUS_V_SHIFT\t3\n+#define CONFIG_VID_FLS_ENV\t\t\"lx2160aqds_vdd_mv\"\n+#define CONFIG_VID\n+\n+/* The lowest and highest voltage allowed*/\n+#define VDD_MV_MIN\t\t\t775\n+#define VDD_MV_MAX\t\t\t925\n+\n+/* PM Bus commands code for LTC3882*/\n+#define PMBUS_CMD_PAGE 0x0\n+#define PMBUS_CMD_READ_VOUT 0x8B\n+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05\n+#define PMBUS_CMD_VOUT_COMMAND 0x21\n+#define PWM_CHANNEL0 0x0\n+\n+#define CONFIG_VOL_MONITOR_LTC3882_SET\n+#define CONFIG_VOL_MONITOR_LTC3882_READ\n+\n+/* RTC */\n+#define CONFIG_SYS_RTC_BUS_NUM\t\t0\n+#define I2C_MUX_CH_RTC\t\t\t0xB\n+\n+/*\n+ * MMC\n+ */\n+#ifdef CONFIG_MMC\n+#ifndef __ASSEMBLY__\n+u8 qixis_esdhc_detect_quirk(void);\n+#endif\n+#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()\n+#endif\n+\n+/* MAC/PHY configuration */\n+#if defined(CONFIG_FSL_MC_ENET)\n+#define CONFIG_MII\n+#define CONFIG_ETHPRIME\t\t\"DPMAC17@rgmii-id\"\n+\n+#define AQ_PHY_ADDR1\t\t0x00\n+#define AQ_PHY_ADDR2\t\t0x01\n+#define AQ_PHY_ADDR3\t\t0x02\n+#define AQ_PHY_ADDR4\t\t0x03\n+\n+#define CORTINA_NO_FW_UPLOAD\n+#define CORTINA_PHY_ADDR1\t0x0\n+\n+#define INPHI_PHY_ADDR1\t\t0x0\n+#define INPHI_PHY_ADDR2\t\t0x1\n+\n+#define RGMII_PHY_ADDR1\t\t0x01\n+#define RGMII_PHY_ADDR2\t\t0x02\n+\n+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C\n+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D\n+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E\n+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F\n+\n+#endif\n+\n+/* EEPROM */\n+#define CONFIG_ID_EEPROM\n+#define CONFIG_SYS_I2C_EEPROM_NXID\n+#define CONFIG_SYS_EEPROM_BUS_NUM\t\t0\n+#define CONFIG_SYS_I2C_EEPROM_ADDR\t\t0x57\n+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN\t\t1\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS\t3\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS\t5\n+\n+/* Initial environment variables */\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\t\\\n+\tEXTRA_ENV_SETTINGS\t\t\t\\\n+\t\"lx2160aqds_vdd_mv=800\\0\"\t\t\\\n+\t\"BOARD=lx2160aqds\\0\"\t\t\t\\\n+\t\"xspi_bootcmd=echo Trying load from flexspi..;\"\t\t\\\n+\t\t\"sf probe 0:0 && sf read $load_addr \"\t\t\\\n+\t\t\"$kernel_start $kernel_size ; env exists secureboot &&\"\t\\\n+\t\t\"sf read $kernelheader_addr_r $kernelheader_start \"\t\\\n+\t\t\"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; \"\\\n+\t\t\" bootm $load_addr#$BOARD\\0\"\t\t\t\\\n+\t\"sd_bootcmd=echo Trying load from sd card..;\"\t\t\\\n+\t\t\"mmcinfo; mmc read $load_addr \"\t\t\t\\\n+\t\t\"$kernel_addr_sd $kernel_size_sd ;\"\t\t\\\n+\t\t\"env exists secureboot && mmc read $kernelheader_addr_r \"\\\n+\t\t\"$kernelhdr_addr_sd $kernelhdr_size_sd \"\t\\\n+\t\t\" && esbc_validate ${kernelheader_addr_r};\"\t\\\n+\t\t\"bootm $load_addr#$BOARD\\0\"\n+\n+#include <asm/fsl_secure_boot.h>\n+\n+#endif /* __LX2_QDS_H */\n", "prefixes": [ "U-Boot", "v6" ] }