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GET /api/patches/1037358/?format=api
{ "id": 1037358, "url": "http://patchwork.ozlabs.org/api/patches/1037358/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190206074837.4851-1-sasha.neftin@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190206074837.4851-1-sasha.neftin@intel.com>", "list_archive_url": null, "date": "2019-02-06T07:48:37", "name": "[v1,1/1] igc: Add multiple receive queues control supporting", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "2cd791f4968f3076b9ac1cbb8a2dd46147990bb7", "submitter": { "id": 69860, "url": "http://patchwork.ozlabs.org/api/people/69860/?format=api", "name": "Sasha Neftin", "email": "sasha.neftin@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190206074837.4851-1-sasha.neftin@intel.com/mbox/", "series": [ { "id": 90319, "url": "http://patchwork.ozlabs.org/api/series/90319/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=90319", "date": "2019-02-06T07:48:37", "name": "[v1,1/1] igc: Add multiple receive queues control supporting", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/90319/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1037358/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1037358/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 43vYV32jGwz9sDr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 6 Feb 2019 18:48:43 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 0460730E82;\n\tWed, 6 Feb 2019 07:48:42 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id iip3u6qx3KXb; Wed, 6 Feb 2019 07:48:40 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id EF9DB2287D;\n\tWed, 6 Feb 2019 07:48:40 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id AD5501BF866\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 6 Feb 2019 07:48:40 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id A9E6E2287D\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 6 Feb 2019 07:48:40 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id i-UAoCMt8eIv for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 6 Feb 2019 07:48:39 +0000 (UTC)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby silver.osuosl.org (Postfix) with ESMTPS id CDE9121526\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 6 Feb 2019 07:48:39 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t05 Feb 2019 23:48:39 -0800", "from ccdlinuxdev08.iil.intel.com ([143.185.161.150])\n\tby orsmga005.jf.intel.com with ESMTP; 05 Feb 2019 23:48:38 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.58,339,1544515200\"; d=\"scan'208\";a=\"297611369\"", "From": "Sasha Neftin <sasha.neftin@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 6 Feb 2019 09:48:37 +0200", "Message-Id": "<20190206074837.4851-1-sasha.neftin@intel.com>", "X-Mailer": "git-send-email 2.11.0", "Subject": "[Intel-wired-lan] [PATCH v1 1/1] igc: Add multiple receive queues\n\tcontrol supporting", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Enable the multi queues to receive.\nProgram the direction of packets to specified queuies according\nto the mode selected in the MRQC register.\nMultiple receive queues defined by filters and RSS for 4 queues.\nEnable/disable RSS hashing and also to enable multiple receive queues.\nThis patch will allow further ethtool support development.\n\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\n---\n drivers/net/ethernet/intel/igc/igc.h | 9 +++++\n drivers/net/ethernet/intel/igc/igc_defines.h | 10 ++++++\n drivers/net/ethernet/intel/igc/igc_main.c | 49 ++++++++++++++++++++++++++++\n drivers/net/ethernet/intel/igc/igc_regs.h | 5 +++\n 4 files changed, 73 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h\nindex 80faccc34cda..473a65c51382 100644\n--- a/drivers/net/ethernet/intel/igc/igc.h\n+++ b/drivers/net/ethernet/intel/igc/igc.h\n@@ -29,6 +29,7 @@ unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);\n void igc_set_flag_queue_pairs(struct igc_adapter *adapter,\n \t\t\t const u32 max_rss_queues);\n int igc_reinit_queues(struct igc_adapter *adapter);\n+void igc_write_rss_indir_tbl(struct igc_adapter *adapter);\n bool igc_has_link(struct igc_adapter *adapter);\n void igc_reset(struct igc_adapter *adapter);\n int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);\n@@ -51,6 +52,13 @@ extern char igc_driver_version[];\n #define IGC_FLAG_VLAN_PROMISC\t\tBIT(15)\n #define IGC_FLAG_RX_LEGACY\t\tBIT(16)\n \n+#define IGC_FLAG_RSS_FIELD_IPV4_UDP\tBIT(6)\n+#define IGC_FLAG_RSS_FIELD_IPV6_UDP\tBIT(7)\n+\n+#define IGC_MRQC_ENABLE_RSS_MQ\t\t0x00000002\n+#define IGC_MRQC_RSS_FIELD_IPV4_UDP\t0x00400000\n+#define IGC_MRQC_RSS_FIELD_IPV6_UDP\t0x00800000\n+\n #define IGC_START_ITR\t\t\t648 /* ~6000 ints/sec */\n #define IGC_4K_ITR\t\t\t980\n #define IGC_20K_ITR\t\t\t196\n@@ -359,6 +367,7 @@ struct igc_adapter {\n \tu32 *shadow_vfta;\n \n \tu32 rss_queues;\n+\tu32 rss_indir_tbl_init;\n \n \t/* lock for RX network flow classification filter */\n \tspinlock_t nfc_lock;\ndiff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h\nindex 7d1bdcd1225a..3666f8837cc8 100644\n--- a/drivers/net/ethernet/intel/igc/igc_defines.h\n+++ b/drivers/net/ethernet/intel/igc/igc_defines.h\n@@ -310,6 +310,12 @@\n \tIGC_RXDEXT_STATERR_CXE |\t\\\n \tIGC_RXDEXT_STATERR_RXE)\n \n+#define IGC_MRQC_RSS_FIELD_IPV4_TCP\t0x00010000\n+#define IGC_MRQC_RSS_FIELD_IPV4\t\t0x00020000\n+#define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX\t0x00040000\n+#define IGC_MRQC_RSS_FIELD_IPV6\t\t0x00100000\n+#define IGC_MRQC_RSS_FIELD_IPV6_TCP\t0x00200000\n+\n /* Header split receive */\n #define IGC_RFCTL_IPV6_EX_DIS\t0x00010000\n #define IGC_RFCTL_LEF\t\t0x00040000\n@@ -325,6 +331,10 @@\n #define I225_RXPBSIZE_DEFAULT\t0x000000A2 /* RXPBSIZE default */\n #define I225_TXPBSIZE_DEFAULT\t0x04000014 /* TXPBSIZE default */\n \n+/* Receive Checksum Control */\n+#define IGC_RXCSUM_CRCOFL\t0x00000800 /* CRC32 offload enable */\n+#define IGC_RXCSUM_PCSD\t\t0x00002000 /* packet checksum disabled */\n+\n /* GPY211 - I225 defines */\n #define GPY_MMD_MASK\t\t0xFFFF0000\n #define GPY_MMD_SHIFT\t\t16\ndiff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c\nindex 9e4afbd764ec..476d0a858bde 100644\n--- a/drivers/net/ethernet/intel/igc/igc_main.c\n+++ b/drivers/net/ethernet/intel/igc/igc_main.c\n@@ -620,6 +620,55 @@ static void igc_configure_tx(struct igc_adapter *adapter)\n */\n static void igc_setup_mrqc(struct igc_adapter *adapter)\n {\n+\tstruct igc_hw *hw = &adapter->hw;\n+\tu32 j, num_rx_queues;\n+\tu32 mrqc, rxcsum;\n+\tu32 rss_key[10];\n+\n+\tnetdev_rss_key_fill(rss_key, sizeof(rss_key));\n+\tfor (j = 0; j < 10; j++)\n+\t\twr32(IGC_RSSRK(j), rss_key[j]);\n+\n+\tnum_rx_queues = adapter->rss_queues;\n+\n+\tif (adapter->rss_indir_tbl_init != num_rx_queues) {\n+\t\tfor (j = 0; j < IGC_RETA_SIZE; j++)\n+\t\t\tadapter->rss_indir_tbl[j] =\n+\t\t\t(j * num_rx_queues) / IGC_RETA_SIZE;\n+\t\tadapter->rss_indir_tbl_init = num_rx_queues;\n+\t}\n+\tigc_write_rss_indir_tbl(adapter);\n+\n+\t/* Disable raw packet checksumming so that RSS hash is placed in\n+\t * descriptor on writeback. No need to enable TCP/UDP/IP checksum\n+\t * offloads as they are enabled by default\n+\t */\n+\trxcsum = rd32(IGC_RXCSUM);\n+\trxcsum |= IGC_RXCSUM_PCSD;\n+\n+\t/* Enable Receive Checksum Offload for SCTP */\n+\trxcsum |= IGC_RXCSUM_CRCOFL;\n+\n+\t/* Don't need to set TUOFL or IPOFL, they default to 1 */\n+\twr32(IGC_RXCSUM, rxcsum);\n+\n+\t/* Generate RSS hash based on packet types, TCP/UDP\n+\t * port numbers and/or IPv4/v6 src and dst addresses\n+\t */\n+\tmrqc = IGC_MRQC_RSS_FIELD_IPV4 |\n+\t IGC_MRQC_RSS_FIELD_IPV4_TCP |\n+\t IGC_MRQC_RSS_FIELD_IPV6 |\n+\t IGC_MRQC_RSS_FIELD_IPV6_TCP |\n+\t IGC_MRQC_RSS_FIELD_IPV6_TCP_EX;\n+\n+\tif (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP)\n+\t\tmrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP;\n+\tif (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP)\n+\t\tmrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP;\n+\n+\tmrqc |= IGC_MRQC_ENABLE_RSS_MQ;\n+\n+\twr32(IGC_MRQC, mrqc);\n }\n \n /**\ndiff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h\nindex 5afe7a8d3faf..325109cb20cc 100644\n--- a/drivers/net/ethernet/intel/igc/igc_regs.h\n+++ b/drivers/net/ethernet/intel/igc/igc_regs.h\n@@ -80,8 +80,13 @@\n /* MSI-X Table Register Descriptions */\n #define IGC_PBACL\t\t0x05B68 /* MSIx PBA Clear - R/W 1 to clear */\n \n+/* RSS registers */\n+#define IGC_MRQC\t\t0x05818 /* Multiple Receive Control - RW */\n+\n /* Redirection Table - RW Array */\n #define IGC_RETA(_i)\t\t(0x05C00 + ((_i) * 4))\n+/* RSS Random Key - RW Array */\n+#define IGC_RSSRK(_i)\t\t(0x05C80 + ((_i) * 4))\n \n /* Receive Register Descriptions */\n #define IGC_RCTL\t\t0x00100 /* Rx Control - RW */\n", "prefixes": [ "v1", "1/1" ] }