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GET /api/patches/1034582/?format=api
{ "id": 1034582, "url": "http://patchwork.ozlabs.org/api/patches/1034582/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190201053956.19814-1-rajesh.bhagat@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190201053956.19814-1-rajesh.bhagat@nxp.com>", "list_archive_url": null, "date": "2019-02-01T05:22:01", "name": "[U-Boot] configs: fsl: move DDR specific defines to Kconfig", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "9eca522dbcc53ff6c05db822d27bea57c9679bb8", "submitter": { "id": 68498, "url": "http://patchwork.ozlabs.org/api/people/68498/?format=api", "name": "Rajesh Bhagat", "email": "rajesh.bhagat@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190201053956.19814-1-rajesh.bhagat@nxp.com/mbox/", "series": [ { "id": 89454, "url": "http://patchwork.ozlabs.org/api/series/89454/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=89454", "date": "2019-02-01T05:22:01", "name": "[U-Boot] configs: fsl: move DDR specific defines to Kconfig", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/89454/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1034582/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1034582/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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<priyanka.jain@nxp.com>,\n\tAlison Wang <alison.wang@nxp.com>, \n\t\"paul.gortmaker@windriver.com\" <paul.gortmaker@windriver.com>,\n\t\"arcsupport@arcturusnetworks.com\" <arcsupport@arcturusnetworks.com>, \n\tMingkai Hu <mingkai.hu@nxp.com>", "Subject": "[U-Boot] [PATCH] configs: fsl: move DDR specific defines to Kconfig", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Moves below DDR specific defines to Kconfig:\n\nCONFIG_FSL_DDR_BIST\nCONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE\nCONFIG_FSL_DDR_INTERACTIVE\nCONFIG_FSL_DDR_SYNC_REFRESH\n\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\n---\n arch/arm/Kconfig | 14 ++++++++++++++\n arch/powerpc/cpu/mpc85xx/Kconfig | 13 +++++++++++++\n arch/powerpc/cpu/mpc86xx/Kconfig | 1 +\n drivers/ddr/fsl/Kconfig | 12 ++++++++++++\n include/configs/B4860QDS.h | 3 ---\n include/configs/BSC9132QDS.h | 1 -\n include/configs/MPC8536DS.h | 1 -\n include/configs/MPC8540ADS.h | 1 -\n include/configs/MPC8541CDS.h | 1 -\n include/configs/MPC8544DS.h | 1 -\n include/configs/MPC8548CDS.h | 1 -\n include/configs/MPC8555CDS.h | 1 -\n include/configs/MPC8560ADS.h | 1 -\n include/configs/MPC8568MDS.h | 1 -\n include/configs/MPC8569MDS.h | 1 -\n include/configs/MPC8572DS.h | 1 -\n include/configs/MPC8610HPCD.h | 1 -\n include/configs/MPC8641HPCN.h | 1 -\n include/configs/P1023RDB.h | 1 -\n include/configs/T102xRDB.h | 1 -\n include/configs/T1040QDS.h | 1 -\n include/configs/T208xQDS.h | 2 --\n include/configs/T208xRDB.h | 1 -\n include/configs/T4240RDB.h | 1 -\n include/configs/UCP1020.h | 1 -\n include/configs/km/kmp204x-common.h | 1 -\n include/configs/ls1021aqds.h | 1 -\n include/configs/ls1043aqds.h | 4 ----\n include/configs/ls1043ardb.h | 2 --\n include/configs/ls1046aqds.h | 4 ----\n include/configs/ls1046ardb.h | 4 ----\n include/configs/ls1088a_common.h | 4 ----\n include/configs/ls2080a_common.h | 3 ---\n include/configs/ls2080a_emu.h | 2 --\n include/configs/ls2080aqds.h | 3 ---\n include/configs/ls2080ardb.h | 2 --\n include/configs/p1_p2_rdb_pc.h | 1 -\n include/configs/sbc8548.h | 1 -\n include/configs/socrates.h | 1 -\n include/configs/t4qds.h | 1 -\n include/configs/xpedite520x.h | 1 -\n include/configs/xpedite537x.h | 1 -\n scripts/config_whitelist.txt | 4 ----\n 43 files changed, 40 insertions(+), 64 deletions(-)", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex cefa8f40d0..829b34787a 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -998,6 +998,7 @@ config TARGET_LS2080A_EMU\n \tselect ARCH_MISC_INIT\n \tselect ARM64\n \tselect ARMV8_MULTIENTRY\n+\tselect FSL_DDR_SYNC_REFRESH\n \thelp\n \t Support for Freescale LS2080A_EMU platform\n \t The LS2080A Development System (EMULATOR) is a pre silicon\n@@ -1024,6 +1025,7 @@ config TARGET_LS1088AQDS\n \tselect ARMV8_MULTIENTRY\n \tselect BOARD_LATE_INIT\n \tselect SUPPORT_SPL\n+\tselect FSL_DDR_INTERACTIVE if !SD_BOOT\n \thelp\n \t Support for NXP LS1088AQDS platform\n \t The LS1088A Development System (QDS) is a high-performance\n@@ -1040,6 +1042,8 @@ config TARGET_LS2080AQDS\n \tselect SUPPORT_SPL\n \timply SCSI\n \timply SCSI_AHCI\n+\tselect FSL_DDR_BIST\n+\tselect FSL_DDR_INTERACTIVE if !SPL\n \thelp\n \t Support for Freescale LS2080AQDS platform\n \t The LS2080A Development System (QDS) is a high-performance\n@@ -1054,6 +1058,8 @@ config TARGET_LS2080ARDB\n \tselect ARMV8_MULTIENTRY\n \tselect BOARD_LATE_INIT\n \tselect SUPPORT_SPL\n+\tselect FSL_DDR_BIST\n+\tselect FSL_DDR_INTERACTIVE if !SPL\n \timply SCSI\n \timply SCSI_AHCI\n \thelp\n@@ -1172,6 +1178,7 @@ config TARGET_LS1088ARDB\n \tselect ARMV8_MULTIENTRY\n \tselect BOARD_LATE_INIT\n \tselect SUPPORT_SPL\n+\tselect FSL_DDR_INTERACTIVE if !SD_BOOT\n \thelp\n \t Support for NXP LS1088ARDB platform.\n \t The LS1088A Reference design board (RDB) is a high-performance\n@@ -1190,6 +1197,7 @@ config TARGET_LS1021AQDS\n \tselect LS1_DEEP_SLEEP\n \tselect SUPPORT_SPL\n \tselect SYS_FSL_DDR\n+\tselect FSL_DDR_INTERACTIVE\n \timply SCSI\n \n config TARGET_LS1021ATWR\n@@ -1229,6 +1237,7 @@ config TARGET_LS1043AQDS\n \tselect BOARD_EARLY_INIT_F\n \tselect BOARD_LATE_INIT\n \tselect SUPPORT_SPL\n+\tselect FSL_DDR_INTERACTIVE if !SPL\n \timply SCSI\n \thelp\n \t Support for Freescale LS1043AQDS platform.\n@@ -1241,6 +1250,8 @@ config TARGET_LS1043ARDB\n \tselect BOARD_EARLY_INIT_F\n \tselect BOARD_LATE_INIT\n \tselect SUPPORT_SPL\n+\tselect FSL_DDR_BIST if !SPL\n+\tselect FSL_DDR_INTERACTIVE if !SPL\n \timply SCSI\n \thelp\n \t Support for Freescale LS1043ARDB platform.\n@@ -1254,6 +1265,7 @@ config TARGET_LS1046AQDS\n \tselect BOARD_LATE_INIT\n \tselect DM_SPI_FLASH if DM_SPI\n \tselect SUPPORT_SPL\n+\tselect FSL_DDR_INTERACTIVE if !SPL\n \timply SCSI\n \thelp\n \t Support for Freescale LS1046AQDS platform.\n@@ -1271,6 +1283,8 @@ config TARGET_LS1046ARDB\n \tselect DM_SPI_FLASH if DM_SPI\n \tselect POWER_MC34VR500\n \tselect SUPPORT_SPL\n+\tselect FSL_DDR_BIST\n+\tselect FSL_DDR_INTERACTIVE if !SPL\n \timply SCSI\n \thelp\n \t Support for Freescale LS1046ARDB platform.\ndiff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig\nindex 309ca29460..0057f195b3 100644\n--- a/arch/powerpc/cpu/mpc85xx/Kconfig\n+++ b/arch/powerpc/cpu/mpc85xx/Kconfig\n@@ -37,6 +37,7 @@ config TARGET_B4860QDS\n \tselect BOARD_LATE_INIT if CHAIN_OF_TRUST\n \tselect SUPPORT_SPL\n \tselect PHYS_64BIT\n+\tselect FSL_DDR_INTERACTIVE if !SPL_BUILD\n \timply PANIC_HANG\n \n config TARGET_BSC9131RDB\n@@ -51,6 +52,7 @@ config TARGET_BSC9132QDS\n \tselect BOARD_LATE_INIT if CHAIN_OF_TRUST\n \tselect SUPPORT_SPL\n \tselect BOARD_EARLY_INIT_F\n+\tselect FSL_DDR_INTERACTIVE\n \n config TARGET_C29XPCIE\n \tbool \"Support C29XPCIE\"\n@@ -165,6 +167,7 @@ config TARGET_P1022DS\n config TARGET_P1023RDB\n \tbool \"Support P1023RDB\"\n \tselect ARCH_P1023\n+\tselect FSL_DDR_INTERACTIVE\n \timply CMD_EEPROM\n \timply PANIC_HANG\n \n@@ -273,6 +276,7 @@ config TARGET_T1023RDB\n \tselect BOARD_LATE_INIT if CHAIN_OF_TRUST\n \tselect SUPPORT_SPL\n \tselect PHYS_64BIT\n+\tselect FSL_DDR_INTERACTIVE\n \timply CMD_EEPROM\n \timply PANIC_HANG\n \n@@ -282,6 +286,7 @@ config TARGET_T1024RDB\n \tselect BOARD_LATE_INIT if CHAIN_OF_TRUST\n \tselect SUPPORT_SPL\n \tselect PHYS_64BIT\n+\tselect FSL_DDR_INTERACTIVE\n \timply CMD_EEPROM\n \timply PANIC_HANG\n \n@@ -290,6 +295,7 @@ config TARGET_T1040QDS\n \tselect ARCH_T1040\n \tselect BOARD_LATE_INIT if CHAIN_OF_TRUST\n \tselect PHYS_64BIT\n+\tselect FSL_DDR_INTERACTIVE\n \timply CMD_EEPROM\n \timply CMD_SATA\n \timply PANIC_HANG\n@@ -344,6 +350,8 @@ config TARGET_T2080QDS\n \tselect BOARD_LATE_INIT if CHAIN_OF_TRUST\n \tselect SUPPORT_SPL\n \tselect PHYS_64BIT\n+\tselect FSL_DDR_FIRST_SLOT_QUAD_CAPABLE\n+\tselect FSL_DDR_INTERACTIVE\n \timply CMD_SATA\n \n config TARGET_T2080RDB\n@@ -360,6 +368,8 @@ config TARGET_T2081QDS\n \tselect ARCH_T2081\n \tselect SUPPORT_SPL\n \tselect PHYS_64BIT\n+\tselect FSL_DDR_FIRST_SLOT_QUAD_CAPABLE\n+\tselect FSL_DDR_INTERACTIVE\n \n config TARGET_T4160QDS\n \tbool \"Support T4160QDS\"\n@@ -383,6 +393,7 @@ config TARGET_T4240QDS\n \tselect BOARD_LATE_INIT if CHAIN_OF_TRUST\n \tselect SUPPORT_SPL\n \tselect PHYS_64BIT\n+\tselect FSL_DDR_FIRST_SLOT_QUAD_CAPABLE\n \timply CMD_SATA\n \timply PANIC_HANG\n \n@@ -391,6 +402,7 @@ config TARGET_T4240RDB\n \tselect ARCH_T4240\n \tselect SUPPORT_SPL\n \tselect PHYS_64BIT\n+\tselect FSL_DDR_FIRST_SLOT_QUAD_CAPABLE\n \timply CMD_SATA\n \timply PANIC_HANG\n \n@@ -402,6 +414,7 @@ config TARGET_KMP204X\n \tbool \"Support kmp204x\"\n \tselect ARCH_P2041\n \tselect PHYS_64BIT\n+\tselect FSL_DDR_INTERACTIVE\n \timply CMD_CRAMFS\n \timply FS_CRAMFS\n \ndiff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig\nindex 2cc180da38..0f253051f2 100644\n--- a/arch/powerpc/cpu/mpc86xx/Kconfig\n+++ b/arch/powerpc/cpu/mpc86xx/Kconfig\n@@ -21,6 +21,7 @@ config TARGET_MPC8610HPCD\n config TARGET_MPC8641HPCN\n \tbool \"Support MPC8641HPCN\"\n \tselect ARCH_MPC8641\n+\tselect FSL_DDR_INTERACTIVE\n \timply SCSI\n \n config TARGET_XPEDITE517X\ndiff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig\nindex c5bd8a8876..1b73df82de 100644\n--- a/drivers/ddr/fsl/Kconfig\n+++ b/drivers/ddr/fsl/Kconfig\n@@ -20,6 +20,18 @@ config SYS_FSL_DDR_LE\n \thelp\n \t\tAccess DDR registers in little-endian\n \n+config FSL_DDR_BIST\n+\tbool\n+\n+config FSL_DDR_INTERACTIVE\n+\tbool\n+\n+config FSL_DDR_SYNC_REFRESH\n+\tbool\n+\n+config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE\n+\tbool\n+\n menu \"Freescale DDR controllers\"\n \tdepends on SYS_FSL_DDR\n \ndiff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h\nindex 252e1272c3..42b3337216 100644\n--- a/include/configs/B4860QDS.h\n+++ b/include/configs/B4860QDS.h\n@@ -194,9 +194,6 @@ unsigned long get_board_ddr_clk(void);\n \n #define CONFIG_DDR_SPD\n #define CONFIG_SYS_DDR_RAW_TIMING\n-#ifndef CONFIG_SPL_BUILD\n-#define CONFIG_FSL_DDR_INTERACTIVE\n-#endif\n \n #define CONFIG_SYS_SPD_BUS_NUM\t0\n #define SPD_EEPROM_ADDRESS1\t0x51\ndiff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h\nindex 49bb38279a..f385509daf 100644\n--- a/include/configs/BSC9132QDS.h\n+++ b/include/configs/BSC9132QDS.h\n@@ -105,7 +105,6 @@\n #define CONFIG_SYS_SPD_BUS_NUM\t\t0\n #define SPD_EEPROM_ADDRESS1\t\t0x54 /* I2C access */\n #define SPD_EEPROM_ADDRESS2\t\t0x56 /* I2C access */\n-#define CONFIG_FSL_DDR_INTERACTIVE\n \n #define CONFIG_MEM_INIT_VALUE\t\t0xDeadBeef\n \ndiff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h\nindex 86a1233e32..1413b3dcfe 100644\n--- a/include/configs/MPC8536DS.h\n+++ b/include/configs/MPC8536DS.h\n@@ -83,7 +83,6 @@\n \n /* DDR Setup */\n #define CONFIG_VERY_BIG_RAM\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup */\n #define CONFIG_DDR_SPD\n \ndiff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h\nindex b8a9b5c638..13ca2c395d 100644\n--- a/include/configs/MPC8540ADS.h\n+++ b/include/configs/MPC8540ADS.h\n@@ -67,7 +67,6 @@\n /* DDR Setup */\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup*/\n #define CONFIG_DDR_SPD\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n \n #define CONFIG_MEM_INIT_VALUE\t\t0xDeadBeef\n \ndiff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h\nindex 13ad04e279..e00a56e2fd 100644\n--- a/include/configs/MPC8541CDS.h\n+++ b/include/configs/MPC8541CDS.h\n@@ -41,7 +41,6 @@ extern unsigned long get_clock_freq(void);\n /* DDR Setup */\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup*/\n #define CONFIG_DDR_SPD\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n \n #define CONFIG_MEM_INIT_VALUE\t\t0xDeadBeef\n \ndiff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h\nindex 6ad0849cec..280b873aee 100644\n--- a/include/configs/MPC8544DS.h\n+++ b/include/configs/MPC8544DS.h\n@@ -45,7 +45,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);\n #define CONFIG_SYS_CCSRBAR_PHYS_LOW\tCONFIG_SYS_CCSRBAR\n \n /* DDR Setup */\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup */\n #define CONFIG_DDR_SPD\n \ndiff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h\nindex b09cbab292..be600becfe 100644\n--- a/include/configs/MPC8548CDS.h\n+++ b/include/configs/MPC8548CDS.h\n@@ -56,7 +56,6 @@ extern unsigned long get_clock_freq(void);\n #define CONFIG_SYS_CCSRBAR_PHYS_LOW\tCONFIG_SYS_CCSRBAR\n \n /* DDR Setup */\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup*/\n #define CONFIG_DDR_SPD\n \ndiff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h\nindex bac8456825..5b3933412c 100644\n--- a/include/configs/MPC8555CDS.h\n+++ b/include/configs/MPC8555CDS.h\n@@ -41,7 +41,6 @@ extern unsigned long get_clock_freq(void);\n /* DDR Setup */\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup*/\n #define CONFIG_DDR_SPD\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n \n #define CONFIG_MEM_INIT_VALUE\t\t0xDeadBeef\n \ndiff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h\nindex d28a35f87b..5ba2b6d643 100644\n--- a/include/configs/MPC8560ADS.h\n+++ b/include/configs/MPC8560ADS.h\n@@ -66,7 +66,6 @@\n /* DDR Setup */\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup*/\n #define CONFIG_DDR_SPD\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n \n #define CONFIG_MEM_INIT_VALUE\t\t0xDeadBeef\n \ndiff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h\nindex 5da70bb83e..9b3485ed4b 100644\n--- a/include/configs/MPC8568MDS.h\n+++ b/include/configs/MPC8568MDS.h\n@@ -44,7 +44,6 @@ extern unsigned long get_clock_freq(void);\n #define CONFIG_SYS_CCSRBAR_PHYS_LOW\tCONFIG_SYS_CCSRBAR\n \n /* DDR Setup */\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup*/\n #define CONFIG_DDR_SPD\n #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\t/* DDR controller or DMA? */\ndiff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h\nindex 0edcc2ed72..de5a7ca959 100644\n--- a/include/configs/MPC8569MDS.h\n+++ b/include/configs/MPC8569MDS.h\n@@ -68,7 +68,6 @@ extern unsigned long get_clock_freq(void);\n #endif\n \n /* DDR Setup */\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup*/\n #define CONFIG_DDR_SPD\n #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\t/* DDR controller or DMA? */\ndiff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h\nindex cff3ca9bce..13fbbb3044 100644\n--- a/include/configs/MPC8572DS.h\n+++ b/include/configs/MPC8572DS.h\n@@ -73,7 +73,6 @@\n \n /* DDR Setup */\n #define CONFIG_VERY_BIG_RAM\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup */\n #define CONFIG_DDR_SPD\n \ndiff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h\nindex a3f29c5f9e..b534d4758b 100644\n--- a/include/configs/MPC8610HPCD.h\n+++ b/include/configs/MPC8610HPCD.h\n@@ -72,7 +72,6 @@\n #define CONFIG_SYS_CCSRBAR_PHYS\t\tCONFIG_SYS_CCSRBAR_PHYS_LOW\n \n /* DDR Setup */\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD for DDR */\n #define CONFIG_DDR_SPD\n \ndiff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h\nindex bb6dd95d59..9318b190ae 100644\n--- a/include/configs/MPC8641HPCN.h\n+++ b/include/configs/MPC8641HPCN.h\n@@ -97,7 +97,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);\n /*\n * DDR Setup\n */\n-#define CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup */\n #define CONFIG_DDR_SPD\n \ndiff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h\nindex ada00ae8bb..4f6ee22385 100644\n--- a/include/configs/P1023RDB.h\n+++ b/include/configs/P1023RDB.h\n@@ -59,7 +59,6 @@ extern unsigned long get_clock_freq(void);\n #define CONFIG_CHIP_SELECTS_PER_CTRL\t1\n \n #define CONFIG_DDR_SPD\n-#define CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SYS_SDRAM_SIZE\t\t512u\t/* DDR is 512M */\n #define CONFIG_SYS_SPD_BUS_NUM 0\n #define SPD_EEPROM_ADDRESS 0x50\ndiff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h\nindex 673d1112e2..2a0d4cf230 100644\n--- a/include/configs/T102xRDB.h\n+++ b/include/configs/T102xRDB.h\n@@ -236,7 +236,6 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_SDRAM_BASE\t\tCONFIG_SYS_DDR_SDRAM_BASE\n #define CONFIG_DIMM_SLOTS_PER_CTLR\t1\n #define CONFIG_CHIP_SELECTS_PER_CTRL\t(4 * CONFIG_DIMM_SLOTS_PER_CTLR)\n-#define CONFIG_FSL_DDR_INTERACTIVE\n #if defined(CONFIG_TARGET_T1024RDB)\n #define CONFIG_DDR_SPD\n #define CONFIG_SYS_SPD_BUS_NUM\t0\ndiff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h\nindex 2d5c96f335..147ef71084 100644\n--- a/include/configs/T1040QDS.h\n+++ b/include/configs/T1040QDS.h\n@@ -140,7 +140,6 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_CHIP_SELECTS_PER_CTRL\t(2 * CONFIG_DIMM_SLOTS_PER_CTLR)\n \n #define CONFIG_DDR_SPD\n-#define CONFIG_FSL_DDR_INTERACTIVE\n \n #define CONFIG_SYS_SPD_BUS_NUM\t0\n #define SPD_EEPROM_ADDRESS\t0x51\ndiff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h\nindex 1dcf2779d7..2da0fe09d2 100644\n--- a/include/configs/T208xQDS.h\n+++ b/include/configs/T208xQDS.h\n@@ -189,9 +189,7 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_SDRAM_BASE\t\tCONFIG_SYS_DDR_SDRAM_BASE\n #define CONFIG_DIMM_SLOTS_PER_CTLR\t2\n #define CONFIG_CHIP_SELECTS_PER_CTRL\t(2 * CONFIG_DIMM_SLOTS_PER_CTLR)\n-#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE\n #define CONFIG_DDR_SPD\n-#define CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SYS_SPD_BUS_NUM\t0\n #define CONFIG_SYS_SDRAM_SIZE\t2048\t/* for fixed parameter use */\n #define SPD_EEPROM_ADDRESS1\t0x51\ndiff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h\nindex ddb60b3d6d..656ad5317b 100644\n--- a/include/configs/T208xRDB.h\n+++ b/include/configs/T208xRDB.h\n@@ -175,7 +175,6 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_DIMM_SLOTS_PER_CTLR\t1\n #define CONFIG_CHIP_SELECTS_PER_CTRL\t(4 * CONFIG_DIMM_SLOTS_PER_CTLR)\n #define CONFIG_DDR_SPD\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SYS_SPD_BUS_NUM\t0\n #define CONFIG_SYS_SDRAM_SIZE\t2048\t/* for fixed parameter use */\n #define SPD_EEPROM_ADDRESS1\t0x51\ndiff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h\nindex 42252c7c42..f42a4f4af0 100644\n--- a/include/configs/T4240RDB.h\n+++ b/include/configs/T4240RDB.h\n@@ -112,7 +112,6 @@\n \n #define CONFIG_DIMM_SLOTS_PER_CTLR\t1\n #define CONFIG_CHIP_SELECTS_PER_CTRL\t4\n-#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE\n \n #define CONFIG_DDR_SPD\n \ndiff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h\nindex 1bbe9d9b37..6a0254a55b 100644\n--- a/include/configs/UCP1020.h\n+++ b/include/configs/UCP1020.h\n@@ -133,7 +133,6 @@\n #define CONFIG_DDR_SPD\n #endif\n #define CONFIG_SYS_SPD_BUS_NUM 1\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n \n #define CONFIG_SYS_SDRAM_SIZE_LAW\tLAW_SIZE_512M\n #define CONFIG_CHIP_SELECTS_PER_CTRL\t1\ndiff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h\nindex a8f7300c1e..948bb8de49 100644\n--- a/include/configs/km/kmp204x-common.h\n+++ b/include/configs/km/kmp204x-common.h\n@@ -94,7 +94,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);\n #define CONFIG_CHIP_SELECTS_PER_CTRL\t(4 * CONFIG_DIMM_SLOTS_PER_CTLR)\n \n #define CONFIG_DDR_SPD\n-#define CONFIG_FSL_DDR_INTERACTIVE\n \n #define CONFIG_SYS_SPD_BUS_NUM\t0\n #define SPD_EEPROM_ADDRESS\t0x54\ndiff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h\nindex 4ad98c69e6..d75ac4e57e 100644\n--- a/include/configs/ls1021aqds.h\n+++ b/include/configs/ls1021aqds.h\n@@ -89,7 +89,6 @@ unsigned long get_board_ddr_clk(void);\n #define SPD_EEPROM_ADDRESS\t\t0x51\n #define CONFIG_SYS_SPD_BUS_NUM\t\t0\n \n-#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n #ifndef CONFIG_SYS_FSL_DDR4\n #define CONFIG_SYS_DDR_RAW_TIMING\n #endif\ndiff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h\nindex ed07d9f28e..52b47ad670 100644\n--- a/include/configs/ls1043aqds.h\n+++ b/include/configs/ls1043aqds.h\n@@ -28,10 +28,6 @@ unsigned long get_board_ddr_clk(void);\n #define SPD_EEPROM_ADDRESS\t\t0x51\n #define CONFIG_SYS_SPD_BUS_NUM\t\t0\n \n-#ifndef CONFIG_SPL\n-#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n-#endif\n-\n #define CONFIG_DDR_ECC\n #ifdef CONFIG_DDR_ECC\n #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\ndiff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h\nindex a0d39878b8..6ab83d02a4 100644\n--- a/include/configs/ls1043ardb.h\n+++ b/include/configs/ls1043ardb.h\n@@ -21,8 +21,6 @@\n \n #ifndef CONFIG_SPL\n #define CONFIG_SYS_DDR_RAW_TIMING\n-#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n-#define CONFIG_FSL_DDR_BIST\n #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\n #define CONFIG_MEM_INIT_VALUE 0xdeadbeef\n #endif\ndiff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h\nindex 886fe723ba..6e36baf4ca 100644\n--- a/include/configs/ls1046aqds.h\n+++ b/include/configs/ls1046aqds.h\n@@ -28,10 +28,6 @@ unsigned long get_board_ddr_clk(void);\n #define SPD_EEPROM_ADDRESS\t\t0x51\n #define CONFIG_SYS_SPD_BUS_NUM\t\t0\n \n-#ifndef CONFIG_SPL\n-#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n-#endif\n-\n #define CONFIG_DDR_ECC\n #ifdef CONFIG_DDR_ECC\n #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\ndiff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h\nindex 77b50dbdad..f22e863749 100644\n--- a/include/configs/ls1046ardb.h\n+++ b/include/configs/ls1046ardb.h\n@@ -24,10 +24,6 @@\n #define CONFIG_DDR_ECC\n #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\n #define CONFIG_MEM_INIT_VALUE 0xdeadbeef\n-#define CONFIG_FSL_DDR_BIST\t/* enable built-in memory test */\n-#ifndef CONFIG_SPL\n-#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n-#endif\n \n #ifdef CONFIG_SD_BOOT\n #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg\ndiff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h\nindex 95e6786e6c..e55c23631e 100644\n--- a/include/configs/ls1088a_common.h\n+++ b/include/configs/ls1088a_common.h\n@@ -49,10 +49,6 @@\n \n #define CONFIG_SKIP_LOWLEVEL_INIT\n \n-#if !defined(CONFIG_SD_BOOT)\n-#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n-#endif\n-\n #define CONFIG_VERY_BIG_RAM\n #define CONFIG_SYS_DDR_SDRAM_BASE\t0x80000000UL\n #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY\t0\ndiff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h\nindex 235a757f75..a248e13443 100644\n--- a/include/configs/ls2080a_common.h\n+++ b/include/configs/ls2080a_common.h\n@@ -36,9 +36,6 @@\n \n #define CONFIG_SKIP_LOWLEVEL_INIT\n \n-#ifndef CONFIG_SPL\n-#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n-#endif\n #ifndef CONFIG_SYS_FSL_DDR4\n #define CONFIG_SYS_DDR_RAW_TIMING\n #endif\ndiff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h\nindex 76ac5363c5..d5cb3e4df9 100644\n--- a/include/configs/ls2080a_emu.h\n+++ b/include/configs/ls2080a_emu.h\n@@ -24,8 +24,6 @@\n #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR\t1\n #endif\n \n-#define CONFIG_FSL_DDR_SYNC_REFRESH\n-\n #define CONFIG_SYS_NOR0_CSPR_EXT\t(0x0)\n #define CONFIG_SYS_NOR_AMASK\tIFC_AMASK(128*1024*1024)\n /*\ndiff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h\nindex 2822811da5..df648e2675 100644\n--- a/include/configs/ls2080aqds.h\n+++ b/include/configs/ls2080aqds.h\n@@ -42,7 +42,6 @@ unsigned long get_board_ddr_clk(void);\n #ifdef CONFIG_SYS_FSL_HAS_DP_DDR\n #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR\t1\n #endif\n-#define CONFIG_FSL_DDR_BIST\t/* enable built-in memory test */\n \n /* SATA */\n #define CONFIG_SCSI_AHCI_PLAT\n@@ -64,8 +63,6 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_ENV_SECT_SIZE\t\t0x20000\n #endif\n \n-/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */\n-\n #define CONFIG_SYS_NOR0_CSPR_EXT\t(0x0)\n #define CONFIG_SYS_NOR_AMASK\t\tIFC_AMASK(128*1024*1024)\n #define CONFIG_SYS_NOR_AMASK_EARLY\tIFC_AMASK(64*1024*1024)\ndiff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h\nindex ef0f4ff48e..e10afae6d7 100644\n--- a/include/configs/ls2080ardb.h\n+++ b/include/configs/ls2080ardb.h\n@@ -57,7 +57,6 @@ unsigned long get_board_sys_clk(void);\n #ifdef CONFIG_SYS_FSL_HAS_DP_DDR\n #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR\t1\n #endif\n-#define CONFIG_FSL_DDR_BIST\t/* enable built-in memory test */\n \n /* SATA */\n #define CONFIG_SCSI_AHCI_PLAT\n@@ -80,7 +79,6 @@ unsigned long get_board_sys_clk(void);\n #endif\n \n #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)\n-/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */\n \n #define CONFIG_SYS_NOR0_CSPR_EXT\t(0x0)\n #define CONFIG_SYS_NOR_AMASK\t\tIFC_AMASK(128*1024*1024)\ndiff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h\nindex 459ecf328f..2af10a2b75 100644\n--- a/include/configs/p1_p2_rdb_pc.h\n+++ b/include/configs/p1_p2_rdb_pc.h\n@@ -264,7 +264,6 @@\n #define CONFIG_DDR_SPD\n #define CONFIG_SYS_SPD_BUS_NUM 1\n #define SPD_EEPROM_ADDRESS 0x52\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n \n #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))\n #define CONFIG_SYS_SDRAM_SIZE_LAW\tLAW_SIZE_2G\ndiff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h\nindex f0b165591c..9df8604af7 100644\n--- a/include/configs/sbc8548.h\n+++ b/include/configs/sbc8548.h\n@@ -83,7 +83,6 @@\n #define CONFIG_SYS_CCSRBAR_PHYS_LOW\tCONFIG_SYS_CCSRBAR\n \n /* DDR Setup */\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #undef CONFIG_DDR_ECC\t\t\t/* only for ECC DDR module */\n /*\n * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD\ndiff --git a/include/configs/socrates.h b/include/configs/socrates.h\nindex 9fa8917a9b..3f84fabdb6 100644\n--- a/include/configs/socrates.h\n+++ b/include/configs/socrates.h\n@@ -60,7 +60,6 @@\n #define CONFIG_SYS_CCSRBAR_PHYS_LOW\tCONFIG_SYS_CCSRBAR\n \n /* DDR Setup */\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup */\n #define CONFIG_DDR_SPD\n \ndiff --git a/include/configs/t4qds.h b/include/configs/t4qds.h\nindex bca5961206..bf37501912 100644\n--- a/include/configs/t4qds.h\n+++ b/include/configs/t4qds.h\n@@ -73,7 +73,6 @@\n \n #define CONFIG_DIMM_SLOTS_PER_CTLR\t2\n #define CONFIG_CHIP_SELECTS_PER_CTRL\t4\n-#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE\n \n #define CONFIG_DDR_SPD\n \ndiff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h\nindex 206f0c13a4..5737cfee95 100644\n--- a/include/configs/xpedite520x.h\n+++ b/include/configs/xpedite520x.h\n@@ -25,7 +25,6 @@\n /*\n * DDR config\n */\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup */\n #define CONFIG_DDR_SPD\n #define CONFIG_MEM_INIT_VALUE\t\t0xdeadbeef\ndiff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h\nindex e6eea8dfc2..22dd3c036e 100644\n--- a/include/configs/xpedite537x.h\n+++ b/include/configs/xpedite537x.h\n@@ -33,7 +33,6 @@\n /*\n * DDR config\n */\n-#undef CONFIG_FSL_DDR_INTERACTIVE\n #define CONFIG_SPD_EEPROM\t\t/* Use SPD EEPROM for DDR setup */\n #define CONFIG_DDR_SPD\n #define CONFIG_MEM_INIT_VALUE\t\t0xdeadbeef\ndiff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt\nindex 8c88031546..a4e73ae56b 100644\n--- a/scripts/config_whitelist.txt\n+++ b/scripts/config_whitelist.txt\n@@ -627,10 +627,6 @@ CONFIG_FSL_CADMUS\n CONFIG_FSL_CORENET\n CONFIG_FSL_CPLD\n CONFIG_FSL_DCU_SII9022A\n-CONFIG_FSL_DDR_BIST\n-CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE\n-CONFIG_FSL_DDR_INTERACTIVE\n-CONFIG_FSL_DDR_SYNC_REFRESH\n CONFIG_FSL_DEEP_SLEEP\n CONFIG_FSL_DEVICE_DISABLE\n CONFIG_FSL_DIU_CH7301\n", "prefixes": [ "U-Boot" ] }