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GET /api/patches/1032839/?format=api
{ "id": 1032839, "url": "http://patchwork.ozlabs.org/api/patches/1032839/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/20190129150143.12681-7-mika.westerberg@linux.intel.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190129150143.12681-7-mika.westerberg@linux.intel.com>", "list_archive_url": null, "date": "2019-01-29T15:01:21", "name": "[06/28] thunderbolt: Configure lanes when switch is initialized", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "c4bd5ee9445dbc3456b16da147dda834ac8d13e5", "submitter": { "id": 14534, "url": "http://patchwork.ozlabs.org/api/people/14534/?format=api", "name": "Mika Westerberg", "email": "mika.westerberg@linux.intel.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/20190129150143.12681-7-mika.westerberg@linux.intel.com/mbox/", "series": [ { "id": 88859, "url": "http://patchwork.ozlabs.org/api/series/88859/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=88859", "date": "2019-01-29T15:01:18", "name": "thunderbolt: Software connection manager improvements", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/88859/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1032839/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1032839/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming-netdev@ozlabs.org", "Delivered-To": "patchwork-incoming-netdev@ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=linux.intel.com" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 43pqZ93yRrz9sDL\n\tfor <patchwork-incoming-netdev@ozlabs.org>;\n\tWed, 30 Jan 2019 02:05:53 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729267AbfA2PFp (ORCPT\n\t<rfc822;patchwork-incoming-netdev@ozlabs.org>);\n\tTue, 29 Jan 2019 10:05:45 -0500", "from mga02.intel.com ([134.134.136.20]:34504 \"EHLO mga02.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1728177AbfA2PBv (ORCPT <rfc822;netdev@vger.kernel.org>);\n\tTue, 29 Jan 2019 10:01:51 -0500", "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Jan 2019 07:01:50 -0800", "from black.fi.intel.com ([10.237.72.28])\n\tby fmsmga005.fm.intel.com with ESMTP; 29 Jan 2019 07:01:47 -0800", "by black.fi.intel.com (Postfix, from userid 1001)\n\tid 6E3273B7; Tue, 29 Jan 2019 17:01:44 +0200 (EET)" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,537,1539673200\"; d=\"scan'208\";a=\"315840510\"", "From": "Mika Westerberg <mika.westerberg@linux.intel.com>", "To": "linux-kernel@vger.kernel.org", "Cc": "Michael Jamet <michael.jamet@intel.com>,\n\tYehezkel Bernat <YehezkelShB@gmail.com>,\n\tAndreas Noever <andreas.noever@gmail.com>,\n\tLukas Wunner <lukas@wunner.de>, \"David S . Miller\" <davem@davemloft.net>,\n\tMika Westerberg <mika.westerberg@linux.intel.com>,\n\tAndy Shevchenko <andriy.shevchenko@linux.intel.com>,\n\tnetdev@vger.kernel.org", "Subject": "[PATCH 06/28] thunderbolt: Configure lanes when switch is\n\tinitialized", "Date": "Tue, 29 Jan 2019 18:01:21 +0300", "Message-Id": "<20190129150143.12681-7-mika.westerberg@linux.intel.com>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20190129150143.12681-1-mika.westerberg@linux.intel.com>", "References": "<20190129150143.12681-1-mika.westerberg@linux.intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "Thunderbolt 2 devices and beyond need to have additional bits set in\nlink controller specific registers. This includes two bits in LC_SX_CTRL\nthat tell the link controller which lane is connected and whether it is\nupstream facing or not.\n\nSigned-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>\n---\n drivers/thunderbolt/lc.c | 114 ++++++++++++++++++++++++++++++++++\n drivers/thunderbolt/switch.c | 9 +++\n drivers/thunderbolt/tb.h | 2 +\n drivers/thunderbolt/tb_regs.h | 11 ++++\n 4 files changed, 136 insertions(+)", "diff": "diff --git a/drivers/thunderbolt/lc.c b/drivers/thunderbolt/lc.c\nindex 2134a55ed837..a5dddf176546 100644\n--- a/drivers/thunderbolt/lc.c\n+++ b/drivers/thunderbolt/lc.c\n@@ -19,3 +19,117 @@ int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid)\n \t\treturn -EINVAL;\n \treturn tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4);\n }\n+\n+static int read_lc_desc(struct tb_switch *sw, u32 *desc)\n+{\n+\tif (!sw->cap_lc)\n+\t\treturn -EINVAL;\n+\treturn tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1);\n+}\n+\n+static int find_port_lc_cap(struct tb_port *port)\n+{\n+\tstruct tb_switch *sw = port->sw;\n+\tint start, phys, ret, size;\n+\tu32 desc;\n+\n+\tret = read_lc_desc(sw, &desc);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Start of port LC registers */\n+\tstart = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;\n+\tsize = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;\n+\tphys = tb_phy_port_from_link(port->port);\n+\n+\treturn sw->cap_lc + start + phys * size;\n+}\n+\n+static int tb_lc_configure_lane(struct tb_port *port, bool configure)\n+{\n+\tbool upstream = tb_is_upstream_port(port);\n+\tstruct tb_switch *sw = port->sw;\n+\tu32 ctrl, lane;\n+\tint cap, ret;\n+\n+\tif (sw->generation < 2)\n+\t\treturn 0;\n+\n+\tcap = find_port_lc_cap(port);\n+\tif (cap < 0)\n+\t\treturn cap;\n+\n+\tret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Resolve correct lane */\n+\tif (port->port % 2)\n+\t\tlane = TB_LC_SX_CTRL_L1C;\n+\telse\n+\t\tlane = TB_LC_SX_CTRL_L2C;\n+\n+\tif (configure) {\n+\t\tctrl |= lane;\n+\t\tif (upstream)\n+\t\t\tctrl |= TB_LC_SX_CTRL_UPSTREAM;\n+\t} else {\n+\t\tctrl &= ~lane;\n+\t\tif (upstream)\n+\t\t\tctrl &= ~TB_LC_SX_CTRL_UPSTREAM;\n+\t}\n+\n+\treturn tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);\n+}\n+\n+/**\n+ * tb_lc_configure_link() - Let LC know about configured link\n+ * @sw: Switch that is being added\n+ *\n+ * Informs LC of both parent switch and @sw that there is established\n+ * link between the two.\n+ */\n+int tb_lc_configure_link(struct tb_switch *sw)\n+{\n+\tstruct tb_port *up, *down;\n+\tint ret;\n+\n+\tif (!sw->config.enabled || !tb_route(sw))\n+\t\treturn 0;\n+\n+\tup = tb_upstream_port(sw);\n+\tdown = tb_port_at(tb_route(sw), tb_to_switch(sw->dev.parent));\n+\n+\t/* Configure parent link toward this switch */\n+\tret = tb_lc_configure_lane(down, true);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Configure upstream link from this switch to the parent */\n+\tret = tb_lc_configure_lane(up, true);\n+\tif (ret)\n+\t\ttb_lc_configure_lane(down, false);\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * tb_lc_unconfigure_link() - Let LC know about unconfigured link\n+ * @sw: Switch to unconfigure\n+ *\n+ * Informs LC of both parent switch and @sw that the link between the\n+ * two does not exist anymore.\n+ */\n+void tb_lc_unconfigure_link(struct tb_switch *sw)\n+{\n+\tstruct tb_port *up, *down;\n+\n+\tif (sw->is_unplugged || !sw->config.enabled || !tb_route(sw))\n+\t\treturn;\n+\n+\tup = tb_upstream_port(sw);\n+\tdown = tb_port_at(tb_route(sw), tb_to_switch(sw->dev.parent));\n+\n+\ttb_lc_configure_lane(up, false);\n+\ttb_lc_configure_lane(down, false);\n+}\ndiff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c\nindex bd96eebd8248..760332f57b5c 100644\n--- a/drivers/thunderbolt/switch.c\n+++ b/drivers/thunderbolt/switch.c\n@@ -1301,6 +1301,10 @@ int tb_switch_configure(struct tb_switch *sw)\n \tif (ret)\n \t\treturn ret;\n \n+\tret = tb_lc_configure_link(sw);\n+\tif (ret)\n+\t\treturn ret;\n+\n \treturn tb_plug_events_active(sw, true);\n }\n \n@@ -1504,6 +1508,7 @@ void tb_switch_remove(struct tb_switch *sw)\n \n \tif (!sw->is_unplugged)\n \t\ttb_plug_events_active(sw, false);\n+\ttb_lc_unconfigure_link(sw);\n \n \ttb_switch_nvm_remove(sw);\n \n@@ -1563,6 +1568,10 @@ int tb_switch_resume(struct tb_switch *sw)\n \tif (err)\n \t\treturn err;\n \n+\terr = tb_lc_configure_link(sw);\n+\tif (err)\n+\t\treturn err;\n+\n \terr = tb_plug_events_active(sw, true);\n \tif (err)\n \t\treturn err;\ndiff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h\nindex 530464b25dcb..e61c2409021d 100644\n--- a/drivers/thunderbolt/tb.h\n+++ b/drivers/thunderbolt/tb.h\n@@ -451,6 +451,8 @@ int tb_drom_read(struct tb_switch *sw);\n int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid);\n \n int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid);\n+int tb_lc_configure_link(struct tb_switch *sw);\n+void tb_lc_unconfigure_link(struct tb_switch *sw);\n \n static inline int tb_route_length(u64 route)\n {\ndiff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h\nindex 4895ae9f0b40..e0f867dad5cf 100644\n--- a/drivers/thunderbolt/tb_regs.h\n+++ b/drivers/thunderbolt/tb_regs.h\n@@ -238,6 +238,17 @@ struct tb_regs_hop {\n } __packed;\n \n /* Common link controller registers */\n+#define TB_LC_DESC\t\t\t0x02\n+#define TB_LC_DESC_SIZE_SHIFT\t\t8\n+#define TB_LC_DESC_SIZE_MASK\t\tGENMASK(15, 8)\n+#define TB_LC_DESC_PORT_SIZE_SHIFT\t16\n+#define TB_LC_DESC_PORT_SIZE_MASK\tGENMASK(27, 16)\n #define TB_LC_FUSE\t\t\t0x03\n \n+/* Link controller registers */\n+#define TB_LC_SX_CTRL\t\t\t0x96\n+#define TB_LC_SX_CTRL_L1C\t\tBIT(16)\n+#define TB_LC_SX_CTRL_L2C\t\tBIT(20)\n+#define TB_LC_SX_CTRL_UPSTREAM\t\tBIT(30)\n+\n #endif\n", "prefixes": [ "06/28" ] }