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GET /api/patches/1019108/?format=api
{ "id": 1019108, "url": "http://patchwork.ozlabs.org/api/patches/1019108/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1545989148-13582-7-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1545989148-13582-7-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-12-28T09:25:13", "name": "[PULL,06/41] target/mips: MXU: Add missing opcodes/decoding for LX* instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "633e0a87428c88e969504b3ba5a857bac34b8df2", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1545989148-13582-7-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 83742, "url": "http://patchwork.ozlabs.org/api/series/83742/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=83742", "date": "2018-12-28T09:25:09", "name": "[PULL,01/41] MAINTAINERS: target/mips: Add MIPS files under default-configs directory", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/83742/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1019108/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1019108/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=208.118.235.17; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [208.118.235.17])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 43R1k46XtHz9s2P\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 28 Dec 2018 20:34:04 +1100 (AEDT)", "from localhost ([127.0.0.1]:57793 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1gcoWo-0000PD-GM\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Dec 2018 04:34:02 -0500", "from eggs.gnu.org ([208.118.235.92]:47801)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1gcoP4-0000YJ-I4\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:26:07 -0500", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1gcoP1-00036W-EL\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:26:02 -0500", "from mx2.rt-rk.com ([89.216.37.149]:49203 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1gcoP1-00034X-13\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:25:59 -0500", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id E76B51A212F;\n\tFri, 28 Dec 2018 10:25:54 +0100 (CET)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id B13401A1DAE;\n\tFri, 28 Dec 2018 10:25:54 +0100 (CET)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Fri, 28 Dec 2018 10:25:13 +0100", "Message-Id": "<1545989148-13582-7-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1545989148-13582-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1545989148-13582-1-git-send-email-aleksandar.markovic@rt-rk.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "quoted-printable", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PULL 06/41] target/mips: MXU: Add missing\n\topcodes/decoding for LX* instructions", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, amarkovic@wavecomp.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Aleksandar Markovic <amarkovic@wavecomp.com>\n\nAdd missing opcodes and decoding engine for LXB, LXH, LXW, LXBU,\nand LXHU instructions. They were for some reason forgotten in\nprevious commits. The MXU opcode list and decoding engine should\nbe now complete.\n\nReviewed-by: Stefan Markovic <smarkovic@wavecomp.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\n---\n target/mips/translate.c | 140 +++++++++++++++++++++++++++++++++++-------------\n 1 file changed, 102 insertions(+), 38 deletions(-)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex e9c23a5..e0c8d8c 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -1663,12 +1663,21 @@ enum {\n * │ 20..18\n * ├─ 100111 ─ OPC_MXU__POOL16 ─┬─ 000 ─ OPC_MXU_D32SARW\n * │ ├─ 001 ─ OPC_MXU_S32ALN\n- * ├─ 101000 ─ OPC_MXU_LXB ├─ 010 ─ OPC_MXU_S32ALNI\n- * ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_S32NOR\n- * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_S32AND\n- * ├─ 101011 ─ OPC_MXU_S16STD ├─ 101 ─ OPC_MXU_S32OR\n- * ├─ 101100 ─ OPC_MXU_S16LDI ├─ 110 ─ OPC_MXU_S32XOR\n- * ├─ 101101 ─ OPC_MXU_S16SDI └─ 111 ─ OPC_MXU_S32LUI\n+ * │ ├─ 010 ─ OPC_MXU_S32ALNI\n+ * │ ├─ 011 ─ OPC_MXU_S32NOR\n+ * │ ├─ 100 ─ OPC_MXU_S32AND\n+ * │ ├─ 101 ─ OPC_MXU_S32OR\n+ * │ ├─ 110 ─ OPC_MXU_S32XOR\n+ * │ └─ 111 ─ OPC_MXU_S32LUI\n+ * │\n+ * │ 7..5\n+ * ├─ 101000 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_LXB\n+ * │ ├─ 001 ─ OPC_MXU_LXH\n+ * ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_LXW\n+ * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_LXBU\n+ * ├─ 101011 ─ OPC_MXU_S16STD └─ 101 ─ OPC_MXU_LXHU\n+ * ├─ 101100 ─ OPC_MXU_S16LDI\n+ * ├─ 101101 ─ OPC_MXU_S16SDI\n * ├─ 101110 ─ OPC_MXU_S32M2I\n * ├─ 101111 ─ OPC_MXU_S32I2M\n * ├─ 110000 ─ OPC_MXU_D32SLL\n@@ -1678,15 +1687,15 @@ enum {\n * ├─ 110100 ─ OPC_MXU_Q16SLL ├─ 010 ─ OPC_MXU_D32SARV\n * ├─ 110101 ─ OPC_MXU_Q16SLR ├─ 011 ─ OPC_MXU_Q16SLLV\n * │ ├─ 100 ─ OPC_MXU_Q16SLRV\n- * ├─ 110110 ─ OPC_MXU__POOL17 ─┴─ 101 ─ OPC_MXU_Q16SARV\n+ * ├─ 110110 ─ OPC_MXU__POOL18 ─┴─ 101 ─ OPC_MXU_Q16SARV\n * │\n * ├─ 110111 ─ OPC_MXU_Q16SAR\n * │ 23..22\n- * ├─ 111000 ─ OPC_MXU__POOL18 ─┬─ 00 ─ OPC_MXU_Q8MUL\n+ * ├─ 111000 ─ OPC_MXU__POOL19 ─┬─ 00 ─ OPC_MXU_Q8MUL\n * │ └─ 01 ─ OPC_MXU_Q8MULSU\n * │\n * │ 20..18\n- * ├─ 111001 ─ OPC_MXU__POOL19 ─┬─ 000 ─ OPC_MXU_Q8MOVZ\n+ * ├─ 111001 ─ OPC_MXU__POOL20 ─┬─ 000 ─ OPC_MXU_Q8MOVZ\n * │ ├─ 001 ─ OPC_MXU_Q8MOVN\n * │ ├─ 010 ─ OPC_MXU_D16MOVZ\n * │ ├─ 011 ─ OPC_MXU_D16MOVN\n@@ -1694,7 +1703,7 @@ enum {\n * │ └─ 101 ─ OPC_MXU_S32MOV\n * │\n * │ 23..22\n- * ├─ 111010 ─ OPC_MXU__POOL20 ─┬─ 00 ─ OPC_MXU_Q8MAC\n+ * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC\n * │ └─ 10 ─ OPC_MXU_Q8MACSU\n * ├─ 111011 ─ OPC_MXU_Q16SCOP\n * ├─ 111100 ─ OPC_MXU_Q8MADL\n@@ -1750,7 +1759,7 @@ enum {\n OPC_MXU_S8SDI = 0x25,\n OPC_MXU__POOL15 = 0x26,\n OPC_MXU__POOL16 = 0x27,\n- OPC_MXU_LXB = 0x28,\n+ OPC_MXU__POOL17 = 0x28,\n /* not assigned 0x29 */\n OPC_MXU_S16LDD = 0x2A,\n OPC_MXU_S16STD = 0x2B,\n@@ -1764,11 +1773,11 @@ enum {\n OPC_MXU_D32SAR = 0x33,\n OPC_MXU_Q16SLL = 0x34,\n OPC_MXU_Q16SLR = 0x35,\n- OPC_MXU__POOL17 = 0x36,\n+ OPC_MXU__POOL18 = 0x36,\n OPC_MXU_Q16SAR = 0x37,\n- OPC_MXU__POOL18 = 0x38,\n- OPC_MXU__POOL19 = 0x39,\n- OPC_MXU__POOL20 = 0x3A,\n+ OPC_MXU__POOL19 = 0x38,\n+ OPC_MXU__POOL20 = 0x39,\n+ OPC_MXU__POOL21 = 0x3A,\n OPC_MXU_Q16SCOP = 0x3B,\n OPC_MXU_Q8MADL = 0x3C,\n OPC_MXU_S32SFL = 0x3D,\n@@ -1941,6 +1950,17 @@ enum {\n * MXU pool 17\n */\n enum {\n+ OPC_MXU_LXB = 0x00,\n+ OPC_MXU_LXH = 0x01,\n+ OPC_MXU_LXW = 0x03,\n+ OPC_MXU_LXBU = 0x04,\n+ OPC_MXU_LXHU = 0x05,\n+};\n+\n+/*\n+ * MXU pool 18\n+ */\n+enum {\n OPC_MXU_D32SLLV = 0x00,\n OPC_MXU_D32SLRV = 0x01,\n OPC_MXU_D32SARV = 0x03,\n@@ -1950,7 +1970,7 @@ enum {\n };\n \n /*\n- * MXU pool 18\n+ * MXU pool 19\n */\n enum {\n OPC_MXU_Q8MUL = 0x00,\n@@ -1958,7 +1978,7 @@ enum {\n };\n \n /*\n- * MXU pool 19\n+ * MXU pool 20\n */\n enum {\n OPC_MXU_Q8MOVZ = 0x00,\n@@ -1970,7 +1990,7 @@ enum {\n };\n \n /*\n- * MXU pool 20\n+ * MXU pool 21\n */\n enum {\n OPC_MXU_Q8MAC = 0x00,\n@@ -25331,12 +25351,58 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx)\n * Decode MXU pool17\n *\n * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n+ * +-----------+---------+---------+---+---------+-----+-----------+\n+ * | SPECIAL2 | rs | rt |0 0| rd |x x x|MXU__POOL15|\n+ * +-----------+---------+---------+---+---------+-----+-----------+\n+ *\n+ */\n+static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx)\n+{\n+ uint32_t opcode = extract32(ctx->opcode, 6, 2);\n+\n+ switch (opcode) {\n+ case OPC_MXU_LXW:\n+ /* TODO: Implement emulation of LXW instruction. */\n+ MIPS_INVAL(\"OPC_MXU_LXW\");\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ case OPC_MXU_LXH:\n+ /* TODO: Implement emulation of LXH instruction. */\n+ MIPS_INVAL(\"OPC_MXU_LXH\");\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ case OPC_MXU_LXHU:\n+ /* TODO: Implement emulation of LXHU instruction. */\n+ MIPS_INVAL(\"OPC_MXU_LXHU\");\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ case OPC_MXU_LXB:\n+ /* TODO: Implement emulation of LXB instruction. */\n+ MIPS_INVAL(\"OPC_MXU_LXB\");\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ case OPC_MXU_LXBU:\n+ /* TODO: Implement emulation of LXBU instruction. */\n+ MIPS_INVAL(\"OPC_MXU_LXBU\");\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ default:\n+ MIPS_INVAL(\"decode_opc_mxu\");\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+}\n+/*\n+ *\n+ * Decode MXU pool18\n+ *\n+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n * +-----------+---------+-----+-------+-------+-------+-----------+\n- * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL17|\n+ * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL18|\n * +-----------+---------+-----+-------+-------+-------+-----------+\n *\n */\n-static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx)\n+static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx)\n {\n uint32_t opcode = extract32(ctx->opcode, 18, 3);\n \n@@ -25380,15 +25446,15 @@ static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx)\n \n /*\n *\n- * Decode MXU pool18\n+ * Decode MXU pool19\n *\n * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n * +-----------+---+---+-------+-------+-------+-------+-----------+\n- * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL18|\n+ * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL19|\n * +-----------+---+---+-------+-------+-------+-------+-----------+\n *\n */\n-static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx)\n+static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx)\n {\n uint32_t opcode = extract32(ctx->opcode, 22, 2);\n \n@@ -25406,15 +25472,15 @@ static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx)\n \n /*\n *\n- * Decode MXU pool19\n+ * Decode MXU pool20\n *\n * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n * +-----------+---------+-----+-------+-------+-------+-----------+\n- * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL19|\n+ * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL20|\n * +-----------+---------+-----+-------+-------+-------+-----------+\n *\n */\n-static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx)\n+static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx)\n {\n uint32_t opcode = extract32(ctx->opcode, 18, 3);\n \n@@ -25458,15 +25524,15 @@ static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx)\n \n /*\n *\n- * Decode MXU pool20\n+ * Decode MXU pool21\n *\n * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n * +-----------+---+---+-------+-------+-------+-------+-----------+\n- * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL20|\n+ * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL21|\n * +-----------+---+---+-------+-------+-------+-------+-----------+\n *\n */\n-static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx)\n+static void decode_opc_mxu__pool21(CPUMIPSState *env, DisasContext *ctx)\n {\n uint32_t opcode = extract32(ctx->opcode, 22, 2);\n \n@@ -25669,10 +25735,8 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)\n case OPC_MXU__POOL16:\n decode_opc_mxu__pool16(env, ctx);\n break;\n- case OPC_MXU_LXB:\n- /* TODO: Implement emulation of LXB instruction. */\n- MIPS_INVAL(\"OPC_MXU_LXB\");\n- generate_exception_end(ctx, EXCP_RI);\n+ case OPC_MXU__POOL17:\n+ decode_opc_mxu__pool17(env, ctx);\n break;\n case OPC_MXU_S16LDD:\n /* TODO: Implement emulation of S16LDD instruction. */\n@@ -25724,23 +25788,23 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)\n MIPS_INVAL(\"OPC_MXU_Q16SLR\");\n generate_exception_end(ctx, EXCP_RI);\n break;\n- case OPC_MXU__POOL17:\n- decode_opc_mxu__pool17(env, ctx);\n+ case OPC_MXU__POOL18:\n+ decode_opc_mxu__pool18(env, ctx);\n break;\n case OPC_MXU_Q16SAR:\n /* TODO: Implement emulation of Q16SAR instruction. */\n MIPS_INVAL(\"OPC_MXU_Q16SAR\");\n generate_exception_end(ctx, EXCP_RI);\n break;\n- case OPC_MXU__POOL18:\n- decode_opc_mxu__pool18(env, ctx);\n- break;\n case OPC_MXU__POOL19:\n decode_opc_mxu__pool19(env, ctx);\n break;\n case OPC_MXU__POOL20:\n decode_opc_mxu__pool20(env, ctx);\n break;\n+ case OPC_MXU__POOL21:\n+ decode_opc_mxu__pool21(env, ctx);\n+ break;\n case OPC_MXU_Q16SCOP:\n /* TODO: Implement emulation of Q16SCOP instruction. */\n MIPS_INVAL(\"OPC_MXU_Q16SCOP\");\n", "prefixes": [ "PULL", "06/41" ] }