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GET /api/patches/1016229/?format=api
{ "id": 1016229, "url": "http://patchwork.ozlabs.org/api/patches/1016229/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181219180334.1104-15-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20181219180334.1104-15-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-12-19T18:03:33", "name": "[S10,14/15] ice: Add support for new PHY types", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "4b5a0c6d4f1f41a4aa498ff51317b098ec1a19dc", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181219180334.1104-15-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 82906, "url": "http://patchwork.ozlabs.org/api/series/82906/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=82906", "date": "2018-12-19T18:03:28", "name": "Feature updates for ice", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/82906/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1016229/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1016229/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 43KjSb5C78z9s3Z\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 20 Dec 2018 05:03:59 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 1D89886429;\n\tWed, 19 Dec 2018 18:03:58 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id w1NtdCnUwlXg; Wed, 19 Dec 2018 18:03:50 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 1C176864D2;\n\tWed, 19 Dec 2018 18:03:47 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 9430E1C2A9B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:42 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 91080879CC\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:42 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id xLzY4rK5kWkI for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:37 +0000 (UTC)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 528C48798D\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:37 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Dec 2018 10:03:36 -0800", "from shasta.jf.intel.com ([10.166.241.11])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Dec 2018 10:03:35 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,373,1539673200\"; d=\"scan'208\";a=\"127400085\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 19 Dec 2018 10:03:33 -0800", "Message-Id": "<20181219180334.1104-15-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.5", "In-Reply-To": "<20181219180334.1104-1-anirudh.venkataramanan@intel.com>", "References": "<20181219180334.1104-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH S10 14/15] ice: Add support for new PHY\n\ttypes", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "This patch adds code for the detection and operation of several\nadditional PHY types that support higher link speeds.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice_adminq_cmd.h | 39 +++-\n drivers/net/ethernet/intel/ice/ice_common.c | 124 ++++++++++-\n drivers/net/ethernet/intel/ice/ice_common.h | 3 +-\n drivers/net/ethernet/intel/ice/ice_ethtool.c | 262 +++++++++++++++++++++++-\n drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h | 2 +\n drivers/net/ethernet/intel/ice/ice_sriov.c | 9 +\n drivers/net/ethernet/intel/ice/ice_type.h | 2 +\n 7 files changed, 418 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\nindex 526224ede3fa..242c78469181 100644\n--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n@@ -847,7 +847,42 @@ struct ice_aqc_get_phy_caps {\n #define ICE_PHY_TYPE_LOW_40GBASE_KR4\t\tBIT_ULL(33)\n #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC\tBIT_ULL(34)\n #define ICE_PHY_TYPE_LOW_40G_XLAUI\t\tBIT_ULL(35)\n+#define ICE_PHY_TYPE_LOW_50GBASE_CR2\t\tBIT_ULL(36)\n+#define ICE_PHY_TYPE_LOW_50GBASE_SR2\t\tBIT_ULL(37)\n+#define ICE_PHY_TYPE_LOW_50GBASE_LR2\t\tBIT_ULL(38)\n+#define ICE_PHY_TYPE_LOW_50GBASE_KR2\t\tBIT_ULL(39)\n+#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC\tBIT_ULL(40)\n+#define ICE_PHY_TYPE_LOW_50G_LAUI2\t\tBIT_ULL(41)\n+#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC\tBIT_ULL(42)\n+#define ICE_PHY_TYPE_LOW_50G_AUI2\t\tBIT_ULL(43)\n+#define ICE_PHY_TYPE_LOW_50GBASE_CP\t\tBIT_ULL(44)\n+#define ICE_PHY_TYPE_LOW_50GBASE_SR\t\tBIT_ULL(45)\n+#define ICE_PHY_TYPE_LOW_50GBASE_FR\t\tBIT_ULL(46)\n+#define ICE_PHY_TYPE_LOW_50GBASE_LR\t\tBIT_ULL(47)\n+#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4\tBIT_ULL(48)\n+#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC\tBIT_ULL(49)\n+#define ICE_PHY_TYPE_LOW_50G_AUI1\t\tBIT_ULL(50)\n+#define ICE_PHY_TYPE_LOW_100GBASE_CR4\t\tBIT_ULL(51)\n+#define ICE_PHY_TYPE_LOW_100GBASE_SR4\t\tBIT_ULL(52)\n+#define ICE_PHY_TYPE_LOW_100GBASE_LR4\t\tBIT_ULL(53)\n+#define ICE_PHY_TYPE_LOW_100GBASE_KR4\t\tBIT_ULL(54)\n+#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC\tBIT_ULL(55)\n+#define ICE_PHY_TYPE_LOW_100G_CAUI4\t\tBIT_ULL(56)\n+#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC\tBIT_ULL(57)\n+#define ICE_PHY_TYPE_LOW_100G_AUI4\t\tBIT_ULL(58)\n+#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4\tBIT_ULL(59)\n+#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4\tBIT_ULL(60)\n+#define ICE_PHY_TYPE_LOW_100GBASE_CP2\t\tBIT_ULL(61)\n+#define ICE_PHY_TYPE_LOW_100GBASE_SR2\t\tBIT_ULL(62)\n+#define ICE_PHY_TYPE_LOW_100GBASE_DR\t\tBIT_ULL(63)\n #define ICE_PHY_TYPE_LOW_MAX_INDEX\t\t63\n+/* The second set of defines is for phy_type_high. */\n+#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4\tBIT_ULL(0)\n+#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC\tBIT_ULL(1)\n+#define ICE_PHY_TYPE_HIGH_100G_CAUI2\t\tBIT_ULL(2)\n+#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC\tBIT_ULL(3)\n+#define ICE_PHY_TYPE_HIGH_100G_AUI2\t\tBIT_ULL(4)\n+#define ICE_PHY_TYPE_HIGH_MAX_INDEX\t\t19\n \n struct ice_aqc_get_phy_caps_data {\n \t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n@@ -1025,10 +1060,12 @@ struct ice_aqc_get_link_status_data {\n #define ICE_AQ_LINK_SPEED_20GB\t\tBIT(6)\n #define ICE_AQ_LINK_SPEED_25GB\t\tBIT(7)\n #define ICE_AQ_LINK_SPEED_40GB\t\tBIT(8)\n+#define ICE_AQ_LINK_SPEED_50GB\t\tBIT(9)\n+#define ICE_AQ_LINK_SPEED_100GB\t\tBIT(10)\n #define ICE_AQ_LINK_SPEED_UNKNOWN\tBIT(15)\n \t__le32 reserved3; /* Aligns next field to 8-byte boundary */\n \t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n-\t__le64 reserved4;\n+\t__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */\n };\n \n /* Set event mask command (direct 0x0613) */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex 19695749f903..ab308fc88920 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -165,8 +165,10 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,\n \tcmd->param0 |= cpu_to_le16(report_mode);\n \tstatus = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);\n \n-\tif (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP)\n+\tif (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) {\n \t\tpi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);\n+\t\tpi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);\n+\t}\n \n \treturn status;\n }\n@@ -183,6 +185,9 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n \t\treturn ICE_MEDIA_UNKNOWN;\n \n \thw_link_info = &pi->phy.link_info;\n+\tif (hw_link_info->phy_type_low && hw_link_info->phy_type_high)\n+\t\t/* If more than one media type is selected, report unknown */\n+\t\treturn ICE_MEDIA_UNKNOWN;\n \n \tif (hw_link_info->phy_type_low) {\n \t\tswitch (hw_link_info->phy_type_low) {\n@@ -196,6 +201,15 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n \t\tcase ICE_PHY_TYPE_LOW_25G_AUI_C2C:\n \t\tcase ICE_PHY_TYPE_LOW_40GBASE_SR4:\n \t\tcase ICE_PHY_TYPE_LOW_40GBASE_LR4:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_SR2:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_LR2:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_SR:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_FR:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_LR:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_SR4:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_LR4:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_SR2:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_DR:\n \t\t\treturn ICE_MEDIA_FIBER;\n \t\tcase ICE_PHY_TYPE_LOW_100BASE_TX:\n \t\tcase ICE_PHY_TYPE_LOW_1000BASE_T:\n@@ -209,6 +223,11 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n \t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR_S:\n \t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR1:\n \t\tcase ICE_PHY_TYPE_LOW_40GBASE_CR4:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_CR2:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_CP:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_CR4:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_CP2:\n \t\t\treturn ICE_MEDIA_DA;\n \t\tcase ICE_PHY_TYPE_LOW_1000BASE_KX:\n \t\tcase ICE_PHY_TYPE_LOW_2500BASE_KX:\n@@ -219,10 +238,18 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n \t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR1:\n \t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR_S:\n \t\tcase ICE_PHY_TYPE_LOW_40GBASE_KR4:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_KR2:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_KR4:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:\n+\t\t\treturn ICE_MEDIA_BACKPLANE;\n+\t\t}\n+\t} else {\n+\t\tswitch (hw_link_info->phy_type_high) {\n+\t\tcase ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:\n \t\t\treturn ICE_MEDIA_BACKPLANE;\n \t\t}\n \t}\n-\n \treturn ICE_MEDIA_UNKNOWN;\n }\n \n@@ -274,6 +301,7 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \t/* update current link status information */\n \thw_link_info->link_speed = le16_to_cpu(link_data.link_speed);\n \thw_link_info->phy_type_low = le64_to_cpu(link_data.phy_type_low);\n+\thw_link_info->phy_type_high = le64_to_cpu(link_data.phy_type_high);\n \t*hw_media_type = ice_get_media_type(pi);\n \thw_link_info->link_info = link_data.link_info;\n \thw_link_info->an_info = link_data.an_info;\n@@ -1707,16 +1735,20 @@ void ice_clear_pxe_mode(struct ice_hw *hw)\n /**\n * ice_get_link_speed_based_on_phy_type - returns link speed\n * @phy_type_low: lower part of phy_type\n+ * @phy_type_high: higher part of phy_type\n *\n- * This helper function will convert a phy_type_low to its corresponding link\n+ * This helper function will convert an entry in phy type structure\n+ * [phy_type_low, phy_type_high] to its corresponding link speed.\n+ * Note: In the structure of [phy_type_low, phy_type_high], there should\n+ * be one bit set, as this function will convert one phy type to its\n * speed.\n- * Note: In the structure of phy_type_low, there should be one bit set, as\n- * this function will convert one phy type to its speed.\n * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned\n * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned\n */\n-static u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low)\n+static u16\n+ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)\n {\n+\tu16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;\n \tu16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;\n \n \tswitch (phy_type_low) {\n@@ -1770,41 +1802,110 @@ static u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low)\n \tcase ICE_PHY_TYPE_LOW_40G_XLAUI:\n \t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;\n \t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_CR2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_SR2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_LR2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_KR2:\n+\tcase ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_50G_LAUI2:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_CP:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_SR:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_FR:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_LR:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI1:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_CR4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_SR4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_LR4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_KR4:\n+\tcase ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_100G_CAUI4:\n+\tcase ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_100G_AUI4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_CP2:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_SR2:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_DR:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;\n+\t\tbreak;\n \tdefault:\n \t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;\n \t\tbreak;\n \t}\n \n-\treturn speed_phy_type_low;\n+\tswitch (phy_type_high) {\n+\tcase ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:\n+\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2:\n+\tcase ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_HIGH_100G_AUI2:\n+\t\tspeed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;\n+\t\tbreak;\n+\tdefault:\n+\t\tspeed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;\n+\t\tbreak;\n+\t}\n+\n+\tif (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&\n+\t speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)\n+\t\treturn ICE_AQ_LINK_SPEED_UNKNOWN;\n+\telse if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&\n+\t\t speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)\n+\t\treturn ICE_AQ_LINK_SPEED_UNKNOWN;\n+\telse if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&\n+\t\t speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)\n+\t\treturn speed_phy_type_low;\n+\telse\n+\t\treturn speed_phy_type_high;\n }\n \n /**\n * ice_update_phy_type\n * @phy_type_low: pointer to the lower part of phy_type\n+ * @phy_type_high: pointer to the higher part of phy_type\n * @link_speeds_bitmap: targeted link speeds bitmap\n *\n * Note: For the link_speeds_bitmap structure, you can check it at\n * [ice_aqc_get_link_status->link_speed]. Caller can pass in\n * link_speeds_bitmap include multiple speeds.\n *\n- * The value of phy_type_low will present a certain link speed. This helper\n- * function will turn on bits in the phy_type_low based on the value of\n+ * Each entry in this [phy_type_low, phy_type_high] structure will\n+ * present a certain link speed. This helper function will turn on bits\n+ * in [phy_type_low, phy_type_high] structure based on the value of\n * link_speeds_bitmap input parameter.\n */\n-void ice_update_phy_type(u64 *phy_type_low, u16 link_speeds_bitmap)\n+void\n+ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,\n+\t\t u16 link_speeds_bitmap)\n {\n \tu16 speed = ICE_AQ_LINK_SPEED_UNKNOWN;\n+\tu64 pt_high;\n \tu64 pt_low;\n \tint index;\n \n \t/* We first check with low part of phy_type */\n \tfor (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {\n \t\tpt_low = BIT_ULL(index);\n-\t\tspeed = ice_get_link_speed_based_on_phy_type(pt_low);\n+\t\tspeed = ice_get_link_speed_based_on_phy_type(pt_low, 0);\n \n \t\tif (link_speeds_bitmap & speed)\n \t\t\t*phy_type_low |= BIT_ULL(index);\n \t}\n+\n+\t/* We then check with high part of phy_type */\n+\tfor (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {\n+\t\tpt_high = BIT_ULL(index);\n+\t\tspeed = ice_get_link_speed_based_on_phy_type(0, pt_high);\n+\n+\t\tif (link_speeds_bitmap & speed)\n+\t\t\t*phy_type_high |= BIT_ULL(index);\n+\t}\n }\n \n /**\n@@ -1936,6 +2037,7 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n \t\tif (ena_auto_link_update)\n \t\t\tcfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;\n \t\t/* Copy over all the old settings */\n+\t\tcfg.phy_type_high = pcaps->phy_type_high;\n \t\tcfg.phy_type_low = pcaps->phy_type_low;\n \t\tcfg.low_power_ctrl = pcaps->low_power_ctrl;\n \t\tcfg.eee_cap = pcaps->eee_cap;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h\nindex 81c1bb77a9fc..17e21874b75b 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.h\n+++ b/drivers/net/ethernet/intel/ice/ice_common.h\n@@ -72,7 +72,8 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,\n \t\t struct ice_aqc_get_phy_caps_data *caps,\n \t\t struct ice_sq_cd *cd);\n void\n-ice_update_phy_type(u64 *phy_type_low, u16 link_speeds_bitmap);\n+ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,\n+\t\t u16 link_speeds_bitmap);\n enum ice_status\n ice_aq_manage_mac_write(struct ice_hw *hw, u8 *mac_addr, u8 flags,\n \t\t\tstruct ice_sq_cd *cd);\ndiff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c\nindex 1f6a5f073e91..a82f0202652d 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ethtool.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c\n@@ -493,16 +493,20 @@ ice_get_ethtool_stats(struct net_device *netdev,\n * @netdev: network interface device structure\n * @ks: ethtool link ksettings struct to fill out\n */\n-static void ice_phy_type_to_ethtool(struct net_device *netdev,\n-\t\t\t\t struct ethtool_link_ksettings *ks)\n+static void\n+ice_phy_type_to_ethtool(struct net_device *netdev,\n+\t\t\tstruct ethtool_link_ksettings *ks)\n {\n \tstruct ice_netdev_priv *np = netdev_priv(netdev);\n \tstruct ice_link_status *hw_link_info;\n+\tbool need_add_adv_mode = false;\n \tstruct ice_vsi *vsi = np->vsi;\n+\tu64 phy_types_high;\n \tu64 phy_types_low;\n \n \thw_link_info = &vsi->port_info->phy.link_info;\n \tphy_types_low = vsi->port_info->phy.phy_type_low;\n+\tphy_types_high = vsi->port_info->phy.phy_type_high;\n \n \tethtool_link_ksettings_zero_link_mode(ks, supported);\n \tethtool_link_ksettings_zero_link_mode(ks, advertising);\n@@ -651,6 +655,95 @@ static void ice_phy_type_to_ethtool(struct net_device *netdev,\n \t\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n \t\t\t\t\t\t\t 40000baseLR4_Full);\n \t}\n+\tif (phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_CR2 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50G_LAUI2 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50G_AUI2 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_CP ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_SR ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50G_AUI1) {\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 50000baseCR2_Full);\n+\t\tif (hw_link_info->req_speeds & ICE_AQ_LINK_SPEED_50GB)\n+\t\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t\t 50000baseCR2_Full);\n+\t}\n+\tif (phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_KR2 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) {\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 50000baseKR2_Full);\n+\t\tif (hw_link_info->req_speeds & ICE_AQ_LINK_SPEED_50GB)\n+\t\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t\t 50000baseKR2_Full);\n+\t}\n+\tif (phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_SR2 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_LR2 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_FR ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_LR) {\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 50000baseSR2_Full);\n+\t\tif (hw_link_info->req_speeds & ICE_AQ_LINK_SPEED_50GB)\n+\t\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t\t 50000baseSR2_Full);\n+\t}\n+\tif (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_CR4 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100G_CAUI4 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100G_AUI4 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_CP2 ||\n+\t phy_types_high & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC ||\n+\t phy_types_high & ICE_PHY_TYPE_HIGH_100G_CAUI2 ||\n+\t phy_types_high & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC ||\n+\t phy_types_high & ICE_PHY_TYPE_HIGH_100G_AUI2) {\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseCR4_Full);\n+\t\tif (hw_link_info->req_speeds & ICE_AQ_LINK_SPEED_100GB)\n+\t\t\tneed_add_adv_mode = true;\n+\t}\n+\tif (need_add_adv_mode) {\n+\t\tneed_add_adv_mode = false;\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseCR4_Full);\n+\t}\n+\tif (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_SR4 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_SR2) {\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseSR4_Full);\n+\t\tif (hw_link_info->req_speeds & ICE_AQ_LINK_SPEED_100GB)\n+\t\t\tneed_add_adv_mode = true;\n+\t}\n+\tif (need_add_adv_mode) {\n+\t\tneed_add_adv_mode = false;\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseSR4_Full);\n+\t}\n+\tif (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_LR4 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_DR) {\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseLR4_ER4_Full);\n+\t\tif (hw_link_info->req_speeds & ICE_AQ_LINK_SPEED_100GB)\n+\t\t\tneed_add_adv_mode = true;\n+\t}\n+\tif (need_add_adv_mode) {\n+\t\tneed_add_adv_mode = false;\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseLR4_ER4_Full);\n+\t}\n+\tif (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_KR4 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 ||\n+\t phy_types_high & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) {\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseKR4_Full);\n+\t\tif (hw_link_info->req_speeds & ICE_AQ_LINK_SPEED_100GB)\n+\t\t\tneed_add_adv_mode = true;\n+\t}\n+\tif (need_add_adv_mode)\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseKR4_Full);\n \n \t/* Autoneg PHY types */\n \tif (phy_types_low & ICE_PHY_TYPE_LOW_100BASE_TX ||\n@@ -676,6 +769,24 @@ static void ice_phy_type_to_ethtool(struct net_device *netdev,\n \t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n \t\t\t\t\t\t Autoneg);\n \t}\n+\tif (phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_CR2 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_KR2 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_CP ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) {\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t Autoneg);\n+\t}\n+\tif (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_CR4 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_KR4 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 ||\n+\t phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_CP2) {\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t Autoneg);\n+\t}\n }\n \n #define TEST_SET_BITS_TIMEOUT\t50\n@@ -687,13 +798,15 @@ static void ice_phy_type_to_ethtool(struct net_device *netdev,\n * @ks: ethtool ksettings to fill in\n * @netdev: network interface device structure\n */\n-static void ice_get_settings_link_up(struct ethtool_link_ksettings *ks,\n-\t\t\t\t struct net_device *netdev)\n+static void\n+ice_get_settings_link_up(struct ethtool_link_ksettings *ks,\n+\t\t\t struct net_device *netdev)\n {\n \tstruct ice_netdev_priv *np = netdev_priv(netdev);\n \tstruct ethtool_link_ksettings cap_ksettings;\n \tstruct ice_link_status *link_info;\n \tstruct ice_vsi *vsi = np->vsi;\n+\tbool unrecog_phy_high = false;\n \tbool unrecog_phy_low = false;\n \n \tlink_info = &vsi->port_info->phy.link_info;\n@@ -855,14 +968,116 @@ static void ice_get_settings_link_up(struct ethtool_link_ksettings *ks,\n \t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n \t\t\t\t\t\t 40000baseKR4_Full);\n \t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_CR2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_CP:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 50000baseCR2_Full);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t 50000baseCR2_Full);\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_50G_LAUI2:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_SR:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI1:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 50000baseCR2_Full);\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_KR2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 50000baseKR2_Full);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t 50000baseKR2_Full);\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_SR2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_LR2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_FR:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_LR:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 50000baseSR2_Full);\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_CR4:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseCR4_Full);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseCR4_Full);\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_100G_CAUI4:\n+\tcase ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_100G_AUI4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseCR4_Full);\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_CP2:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseCR4_Full);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseCR4_Full);\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_SR4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_SR2:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseSR4_Full);\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_LR4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_DR:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseLR4_ER4_Full);\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_KR4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseKR4_Full);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseKR4_Full);\n+\t\tbreak;\n \tdefault:\n \t\tunrecog_phy_low = true;\n \t}\n \n-\tif (unrecog_phy_low) {\n+\tswitch (link_info->phy_type_high) {\n+\tcase ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseKR4_Full);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);\n+\t\tethtool_link_ksettings_add_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseKR4_Full);\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2:\n+\tcase ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_HIGH_100G_AUI2:\n+\t\tethtool_link_ksettings_add_link_mode(ks, supported,\n+\t\t\t\t\t\t 100000baseCR4_Full);\n+\t\tbreak;\n+\tdefault:\n+\t\tunrecog_phy_high = true;\n+\t}\n+\n+\tif (unrecog_phy_low && unrecog_phy_high) {\n \t\t/* if we got here and link is up something bad is afoot */\n-\t\tnetdev_info(netdev, \"WARNING: Unrecognized PHY_Low (0x%llx).\\n\",\n+\t\tnetdev_info(netdev,\n+\t\t\t \"WARNING: Unrecognized PHY_Low (0x%llx).\\n\",\n \t\t\t (u64)link_info->phy_type_low);\n+\t\tnetdev_info(netdev,\n+\t\t\t \"WARNING: Unrecognized PHY_High (0x%llx).\\n\",\n+\t\t\t (u64)link_info->phy_type_high);\n \t}\n \n \t/* Now that we've worked out everything that could be supported by the\n@@ -874,6 +1089,12 @@ static void ice_get_settings_link_up(struct ethtool_link_ksettings *ks,\n \tethtool_intersect_link_masks(ks, &cap_ksettings);\n \n \tswitch (link_info->link_speed) {\n+\tcase ICE_AQ_LINK_SPEED_100GB:\n+\t\tks->base.speed = SPEED_100000;\n+\t\tbreak;\n+\tcase ICE_AQ_LINK_SPEED_50GB:\n+\t\tks->base.speed = SPEED_50000;\n+\t\tbreak;\n \tcase ICE_AQ_LINK_SPEED_40GB:\n \t\tks->base.speed = SPEED_40000;\n \t\tbreak;\n@@ -1067,6 +1288,23 @@ ice_ksettings_find_adv_link_speed(const struct ethtool_link_ksettings *ks)\n \t ethtool_link_ksettings_test_link_mode(ks, advertising,\n \t\t\t\t\t\t 40000baseKR4_Full))\n \t\tadv_link_speed |= ICE_AQ_LINK_SPEED_40GB;\n+\tif (ethtool_link_ksettings_test_link_mode(ks, advertising,\n+\t\t\t\t\t\t 50000baseCR2_Full) ||\n+\t ethtool_link_ksettings_test_link_mode(ks, advertising,\n+\t\t\t\t\t\t 50000baseKR2_Full))\n+\t\tadv_link_speed |= ICE_AQ_LINK_SPEED_50GB;\n+\tif (ethtool_link_ksettings_test_link_mode(ks, advertising,\n+\t\t\t\t\t\t 50000baseSR2_Full))\n+\t\tadv_link_speed |= ICE_AQ_LINK_SPEED_50GB;\n+\tif (ethtool_link_ksettings_test_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseCR4_Full) ||\n+\t ethtool_link_ksettings_test_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseSR4_Full) ||\n+\t ethtool_link_ksettings_test_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseLR4_ER4_Full) ||\n+\t ethtool_link_ksettings_test_link_mode(ks, advertising,\n+\t\t\t\t\t\t 100000baseKR4_Full))\n+\t\tadv_link_speed |= ICE_AQ_LINK_SPEED_100GB;\n \n \treturn adv_link_speed;\n }\n@@ -1137,8 +1375,9 @@ ice_setup_autoneg(struct ice_port_info *p, struct ethtool_link_ksettings *ks,\n *\n * Set speed/duplex per media_types advertised/forced\n */\n-static int ice_set_link_ksettings(struct net_device *netdev,\n-\t\t\t\t const struct ethtool_link_ksettings *ks)\n+static int\n+ice_set_link_ksettings(struct net_device *netdev,\n+\t\t const struct ethtool_link_ksettings *ks)\n {\n \tu8 autoneg, timeout = TEST_SET_BITS_TIMEOUT, lport = 0;\n \tstruct ice_netdev_priv *np = netdev_priv(netdev);\n@@ -1150,6 +1389,7 @@ static int ice_set_link_ksettings(struct net_device *netdev,\n \tstruct ice_port_info *p;\n \tu8 autoneg_changed = 0;\n \tenum ice_status status;\n+\tu64 phy_type_high;\n \tu64 phy_type_low;\n \tint err = 0;\n \tbool linkup;\n@@ -1265,7 +1505,7 @@ static int ice_set_link_ksettings(struct net_device *netdev,\n \t\tadv_link_speed = curr_link_speed;\n \n \t/* Convert the advertise link speeds to their corresponded PHY_TYPE */\n-\tice_update_phy_type(&phy_type_low, adv_link_speed);\n+\tice_update_phy_type(&phy_type_low, &phy_type_high, adv_link_speed);\n \n \tif (!autoneg_changed && adv_link_speed == curr_link_speed) {\n \t\tnetdev_info(netdev, \"Nothing changed, exiting without setting anything.\\n\");\n@@ -1284,7 +1524,9 @@ static int ice_set_link_ksettings(struct net_device *netdev,\n \t/* set link and auto negotiation so changes take effect */\n \tconfig.caps |= ICE_AQ_PHY_ENA_LINK;\n \n-\tif (phy_type_low) {\n+\tif (phy_type_low || phy_type_high) {\n+\t\tconfig.phy_type_high = cpu_to_le64(phy_type_high) &\n+\t\t\tabilities->phy_type_high;\n \t\tconfig.phy_type_low = cpu_to_le64(phy_type_low) &\n \t\t\tabilities->phy_type_low;\n \t} else {\ndiff --git a/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h b/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h\nindex bd7c01db8c63..ef4c79b5aa32 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h\n+++ b/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h\n@@ -489,5 +489,7 @@ static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype)\n #define ICE_LINK_SPEED_20000MBPS\t20000\n #define ICE_LINK_SPEED_25000MBPS\t25000\n #define ICE_LINK_SPEED_40000MBPS\t40000\n+#define ICE_LINK_SPEED_50000MBPS\t50000\n+#define ICE_LINK_SPEED_100000MBPS\t100000\n \n #endif /* _ICE_LAN_TX_RX_H_ */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_sriov.c b/drivers/net/ethernet/intel/ice/ice_sriov.c\nindex 533b989a23e1..d2db0d04e117 100644\n--- a/drivers/net/ethernet/intel/ice/ice_sriov.c\n+++ b/drivers/net/ethernet/intel/ice/ice_sriov.c\n@@ -85,6 +85,12 @@ u32 ice_conv_link_speed_to_virtchnl(bool adv_link_support, u16 link_speed)\n \t\tcase ICE_AQ_LINK_SPEED_40GB:\n \t\t\tspeed = ICE_LINK_SPEED_40000MBPS;\n \t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_50GB:\n+\t\t\tspeed = ICE_LINK_SPEED_50000MBPS;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_100GB:\n+\t\t\tspeed = ICE_LINK_SPEED_100000MBPS;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tspeed = ICE_LINK_SPEED_UNKNOWN;\n \t\t\tbreak;\n@@ -116,6 +122,9 @@ u32 ice_conv_link_speed_to_virtchnl(bool adv_link_support, u16 link_speed)\n \t\t\tbreak;\n \t\tcase ICE_AQ_LINK_SPEED_40GB:\n \t\t\t/* fall through */\n+\t\tcase ICE_AQ_LINK_SPEED_50GB:\n+\t\t\t/* fall through */\n+\t\tcase ICE_AQ_LINK_SPEED_100GB:\n \t\t\tspeed = (u32)VIRTCHNL_LINK_SPEED_40GB;\n \t\t\tbreak;\n \t\tdefault:\ndiff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h\nindex a078e2c98871..17086d5b5c33 100644\n--- a/drivers/net/ethernet/intel/ice/ice_type.h\n+++ b/drivers/net/ethernet/intel/ice/ice_type.h\n@@ -90,6 +90,7 @@ enum ice_vsi_type {\n struct ice_link_status {\n \t/* Refer to ice_aq_phy_type for bits definition */\n \tu64 phy_type_low;\n+\tu64 phy_type_high;\n \tu16 max_frame_size;\n \tu16 link_speed;\n \tu16 req_speeds;\n@@ -118,6 +119,7 @@ struct ice_phy_info {\n \tstruct ice_link_status link_info;\n \tstruct ice_link_status link_info_old;\n \tu64 phy_type_low;\n+\tu64 phy_type_high;\n \tenum ice_media_type media_type;\n \tu8 get_link_info;\n };\n", "prefixes": [ "S10", "14/15" ] }