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GET /api/patches/1016228/?format=api
{ "id": 1016228, "url": "http://patchwork.ozlabs.org/api/patches/1016228/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181219180334.1104-12-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20181219180334.1104-12-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-12-19T18:03:30", "name": "[S10,11/15] ice: Implement getting and setting ethtool coalesce", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "d397459cc615e073e32500d4fbbdd141e1aace87", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181219180334.1104-12-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 82906, "url": "http://patchwork.ozlabs.org/api/series/82906/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=82906", "date": "2018-12-19T18:03:28", "name": "Feature updates for ice", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/82906/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1016228/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1016228/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 43KjSS2HHTz9sB5\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 20 Dec 2018 05:03:52 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id EA13022FB9;\n\tWed, 19 Dec 2018 18:03:50 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id HIxoKEJOJjAA; Wed, 19 Dec 2018 18:03:47 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 9CB422331B;\n\tWed, 19 Dec 2018 18:03:46 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 838021C2A9B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:41 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 80FE9879FC\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:41 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id YPgMdvQfr58v for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:37 +0000 (UTC)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id EA313878C4\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:36 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Dec 2018 10:03:36 -0800", "from shasta.jf.intel.com ([10.166.241.11])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Dec 2018 10:03:35 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,373,1539673200\"; d=\"scan'208\";a=\"127400082\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 19 Dec 2018 10:03:30 -0800", "Message-Id": "<20181219180334.1104-12-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.5", "In-Reply-To": "<20181219180334.1104-1-anirudh.venkataramanan@intel.com>", "References": "<20181219180334.1104-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH S10 11/15] ice: Implement getting and\n\tsetting ethtool coalesce", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Brett Creeley <brett.creeley@intel.com>\n\nThis patch includes the following ethtool operations:\n\n1. get_coalesce\n2. set_coalesce\n3. get_per_q_coalesce\n4. set_per_q_coalesce\n\nEach itr value (current_itr/target_itr) are stored on a per\nice_ring_container basis. This is because each valid ice_ring_container\ncan have 1 or more rings that are tied to the same q_vector ITR index.\n\nSigned-off-by: Brett Creeley <brett.creeley@intel.com>\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice.h | 3 +\n drivers/net/ethernet/intel/ice/ice_ethtool.c | 256 +++++++++++++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_txrx.h | 2 +\n 3 files changed, 261 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h\nindex ffe4ffe16912..ac8bf7491d08 100644\n--- a/drivers/net/ethernet/intel/ice/ice.h\n+++ b/drivers/net/ethernet/intel/ice/ice.h\n@@ -110,6 +110,9 @@ extern const char ice_drv_ver[];\n #define ice_for_each_alloc_rxq(vsi, i) \\\n \tfor ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++)\n \n+#define ice_for_each_q_vector(vsi, i) \\\n+\tfor ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++)\n+\n struct ice_tc_info {\n \tu16 qoffset;\n \tu16 qcount_tx;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c\nindex 24c8aeaea2d5..02316e32dfb3 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ethtool.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c\n@@ -1823,6 +1823,258 @@ static int ice_set_rxfh(struct net_device *netdev, const u32 *indir,\n \treturn 0;\n }\n \n+enum ice_container_type {\n+\tICE_RX_CONTAINER,\n+\tICE_TX_CONTAINER,\n+};\n+\n+/**\n+ * ice_get_rc_coalesce - get ITR values for specific ring container\n+ * @ec: ethtool structure to fill with driver's coalesce settings\n+ * @c_type: container type, RX or TX\n+ * @rc: ring container that the ITR values will come from\n+ *\n+ * Query the device for ice_ring_container specific ITR values. This is\n+ * done per ice_ring_container because each q_vector can have 1 or more rings\n+ * and all of said ring(s) will have the same ITR values.\n+ *\n+ * Returns 0 on success, negative otherwise.\n+ */\n+static int\n+ice_get_rc_coalesce(struct ethtool_coalesce *ec, enum ice_container_type c_type,\n+\t\t struct ice_ring_container *rc)\n+{\n+\tstruct ice_pf *pf = rc->ring->vsi->back;\n+\n+\tswitch (c_type) {\n+\tcase ICE_RX_CONTAINER:\n+\t\tec->use_adaptive_rx_coalesce = ITR_IS_DYNAMIC(rc->itr_setting);\n+\t\tec->rx_coalesce_usecs = rc->itr_setting & ~ICE_ITR_DYNAMIC;\n+\t\tbreak;\n+\tcase ICE_TX_CONTAINER:\n+\t\tec->use_adaptive_tx_coalesce = ITR_IS_DYNAMIC(rc->itr_setting);\n+\t\tec->tx_coalesce_usecs = rc->itr_setting & ~ICE_ITR_DYNAMIC;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_dbg(&pf->pdev->dev, \"Invalid c_type %d\\n\", c_type);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * __ice_get_coalesce - get ITR/INTRL values for the device\n+ * @netdev: pointer to the netdev associated with this query\n+ * @ec: ethtool structure to fill with driver's coalesce settings\n+ * @q_num: queue number to get the coalesce settings for\n+ */\n+static int\n+__ice_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec,\n+\t\t int q_num)\n+{\n+\tstruct ice_netdev_priv *np = netdev_priv(netdev);\n+\tint tx = -EINVAL, rx = -EINVAL;\n+\tstruct ice_vsi *vsi = np->vsi;\n+\n+\tif (q_num < 0) {\n+\t\trx = ice_get_rc_coalesce(ec, ICE_RX_CONTAINER,\n+\t\t\t\t\t &vsi->rx_rings[0]->q_vector->rx);\n+\t\ttx = ice_get_rc_coalesce(ec, ICE_TX_CONTAINER,\n+\t\t\t\t\t &vsi->tx_rings[0]->q_vector->tx);\n+\n+\t\tgoto update_coalesced_frames;\n+\t}\n+\n+\tif (q_num < vsi->num_rxq && q_num < vsi->num_txq) {\n+\t\trx = ice_get_rc_coalesce(ec, ICE_RX_CONTAINER,\n+\t\t\t\t\t &vsi->rx_rings[q_num]->q_vector->rx);\n+\t\ttx = ice_get_rc_coalesce(ec, ICE_TX_CONTAINER,\n+\t\t\t\t\t &vsi->tx_rings[q_num]->q_vector->tx);\n+\t} else if (q_num < vsi->num_rxq) {\n+\t\trx = ice_get_rc_coalesce(ec, ICE_RX_CONTAINER,\n+\t\t\t\t\t &vsi->rx_rings[q_num]->q_vector->rx);\n+\t} else if (q_num < vsi->num_txq) {\n+\t\ttx = ice_get_rc_coalesce(ec, ICE_TX_CONTAINER,\n+\t\t\t\t\t &vsi->tx_rings[q_num]->q_vector->tx);\n+\t} else {\n+\t\t/* q_num is invalid for both Rx and Tx queues */\n+\t\treturn -EINVAL;\n+\t}\n+\n+update_coalesced_frames:\n+\t/* either q_num is invalid for both Rx and Tx queues or setting coalesce\n+\t * failed completely\n+\t */\n+\tif (tx && rx)\n+\t\treturn -EINVAL;\n+\n+\tif (q_num < vsi->num_txq)\n+\t\tec->tx_max_coalesced_frames_irq = vsi->work_lmt;\n+\n+\tif (q_num < vsi->num_rxq)\n+\t\tec->rx_max_coalesced_frames_irq = vsi->work_lmt;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec)\n+{\n+\treturn __ice_get_coalesce(netdev, ec, -1);\n+}\n+\n+static int ice_get_per_q_coalesce(struct net_device *netdev, u32 q_num,\n+\t\t\t\t struct ethtool_coalesce *ec)\n+{\n+\treturn __ice_get_coalesce(netdev, ec, q_num);\n+}\n+\n+/**\n+ * ice_set_rc_coalesce - set ITR values for specific ring container\n+ * @c_type: container type, RX or TX\n+ * @ec: ethtool structure from user to update ITR settings\n+ * @rc: ring container that the ITR values will come from\n+ * @vsi: VSI associated to the ring container\n+ *\n+ * Set specific ITR values. This is done per ice_ring_container because each\n+ * q_vector can have 1 or more rings and all of said ring(s) will have the same\n+ * ITR values.\n+ *\n+ * Returns 0 on success, negative otherwise.\n+ */\n+static int\n+ice_set_rc_coalesce(enum ice_container_type c_type, struct ethtool_coalesce *ec,\n+\t\t struct ice_ring_container *rc, struct ice_vsi *vsi)\n+{\n+\tstruct ice_pf *pf = vsi->back;\n+\tu16 itr_setting;\n+\n+\tif (!rc->ring)\n+\t\treturn -EINVAL;\n+\n+\titr_setting = rc->itr_setting & ~ICE_ITR_DYNAMIC;\n+\n+\tswitch (c_type) {\n+\tcase ICE_RX_CONTAINER:\n+\t\tif (ec->rx_coalesce_usecs != itr_setting &&\n+\t\t ec->use_adaptive_rx_coalesce) {\n+\t\t\tnetdev_info(vsi->netdev,\n+\t\t\t\t \"Rx interrupt throttling cannot be changed if adaptive-rx is enabled\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tif (ec->rx_coalesce_usecs > ICE_ITR_MAX) {\n+\t\t\tnetdev_info(vsi->netdev,\n+\t\t\t\t \"Invalid value, rx-usecs range is 0-%d\\n\",\n+\t\t\t\t ICE_ITR_MAX);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tif (ec->use_adaptive_rx_coalesce) {\n+\t\t\trc->itr_setting |= ICE_ITR_DYNAMIC;\n+\t\t} else {\n+\t\t\trc->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs);\n+\t\t\trc->target_itr = ITR_TO_REG(rc->itr_setting);\n+\t\t}\n+\t\tbreak;\n+\tcase ICE_TX_CONTAINER:\n+\t\tif (ec->tx_coalesce_usecs != itr_setting &&\n+\t\t ec->use_adaptive_tx_coalesce) {\n+\t\t\tnetdev_info(vsi->netdev,\n+\t\t\t\t \"Tx interrupt throttling cannot be changed if adaptive-tx is enabled\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tif (ec->tx_coalesce_usecs > ICE_ITR_MAX) {\n+\t\t\tnetdev_info(vsi->netdev,\n+\t\t\t\t \"Invalid value, tx-usecs range is 0-%d\\n\",\n+\t\t\t\t ICE_ITR_MAX);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tif (ec->use_adaptive_tx_coalesce) {\n+\t\t\trc->itr_setting |= ICE_ITR_DYNAMIC;\n+\t\t} else {\n+\t\t\trc->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs);\n+\t\t\trc->target_itr = ITR_TO_REG(rc->itr_setting);\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_dbg(&pf->pdev->dev, \"Invalid container type %d\\n\", c_type);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+__ice_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec,\n+\t\t int q_num)\n+{\n+\tstruct ice_netdev_priv *np = netdev_priv(netdev);\n+\tint rx = -EINVAL, tx = -EINVAL;\n+\tstruct ice_vsi *vsi = np->vsi;\n+\n+\tif (q_num < 0) {\n+\t\tint i;\n+\n+\t\tice_for_each_q_vector(vsi, i) {\n+\t\t\tstruct ice_q_vector *q_vector = vsi->q_vectors[i];\n+\n+\t\t\tif (ice_set_rc_coalesce(ICE_RX_CONTAINER, ec,\n+\t\t\t\t\t\t&q_vector->rx, vsi) ||\n+\t\t\t ice_set_rc_coalesce(ICE_TX_CONTAINER, ec,\n+\t\t\t\t\t\t&q_vector->tx, vsi))\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tgoto set_work_lmt;\n+\t}\n+\n+\tif (q_num < vsi->num_rxq && q_num < vsi->num_txq) {\n+\t\trx = ice_set_rc_coalesce(ICE_RX_CONTAINER, ec,\n+\t\t\t\t\t &vsi->rx_rings[q_num]->q_vector->rx,\n+\t\t\t\t\t vsi);\n+\t\ttx = ice_set_rc_coalesce(ICE_TX_CONTAINER, ec,\n+\t\t\t\t\t &vsi->tx_rings[q_num]->q_vector->tx,\n+\t\t\t\t\t vsi);\n+\t} else if (q_num < vsi->num_rxq) {\n+\t\trx = ice_set_rc_coalesce(ICE_RX_CONTAINER, ec,\n+\t\t\t\t\t &vsi->rx_rings[q_num]->q_vector->rx,\n+\t\t\t\t\t vsi);\n+\t} else if (q_num < vsi->num_txq) {\n+\t\ttx = ice_set_rc_coalesce(ICE_TX_CONTAINER, ec,\n+\t\t\t\t\t &vsi->tx_rings[q_num]->q_vector->tx,\n+\t\t\t\t\t vsi);\n+\t}\n+\n+\t/* either q_num is invalid for both Rx and Tx queues or setting coalesce\n+\t * failed completely\n+\t */\n+\tif (rx && tx)\n+\t\treturn -EINVAL;\n+\n+set_work_lmt:\n+\tif (ec->tx_max_coalesced_frames_irq || ec->rx_max_coalesced_frames_irq)\n+\t\tvsi->work_lmt = max(ec->tx_max_coalesced_frames_irq,\n+\t\t\t\t ec->rx_max_coalesced_frames_irq);\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec)\n+{\n+\treturn __ice_set_coalesce(netdev, ec, -1);\n+}\n+\n+static int ice_set_per_q_coalesce(struct net_device *netdev, u32 q_num,\n+\t\t\t\t struct ethtool_coalesce *ec)\n+{\n+\treturn __ice_set_coalesce(netdev, ec, q_num);\n+}\n+\n static const struct ethtool_ops ice_ethtool_ops = {\n \t.get_link_ksettings\t= ice_get_link_ksettings,\n \t.set_link_ksettings\t= ice_set_link_ksettings,\n@@ -1834,6 +2086,8 @@ static const struct ethtool_ops ice_ethtool_ops = {\n \t.get_link\t\t= ethtool_op_get_link,\n \t.get_eeprom_len\t\t= ice_get_eeprom_len,\n \t.get_eeprom\t\t= ice_get_eeprom,\n+\t.get_coalesce\t\t= ice_get_coalesce,\n+\t.set_coalesce\t\t= ice_set_coalesce,\n \t.get_strings\t\t= ice_get_strings,\n \t.set_phys_id\t\t= ice_set_phys_id,\n \t.get_ethtool_stats = ice_get_ethtool_stats,\n@@ -1850,6 +2104,8 @@ static const struct ethtool_ops ice_ethtool_ops = {\n \t.get_rxfh_indir_size\t= ice_get_rxfh_indir_size,\n \t.get_rxfh\t\t= ice_get_rxfh,\n \t.set_rxfh\t\t= ice_set_rxfh,\n+\t.get_per_queue_coalesce = ice_get_per_q_coalesce,\n+\t.set_per_queue_coalesce = ice_set_per_q_coalesce,\n };\n \n /**\ndiff --git a/drivers/net/ethernet/intel/ice/ice_txrx.h b/drivers/net/ethernet/intel/ice/ice_txrx.h\nindex 794a706e0f5f..b6bafa74aef8 100644\n--- a/drivers/net/ethernet/intel/ice/ice_txrx.h\n+++ b/drivers/net/ethernet/intel/ice/ice_txrx.h\n@@ -118,9 +118,11 @@ enum ice_rx_dtype {\n #define ICE_TX_ITR\tICE_IDX_ITR1\n #define ICE_ITR_8K\t124\n #define ICE_ITR_20K\t50\n+#define ICE_ITR_MAX\t8160\n #define ICE_DFLT_TX_ITR\t(ICE_ITR_20K | ICE_ITR_DYNAMIC)\n #define ICE_DFLT_RX_ITR\t(ICE_ITR_20K | ICE_ITR_DYNAMIC)\n #define ICE_ITR_DYNAMIC\t0x8000 /* used as flag for itr_setting */\n+#define ITR_IS_DYNAMIC(setting) (!!((setting) & ICE_ITR_DYNAMIC))\n #define ITR_TO_REG(setting)\t((setting) & ~ICE_ITR_DYNAMIC)\n #define ICE_ITR_GRAN_S\t\t1\t/* Assume ITR granularity is 2us */\n #define ICE_ITR_MASK\t\t0x1FFE\t/* ITR register value alignment mask */\n", "prefixes": [ "S10", "11/15" ] }