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GET /api/patches/1016225/?format=api
{ "id": 1016225, "url": "http://patchwork.ozlabs.org/api/patches/1016225/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181219180334.1104-11-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20181219180334.1104-11-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-12-19T18:03:29", "name": "[S10,10/15] ice: Add support for adaptive interrupt moderation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "e4a240c9984e235135af8aa26f2db278df0583ae", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181219180334.1104-11-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 82906, "url": "http://patchwork.ozlabs.org/api/series/82906/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=82906", "date": "2018-12-19T18:03:28", "name": "Feature updates for ice", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/82906/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1016225/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1016225/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.137; helo=fraxinus.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 43KjSQ25wVz9sB5\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 20 Dec 2018 05:03:50 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id E96BA85BA4;\n\tWed, 19 Dec 2018 18:03:48 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 5r9tvZeJt7UH; Wed, 19 Dec 2018 18:03:47 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 5C10585B73;\n\tWed, 19 Dec 2018 18:03:47 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 23FE01C2A9B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:43 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 1F38422049\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:43 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id n1SMvm-xDBFE for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:37 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby silver.osuosl.org (Postfix) with ESMTPS id 09E3122EA3\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 19 Dec 2018 18:03:37 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Dec 2018 10:03:36 -0800", "from shasta.jf.intel.com ([10.166.241.11])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Dec 2018 10:03:35 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,373,1539673200\"; d=\"scan'208\";a=\"127400081\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 19 Dec 2018 10:03:29 -0800", "Message-Id": "<20181219180334.1104-11-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.5", "In-Reply-To": "<20181219180334.1104-1-anirudh.venkataramanan@intel.com>", "References": "<20181219180334.1104-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH S10 10/15] ice: Add support for adaptive\n\tinterrupt moderation", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Brett Creeley <brett.creeley@intel.com>\n\nCurrently the driver does not support adaptive/dynamic interrupt\nmoderation. This patch adds support for this. Also, adaptive/dynamic\ninterrupt moderation is turned on by default upon driver load.\n\nIn order to support adaptive interrupt moderation, two functions were\nadded, ice_update_itr() and ice_itr_divisor(). These are used to\ndetermine the current packet load and to determine a divisor based\non link speed respectively.\n\nThis patch also adds the ICE_ITR_GRAN_S define that is used in the\nhot-path when setting a new ITR value. The shift is used to pet two\nbirds with one hand, set the ITR value while re-enabling the\ninterrupt. Also, the ICE_ITR_GRAN_S is defined as 1 because the device\nhas a ITR granularity of 2usecs.\n\nSigned-off-by: Brett Creeley <brett.creeley@intel.com>\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice_hw_autogen.h | 1 +\n drivers/net/ethernet/intel/ice/ice_lib.c | 24 ++++++---\n drivers/net/ethernet/intel/ice/ice_main.c | 23 +++++++--\n drivers/net/ethernet/intel/ice/ice_txrx.c | 65 ++++++++++++++++++++++++-\n drivers/net/ethernet/intel/ice/ice_txrx.h | 30 +++++++-----\n 5 files changed, 120 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex 5507928c8fbe..f9a38f2cd470 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -110,6 +110,7 @@\n #define GLINT_DYN_CTL_CLEARPBA_M\t\tBIT(1)\n #define GLINT_DYN_CTL_SWINT_TRIG_M\t\tBIT(2)\n #define GLINT_DYN_CTL_ITR_INDX_S\t\t3\n+#define GLINT_DYN_CTL_INTERVAL_S\t\t5\n #define GLINT_DYN_CTL_SW_ITR_INDX_M\t\tICE_M(0x3, 25)\n #define GLINT_DYN_CTL_INTENA_MSK_M\t\tBIT(31)\n #define GLINT_ITR(_i, _INT)\t\t\t(0x00154000 + ((_i) * 8192 + (_INT) * 4))\ndiff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c\nindex 67f01292337a..15be202fc9ef 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lib.c\n+++ b/drivers/net/ethernet/intel/ice/ice_lib.c\n@@ -1715,22 +1715,34 @@ static u32 ice_intrl_usec_to_reg(u8 intrl, u8 gran)\n static void\n ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector, u16 vector)\n {\n-\tu8 itr_gran = hw->itr_gran;\n-\n \tif (q_vector->num_ring_rx) {\n \t\tstruct ice_ring_container *rc = &q_vector->rx;\n \n-\t\trc->itr = ITR_TO_REG(ICE_DFLT_RX_ITR, itr_gran);\n+\t\t/* if this value is set then don't overwrite with default */\n+\t\tif (!rc->itr_setting)\n+\t\t\trc->itr_setting = ICE_DFLT_RX_ITR;\n+\n+\t\trc->target_itr = ITR_TO_REG(rc->itr_setting);\n+\t\trc->next_update = jiffies + 1;\n+\t\trc->current_itr = rc->target_itr;\n \t\trc->latency_range = ICE_LOW_LATENCY;\n-\t\twr32(hw, GLINT_ITR(rc->itr_idx, vector), rc->itr);\n+\t\twr32(hw, GLINT_ITR(rc->itr_idx, vector),\n+\t\t ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);\n \t}\n \n \tif (q_vector->num_ring_tx) {\n \t\tstruct ice_ring_container *rc = &q_vector->tx;\n \n-\t\trc->itr = ITR_TO_REG(ICE_DFLT_TX_ITR, itr_gran);\n+\t\t/* if this value is set then don't overwrite with default */\n+\t\tif (!rc->itr_setting)\n+\t\t\trc->itr_setting = ICE_DFLT_TX_ITR;\n+\n+\t\trc->target_itr = ITR_TO_REG(rc->itr_setting);\n+\t\trc->next_update = jiffies + 1;\n+\t\trc->current_itr = rc->target_itr;\n \t\trc->latency_range = ICE_LOW_LATENCY;\n-\t\twr32(hw, GLINT_ITR(rc->itr_idx, vector), rc->itr);\n+\t\twr32(hw, GLINT_ITR(rc->itr_idx, vector),\n+\t\t ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);\n \t}\n }\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c\nindex 508644087a9b..081337bd9dd4 100644\n--- a/drivers/net/ethernet/intel/ice/ice_main.c\n+++ b/drivers/net/ethernet/intel/ice/ice_main.c\n@@ -1389,7 +1389,6 @@ static int ice_req_irq_msix_misc(struct ice_pf *pf)\n {\n \tstruct ice_hw *hw = &pf->hw;\n \tint oicr_idx, err = 0;\n-\tu8 itr_gran;\n \tu32 val;\n \n \tif (!pf->int_name[0])\n@@ -1453,10 +1452,8 @@ static int ice_req_irq_msix_misc(struct ice_pf *pf)\n \t PFINT_MBX_CTL_CAUSE_ENA_M);\n \twr32(hw, PFINT_MBX_CTL, val);\n \n-\titr_gran = hw->itr_gran;\n-\n \twr32(hw, GLINT_ITR(ICE_RX_ITR, pf->hw_oicr_idx),\n-\t ITR_TO_REG(ICE_ITR_8K, itr_gran));\n+\t ITR_REG_ALIGN(ICE_ITR_8K) >> ICE_ITR_GRAN_S);\n \n \tice_flush(hw);\n \tice_irq_dynamic_ena(hw, NULL, NULL);\n@@ -1997,6 +1994,23 @@ static int ice_init_interrupt_scheme(struct ice_pf *pf)\n \treturn 0;\n }\n \n+/**\n+ * ice_verify_itr_gran - verify driver's assumption of itr granularity\n+ * @pf: pointer to the PF structure\n+ *\n+ * There is no error returned here because the driver will be able to handle a\n+ * different ITR granularity, but interrupt moderation will not be accurate if\n+ * the driver's assumptions are not verified. This assumption is made so we can\n+ * use constants in the hot path instead of accessing structure members.\n+ */\n+static void ice_verify_itr_gran(struct ice_pf *pf)\n+{\n+\tif (pf->hw.itr_gran != (ICE_ITR_GRAN_S << 1))\n+\t\tdev_warn(&pf->pdev->dev,\n+\t\t\t \"%d ITR granularity assumption is invalid, actual ITR granularity is %d. Interrupt moderation will be inaccurate!\\n\",\n+\t\t\t (ICE_ITR_GRAN_S << 1), pf->hw.itr_gran);\n+}\n+\n /**\n * ice_verify_cacheline_size - verify driver's assumption of 64 Byte cache lines\n * @pf: pointer to the PF structure\n@@ -2163,6 +2177,7 @@ static int ice_probe(struct pci_dev *pdev,\n \tmod_timer(&pf->serv_tmr, round_jiffies(jiffies + pf->serv_tmr_period));\n \n \tice_verify_cacheline_size(pf);\n+\tice_verify_itr_gran(pf);\n \n \treturn 0;\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_txrx.c b/drivers/net/ethernet/intel/ice/ice_txrx.c\nindex 49fc38094185..f76a3666f2cd 100644\n--- a/drivers/net/ethernet/intel/ice/ice_txrx.c\n+++ b/drivers/net/ethernet/intel/ice/ice_txrx.c\n@@ -1052,6 +1052,69 @@ static int ice_clean_rx_irq(struct ice_ring *rx_ring, int budget)\n \treturn failure ? budget : (int)total_rx_pkts;\n }\n \n+/**\n+ * ice_buildreg_itr - build value for writing to the GLINT_DYN_CTL register\n+ * @itr_idx: interrupt throttling index\n+ * @reg_itr: interrupt throttling value adjusted based on itr granularity\n+ */\n+static u32 ice_buildreg_itr(int itr_idx, u16 reg_itr)\n+{\n+\treturn GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |\n+\t\t(itr_idx << GLINT_DYN_CTL_ITR_INDX_S) |\n+\t\t(reg_itr << GLINT_DYN_CTL_INTERVAL_S);\n+}\n+\n+/**\n+ * ice_update_ena_itr - Update itr and re-enable MSIX interrupt\n+ * @vsi: the VSI associated with the q_vector\n+ * @q_vector: q_vector for which itr is being updated and interrupt enabled\n+ */\n+static void\n+ice_update_ena_itr(struct ice_vsi *vsi, struct ice_q_vector *q_vector)\n+{\n+\tstruct ice_hw *hw = &vsi->back->hw;\n+\tstruct ice_ring_container *rc;\n+\tu32 itr_val;\n+\n+\t/* This block of logic allows us to get away with only updating\n+\t * one ITR value with each interrupt. The idea is to perform a\n+\t * pseudo-lazy update with the following criteria.\n+\t *\n+\t * 1. Rx is given higher priority than Tx if both are in same state\n+\t * 2. If we must reduce an ITR that is given highest priority.\n+\t * 3. We then give priority to increasing ITR based on amount.\n+\t */\n+\tif (q_vector->rx.target_itr < q_vector->rx.current_itr) {\n+\t\trc = &q_vector->rx;\n+\t\t/* Rx ITR needs to be reduced, this is highest priority */\n+\t\titr_val = ice_buildreg_itr(rc->itr_idx, rc->target_itr);\n+\t\trc->current_itr = rc->target_itr;\n+\t} else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||\n+\t\t ((q_vector->rx.target_itr - q_vector->rx.current_itr) <\n+\t\t (q_vector->tx.target_itr - q_vector->tx.current_itr))) {\n+\t\trc = &q_vector->tx;\n+\t\t/* Tx ITR needs to be reduced, this is second priority\n+\t\t * Tx ITR needs to be increased more than Rx, fourth priority\n+\t\t */\n+\t\titr_val = ice_buildreg_itr(rc->itr_idx, rc->target_itr);\n+\t\trc->current_itr = rc->target_itr;\n+\t} else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {\n+\t\trc = &q_vector->rx;\n+\t\t/* Rx ITR needs to be increased, third priority */\n+\t\titr_val = ice_buildreg_itr(rc->itr_idx, rc->target_itr);\n+\t\trc->current_itr = rc->target_itr;\n+\t} else {\n+\t\t/* Still have to re-enable the interrupts */\n+\t\titr_val = ice_buildreg_itr(ICE_ITR_NONE, 0);\n+\t}\n+\n+\tif (!test_bit(__ICE_DOWN, vsi->state)) {\n+\t\tint vector = vsi->hw_base_vector + q_vector->v_idx;\n+\n+\t\twr32(hw, GLINT_DYN_CTL(vector), itr_val);\n+\t}\n+}\n+\n /**\n * ice_napi_poll - NAPI polling Rx/Tx cleanup routine\n * @napi: napi struct with our devices info in it\n@@ -1108,7 +1171,7 @@ int ice_napi_poll(struct napi_struct *napi, int budget)\n \t */\n \tif (likely(napi_complete_done(napi, work_done)))\n \t\tif (test_bit(ICE_FLAG_MSIX_ENA, pf->flags))\n-\t\t\tice_irq_dynamic_ena(&vsi->back->hw, vsi, q_vector);\n+\t\t\tice_update_ena_itr(vsi, q_vector);\n \n \treturn min(work_done, budget - 1);\n }\ndiff --git a/drivers/net/ethernet/intel/ice/ice_txrx.h b/drivers/net/ethernet/intel/ice/ice_txrx.h\nindex 75d0eaf6c9dd..794a706e0f5f 100644\n--- a/drivers/net/ethernet/intel/ice/ice_txrx.h\n+++ b/drivers/net/ethernet/intel/ice/ice_txrx.h\n@@ -116,16 +116,15 @@ enum ice_rx_dtype {\n /* indices into GLINT_ITR registers */\n #define ICE_RX_ITR\tICE_IDX_ITR0\n #define ICE_TX_ITR\tICE_IDX_ITR1\n-#define ICE_ITR_DYNAMIC\t0x8000 /* use top bit as a flag */\n-#define ICE_ITR_8K\t125\n+#define ICE_ITR_8K\t124\n #define ICE_ITR_20K\t50\n-#define ICE_DFLT_TX_ITR\tICE_ITR_20K\n-#define ICE_DFLT_RX_ITR\tICE_ITR_20K\n-/* apply ITR granularity translation to program the register. itr_gran is either\n- * 2 or 4 usecs so we need to divide by 2 first then shift by that value\n- */\n-#define ITR_TO_REG(val, itr_gran) (((val) & ~ICE_ITR_DYNAMIC) >> \\\n-\t\t\t\t ((itr_gran) / 2))\n+#define ICE_DFLT_TX_ITR\t(ICE_ITR_20K | ICE_ITR_DYNAMIC)\n+#define ICE_DFLT_RX_ITR\t(ICE_ITR_20K | ICE_ITR_DYNAMIC)\n+#define ICE_ITR_DYNAMIC\t0x8000 /* used as flag for itr_setting */\n+#define ITR_TO_REG(setting)\t((setting) & ~ICE_ITR_DYNAMIC)\n+#define ICE_ITR_GRAN_S\t\t1\t/* Assume ITR granularity is 2us */\n+#define ICE_ITR_MASK\t\t0x1FFE\t/* ITR register value alignment mask */\n+#define ITR_REG_ALIGN(setting)\t__ALIGN_MASK(setting, ~ICE_ITR_MASK)\n \n #define ICE_DFLT_INTRL\t0\n \n@@ -180,13 +179,20 @@ enum ice_latency_range {\n };\n \n struct ice_ring_container {\n-\t/* array of pointers to rings */\n+\t/* head of linked-list of rings */\n \tstruct ice_ring *ring;\n+\tunsigned long next_update;\t/* jiffies value of next queue update */\n \tunsigned int total_bytes;\t/* total bytes processed this int */\n \tunsigned int total_pkts;\t/* total packets processed this int */\n \tenum ice_latency_range latency_range;\n-\tint itr_idx;\t/* index in the interrupt vector */\n-\tu16 itr;\n+\tint itr_idx;\t\t/* index in the interrupt vector */\n+\tu16 target_itr;\t\t/* value in usecs divided by the hw->itr_gran */\n+\tu16 current_itr;\t/* value in usecs divided by the hw->itr_gran */\n+\t/* high bit set means dynamic itr, rest is used to store user\n+\t * readable itr value in usecs and must be converted before programming\n+\t * to a register.\n+\t */\n+\tu16 itr_setting;\n };\n \n /* iterator for handling rings in ring container */\n", "prefixes": [ "S10", "10/15" ] }