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GET /api/patches/1008875/?format=api
{ "id": 1008875, "url": "http://patchwork.ozlabs.org/api/patches/1008875/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181206154955.334-2-stephend@silicom-usa.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20181206154955.334-2-stephend@silicom-usa.com>", "list_archive_url": null, "date": "2018-12-06T15:50:39", "name": "[net-next,v5,1/2] ixgbe: register a mdiobus", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "36d8beddcec300c8938b652a1d91c4674b9a02f3", "submitter": { "id": 73588, "url": "http://patchwork.ozlabs.org/api/people/73588/?format=api", "name": "Stephen Douthit", "email": "stephend@silicom-usa.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181206154955.334-2-stephend@silicom-usa.com/mbox/", "series": [ { "id": 80189, "url": "http://patchwork.ozlabs.org/api/series/80189/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=80189", "date": "2018-12-06T15:50:39", "name": "[net-next,v5,1/2] ixgbe: register a mdiobus", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/80189/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1008875/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1008875/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.137; 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Thu, 6 Dec 2018 15:50:39 +0000", "from VI1PR0402MB3853.eurprd04.prod.outlook.com\n\t([fe80::457b:1a37:563c:a718]) by\n\tVI1PR0402MB3853.eurprd04.prod.outlook.com\n\t([fe80::457b:1a37:563c:a718%5]) with mapi id 15.20.1404.021;\n\tThu, 6 Dec 2018 15:50:39 +0000" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "from auto-whitelisted by SQLgrey-1.7.6", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=SILICOMLTD.onmicrosoft.com; s=selector1-silicomusa-com01i;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=uDuQs3qIgGTKf1DiGRoAxN3w7nnodcFfxUFyCRbuw7g=;\n\tb=0MruwzplUnC8ZEH/+Axo9gxzHz6S4KYikGUqGcv9Bz9X2BDZCs3XDDtaZpjpjhFDsb1zyU11ccc9jJdCI7jFKcPQ+1e/nSQP+qyz///Bl0fcCHLi5kYXV2F/UX+rwcLHVH+oNAEKp5R5YExPcXIK3IsxCKvwxDQ17FMeAexx5CQ=", "From": "Steve Douthit <stephend@silicom-usa.com>", "To": "Jeff Kirsher <jeffrey.t.kirsher@intel.com>", "Thread-Topic": "[PATCH net-next v5 1/2] ixgbe: register a mdiobus", "Thread-Index": "AQHUjXtvcZq0sewc8U+G3Ju/Btqi0Q==", "Date": "Thu, 6 Dec 2018 15:50:39 +0000", "Message-ID": "<20181206154955.334-2-stephend@silicom-usa.com>", "References": "<20181203163227.5107-1-stephend@silicom-usa.com>\n\t<20181206154955.334-1-stephend@silicom-usa.com>", "In-Reply-To": "<20181206154955.334-1-stephend@silicom-usa.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "BL0PR02CA0037.namprd02.prod.outlook.com\n\t(2603:10b6:207:3d::14) To VI1PR0402MB3853.eurprd04.prod.outlook.com\n\t(2603:10a6:803:21::21)", "authentication-results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.137; 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PCL:0;\n\tRULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020);\n\tSRVR:VI1PR0402MB3455; ", "x-ms-traffictypediagnostic": "VI1PR0402MB3455:", "x-microsoft-antispam-prvs": "<VI1PR0402MB34556F5095A97D48C621743894A90@VI1PR0402MB3455.eurprd04.prod.outlook.com>", "x-ms-exchange-senderadcheck": "1", "x-exchange-antispam-report-cfa-test": "BCL:0; PCL:0;\n\tRULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231455)(999002)(944501520)(52105112)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123562045)(20161123560045)(20161123564045)(201708071742011)(7699051)(76991095);\n\tSRVR:VI1PR0402MB3455; BCL:0; PCL:0; RULEID:; SRVR:VI1PR0402MB3455; ", "x-forefront-prvs": "087894CD3C", "x-forefront-antispam-report": "SFV:NSPM;\n\tSFS:(10019020)(39850400004)(396003)(136003)(376002)(346002)(366004)(199004)(189003)(486006)(14444005)(7736002)(5660300001)(2616005)(66066001)(476003)(256004)(81156014)(8676002)(551934003)(54906003)(305945005)(446003)(97736004)(81166006)(316002)(8936002)(106356001)(11346002)(68736007)(107886003)(4326008)(575784001)(86362001)(99286004)(105586002)(76176011)(52116002)(3846002)(6116002)(1076002)(186003)(478600001)(102836004)(39060400002)(6506007)(26005)(36756003)(6512007)(2906002)(6486002)(14454004)(6916009)(25786009)(53936002)(386003)(71190400001)(4744004)(6436002)(71200400001)(42262002);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:VI1PR0402MB3455;\n\tH:VI1PR0402MB3853.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; \n\tPTR:InfoNoRecords; A:1; MX:1; ", "received-spf": "None (protection.outlook.com: silicom-usa.com does not\n\tdesignate permitted sender hosts)", "x-microsoft-antispam-message-info": "4vgVn9Ihe+P3mLVji1CA3Qv66u7EMdOehzllJMzXRJhYZGR46Pa4qqU6cgad7PBZ8HLoi/FpODc9YfxE8IkvNfYdcsVrjVT3bMBiMjDpBZKSddDtkRyJafyC/+331BZZVWCGQh70rkpznVNRzEy/+1vwdvMtuSQPkERoNt/oKI7CJeesD/LwglORv//MSjnXoDJuHa17DQbM4+GeD9jUdyBhrqUe3gZ2ZDm9D4sF5UkPZW7Fjvzt6BHWyem01jXgiJrMVimWL19UhUK/lSn2swFinCG0rlFoDbU89l5bnw5OVh19gZpouf/ehS+BnfdZ38gAC57OTHnyB/DSolSZtZKzOY5qLRFfaJ1XfMAC4LQ=", "spamdiagnosticoutput": "1:99", "spamdiagnosticmetadata": "NSPM", "MIME-Version": "1.0", "X-OriginatorOrg": "silicom-usa.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "e422ccd2-f0b1-438d-0f65-08d65b9291c3", "X-MS-Exchange-CrossTenant-originalarrivaltime": "06 Dec 2018 15:50:39.2659\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "c9e326d8-ce47-4930-8612-cc99d3c87ad1", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "VI1PR0402MB3455", "Subject": "[Intel-wired-lan] [PATCH net-next v5 1/2] ixgbe: register a mdiobus", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "Andrew Lunn <andrew@lunn.ch>, Florian Fainelli <f.fainelli@gmail.com>,\n\t\"netdev@vger.kernel.org\" <netdev@vger.kernel.org>,\n\t\"intel-wired-lan@lists.osuosl.org\" <intel-wired-lan@lists.osuosl.org>,\n\t\"David S. Miller\" <davem@davemloft.net>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Most dsa devices expect a 'struct mii_bus' pointer to talk to switches\nvia the MII interface.\n\nWhile this works for dsa devices, it will not work safely with Linux\nPHYs in all configurations since the firmware of the ixgbe device may\nbe polling some PHY addresses in the background.\n\nSigned-off-by: Stephen Douthit <stephend@silicom-usa.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nTested-by: Andrew Bowers <andrewx.bowers@intel.com>\n---\n drivers/net/ethernet/intel/Kconfig | 1 +\n drivers/net/ethernet/intel/ixgbe/ixgbe.h | 2 +\n drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 5 +\n drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c | 299 ++++++++++++++++++\n drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h | 2 +\n 5 files changed, 309 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig\nindex 59e1bc0f609e..096cf3bc76a0 100644\n--- a/drivers/net/ethernet/intel/Kconfig\n+++ b/drivers/net/ethernet/intel/Kconfig\n@@ -159,6 +159,7 @@ config IXGBE\n \ttristate \"Intel(R) 10GbE PCI Express adapters support\"\n \tdepends on PCI\n \tselect MDIO\n+\tselect MDIO_DEVICE\n \timply PTP_1588_CLOCK\n \t---help---\n \t This driver supports Intel(R) 10GbE PCI Express family of\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe.h\nindex 143bdd5ee2a0..08d85e336bd4 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h\n@@ -12,6 +12,7 @@\n #include <linux/aer.h>\n #include <linux/if_vlan.h>\n #include <linux/jiffies.h>\n+#include <linux/phy.h>\n \n #include <linux/timecounter.h>\n #include <linux/net_tstamp.h>\n@@ -561,6 +562,7 @@ struct ixgbe_adapter {\n \tstruct net_device *netdev;\n \tstruct bpf_prog *xdp_prog;\n \tstruct pci_dev *pdev;\n+\tstruct mii_bus *mii_bus;\n \n \tunsigned long state;\n \ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\nindex b57fa0cfb222..b7907674c565 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\n@@ -39,6 +39,7 @@\n #include \"ixgbe.h\"\n #include \"ixgbe_common.h\"\n #include \"ixgbe_dcb_82599.h\"\n+#include \"ixgbe_phy.h\"\n #include \"ixgbe_sriov.h\"\n #include \"ixgbe_model.h\"\n #include \"ixgbe_txrx_common.h\"\n@@ -11120,6 +11121,8 @@ static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n \t\t\tIXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,\n \t\t\ttrue);\n \n+\tixgbe_mii_bus_init(hw);\n+\n \treturn 0;\n \n err_register:\n@@ -11170,6 +11173,8 @@ static void ixgbe_remove(struct pci_dev *pdev)\n \tset_bit(__IXGBE_REMOVING, &adapter->state);\n \tcancel_work_sync(&adapter->service_task);\n \n+\tif (adapter->mii_bus)\n+\t\tmdiobus_unregister(adapter->mii_bus);\n \n #ifdef CONFIG_IXGBE_DCA\n \tif (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c\nindex 919a7af84b42..cc4907f9ff02 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c\n@@ -3,6 +3,7 @@\n \n #include <linux/pci.h>\n #include <linux/delay.h>\n+#include <linux/iopoll.h>\n #include <linux/sched.h>\n \n #include \"ixgbe.h\"\n@@ -658,6 +659,304 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n \treturn status;\n }\n \n+#define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)\n+\n+/**\n+ * ixgbe_msca_cmd - Write the command register and poll for completion/timeout\n+ * @hw: pointer to hardware structure\n+ * @cmd: command register value to write\n+ **/\n+static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)\n+{\n+\tIXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);\n+\n+\treturn readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,\n+\t\t\t\t !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,\n+\t\t\t\t 10 * IXGBE_MDIO_COMMAND_TIMEOUT);\n+}\n+\n+/**\n+ * ixgbe_mii_bus_read_generic - Read a clause 22/45 register with gssr flags\n+ * @hw: pointer to hardware structure\n+ * @addr: address\n+ * @regnum: register number\n+ * @gssr: semaphore flags to acquire\n+ **/\n+static s32 ixgbe_mii_bus_read_generic(struct ixgbe_hw *hw, int addr,\n+\t\t\t\t int regnum, u32 gssr)\n+{\n+\tu32 hwaddr, cmd;\n+\ts32 data;\n+\n+\tif (hw->mac.ops.acquire_swfw_sync(hw, gssr))\n+\t\treturn -EBUSY;\n+\n+\thwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;\n+\tif (regnum & MII_ADDR_C45) {\n+\t\thwaddr |= regnum & GENMASK(21, 0);\n+\t\tcmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;\n+\t} else {\n+\t\thwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;\n+\t\tcmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |\n+\t\t\tIXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;\n+\t}\n+\n+\tdata = ixgbe_msca_cmd(hw, cmd);\n+\tif (data < 0)\n+\t\tgoto mii_bus_read_done;\n+\n+\t/* For a clause 45 access the address cycle just completed, we still\n+\t * need to do the read command, otherwise just get the data\n+\t */\n+\tif (!(regnum & MII_ADDR_C45))\n+\t\tgoto do_mii_bus_read;\n+\n+\tcmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;\n+\tdata = ixgbe_msca_cmd(hw, cmd);\n+\tif (data < 0)\n+\t\tgoto mii_bus_read_done;\n+\n+do_mii_bus_read:\n+\tdata = IXGBE_READ_REG(hw, IXGBE_MSRWD);\n+\tdata = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);\n+\n+mii_bus_read_done:\n+\thw->mac.ops.release_swfw_sync(hw, gssr);\n+\treturn data;\n+}\n+\n+/**\n+ * ixgbe_mii_bus_write_generic - Write a clause 22/45 register with gssr flags\n+ * @hw: pointer to hardware structure\n+ * @addr: address\n+ * @regnum: register number\n+ * @val: value to write\n+ * @gssr: semaphore flags to acquire\n+ **/\n+static s32 ixgbe_mii_bus_write_generic(struct ixgbe_hw *hw, int addr,\n+\t\t\t\t int regnum, u16 val, u32 gssr)\n+{\n+\tu32 hwaddr, cmd;\n+\ts32 err;\n+\n+\tif (hw->mac.ops.acquire_swfw_sync(hw, gssr))\n+\t\treturn -EBUSY;\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);\n+\n+\thwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;\n+\tif (regnum & MII_ADDR_C45) {\n+\t\thwaddr |= regnum & GENMASK(21, 0);\n+\t\tcmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;\n+\t} else {\n+\t\thwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;\n+\t\tcmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |\n+\t\t\tIXGBE_MSCA_MDI_COMMAND;\n+\t}\n+\n+\t/* For clause 45 this is an address cycle, for clause 22 this is the\n+\t * entire transaction\n+\t */\n+\terr = ixgbe_msca_cmd(hw, cmd);\n+\tif (err < 0 || !(regnum & MII_ADDR_C45))\n+\t\tgoto mii_bus_write_done;\n+\n+\tcmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;\n+\terr = ixgbe_msca_cmd(hw, cmd);\n+\n+mii_bus_write_done:\n+\thw->mac.ops.release_swfw_sync(hw, gssr);\n+\treturn err;\n+}\n+\n+/**\n+ * ixgbe_mii_bus_read - Read a clause 22/45 register\n+ * @hw: pointer to hardware structure\n+ * @addr: address\n+ * @regnum: register number\n+ **/\n+static s32 ixgbe_mii_bus_read(struct mii_bus *bus, int addr, int regnum)\n+{\n+\tstruct ixgbe_adapter *adapter = bus->priv;\n+\tstruct ixgbe_hw *hw = &adapter->hw;\n+\tu32 gssr = hw->phy.phy_semaphore_mask;\n+\n+\treturn ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);\n+}\n+\n+/**\n+ * ixgbe_mii_bus_write - Write a clause 22/45 register\n+ * @hw: pointer to hardware structure\n+ * @addr: address\n+ * @regnum: register number\n+ * @val: value to write\n+ **/\n+static s32 ixgbe_mii_bus_write(struct mii_bus *bus, int addr, int regnum,\n+\t\t\t u16 val)\n+{\n+\tstruct ixgbe_adapter *adapter = bus->priv;\n+\tstruct ixgbe_hw *hw = &adapter->hw;\n+\tu32 gssr = hw->phy.phy_semaphore_mask;\n+\n+\treturn ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);\n+}\n+\n+/**\n+ * ixgbe_x550em_a_mii_bus_read - Read a clause 22/45 register on x550em_a\n+ * @hw: pointer to hardware structure\n+ * @addr: address\n+ * @regnum: register number\n+ **/\n+static s32 ixgbe_x550em_a_mii_bus_read(struct mii_bus *bus, int addr,\n+\t\t\t\t int regnum)\n+{\n+\tstruct ixgbe_adapter *adapter = bus->priv;\n+\tstruct ixgbe_hw *hw = &adapter->hw;\n+\tu32 gssr = hw->phy.phy_semaphore_mask;\n+\n+\tgssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;\n+\treturn ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);\n+}\n+\n+/**\n+ * ixgbe_x550em_a_mii_bus_write - Write a clause 22/45 register on x550em_a\n+ * @hw: pointer to hardware structure\n+ * @addr: address\n+ * @regnum: register number\n+ * @val: value to write\n+ **/\n+static s32 ixgbe_x550em_a_mii_bus_write(struct mii_bus *bus, int addr,\n+\t\t\t\t\tint regnum, u16 val)\n+{\n+\tstruct ixgbe_adapter *adapter = bus->priv;\n+\tstruct ixgbe_hw *hw = &adapter->hw;\n+\tu32 gssr = hw->phy.phy_semaphore_mask;\n+\n+\tgssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;\n+\treturn ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);\n+}\n+\n+/**\n+ * ixgbe_get_first_secondary_devfn - get first device downstream of root port\n+ * @devfn: PCI_DEVFN of root port on domain 0, bus 0\n+ *\n+ * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root\n+ * on domain 0, bus 0, devfn = 'devfn'\n+ **/\n+static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)\n+{\n+\tstruct pci_dev *rp_pdev;\n+\tint bus;\n+\n+\trp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);\n+\tif (rp_pdev && rp_pdev->subordinate) {\n+\t\tbus = rp_pdev->subordinate->number;\n+\t\treturn pci_get_domain_bus_and_slot(0, bus, 0);\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+/**\n+ * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?\n+ * @hw: pointer to hardware structure\n+ *\n+ * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in\n+ * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a,\n+ * but we only want to register one MDIO bus.\n+ **/\n+static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_adapter *adapter = hw->back;\n+\tstruct pci_dev *pdev = adapter->pdev;\n+\tstruct pci_dev *func0_pdev;\n+\n+\t/* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices\n+\t * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0\n+\t * It's not valid for function 0 to be disabled and function 1 is up,\n+\t * so the lowest numbered ixgbe dev will be device 0 function 0 on one\n+\t * of those two root ports\n+\t */\n+\tfunc0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));\n+\tif (func0_pdev) {\n+\t\tif (func0_pdev == pdev)\n+\t\t\treturn true;\n+\t\telse\n+\t\t\treturn false;\n+\t}\n+\tfunc0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));\n+\tif (func0_pdev == pdev)\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+/**\n+ * ixgbe_mii_bus_init - mii_bus structure setup\n+ * @hw: pointer to hardware structure\n+ *\n+ * Returns 0 on success, negative on failure\n+ *\n+ * ixgbe_mii_bus_init initializes a mii_bus structure in adapter\n+ **/\n+s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_adapter *adapter = hw->back;\n+\tstruct pci_dev *pdev = adapter->pdev;\n+\tstruct device *dev = &adapter->netdev->dev;\n+\tstruct mii_bus *bus;\n+\n+\tadapter->mii_bus = devm_mdiobus_alloc(dev);\n+\tif (!adapter->mii_bus)\n+\t\treturn -ENOMEM;\n+\n+\tbus = adapter->mii_bus;\n+\n+\tswitch (hw->device_id) {\n+\t/* C3000 SoCs */\n+\tcase IXGBE_DEV_ID_X550EM_A_KR:\n+\tcase IXGBE_DEV_ID_X550EM_A_KR_L:\n+\tcase IXGBE_DEV_ID_X550EM_A_SFP_N:\n+\tcase IXGBE_DEV_ID_X550EM_A_SGMII:\n+\tcase IXGBE_DEV_ID_X550EM_A_SGMII_L:\n+\tcase IXGBE_DEV_ID_X550EM_A_10G_T:\n+\tcase IXGBE_DEV_ID_X550EM_A_SFP:\n+\tcase IXGBE_DEV_ID_X550EM_A_1G_T:\n+\tcase IXGBE_DEV_ID_X550EM_A_1G_T_L:\n+\t\tif (!ixgbe_x550em_a_has_mii(hw))\n+\t\t\tgoto ixgbe_no_mii_bus;\n+\t\tbus->read = &ixgbe_x550em_a_mii_bus_read;\n+\t\tbus->write = &ixgbe_x550em_a_mii_bus_write;\n+\t\tbreak;\n+\tdefault:\n+\t\tbus->read = &ixgbe_mii_bus_read;\n+\t\tbus->write = &ixgbe_mii_bus_write;\n+\t\tbreak;\n+\t}\n+\n+\t/* Use the position of the device in the PCI hierarchy as the id */\n+\tsnprintf(bus->id, MII_BUS_ID_SIZE, \"%s-mdio-%s\", ixgbe_driver_name,\n+\t\t pci_name(pdev));\n+\n+\tbus->name = \"ixgbe-mdio\";\n+\tbus->priv = adapter;\n+\tbus->parent = dev;\n+\tbus->phy_mask = GENMASK(31, 0);\n+\n+\t/* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22\n+\t * unfortunately that causes some clause 22 frames to be sent with\n+\t * clause 45 addressing. We don't want that.\n+\t */\n+\thw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;\n+\n+\treturn mdiobus_register(bus);\n+\n+ixgbe_no_mii_bus:\n+\tdevm_mdiobus_free(dev, bus);\n+\tadapter->mii_bus = NULL;\n+\treturn -ENODEV;\n+}\n+\n /**\n * ixgbe_setup_phy_link_generic - Set and restart autoneg\n * @hw: pointer to hardware structure\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h\nindex 64e44e01c973..214b01085718 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h\n@@ -120,6 +120,8 @@\n /* SFP+ SFF-8472 Compliance code */\n #define IXGBE_SFF_SFF_8472_UNSUP 0x00\n \n+s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw);\n+\n s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);\n s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);\n s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n", "prefixes": [ "net-next", "v5", "1/2" ] }