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GET /api/patches/100186/?format=api
{ "id": 100186, "url": "http://patchwork.ozlabs.org/api/patches/100186/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1308006792-22544-2-git-send-email-sjg@chromium.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1308006792-22544-2-git-send-email-sjg@chromium.org>", "list_archive_url": null, "date": "2011-06-13T23:13:09", "name": "[U-Boot,v8,1/4] Add support for SMSC95XX USB 2.0 10/100MBit Ethernet Adapter", "commit_ref": "291391bed566a569a80b50c924a7c43747abc1b5", "pull_url": null, "state": "accepted", "archived": true, "hash": "daebfb7545095a5bafc0fea25f3744122c07b057", "submitter": { "id": 6170, "url": "http://patchwork.ozlabs.org/api/people/6170/?format=api", "name": "Simon Glass", "email": "sjg@chromium.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1308006792-22544-2-git-send-email-sjg@chromium.org/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/100186/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/100186/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 980C2B6FA9\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 14 Jun 2011 09:14:21 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id C3E332819F;\n\tTue, 14 Jun 2011 01:14:11 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id kYZPdFNTSEe8; Tue, 14 Jun 2011 01:14:11 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 010442816B;\n\tTue, 14 Jun 2011 01:14:09 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 5DDA228194\n\tfor <u-boot@lists.denx.de>; Tue, 14 Jun 2011 01:14:06 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id HeYKwzsXf0Y6 for <u-boot@lists.denx.de>;\n\tTue, 14 Jun 2011 01:14:04 +0200 (CEST)", "from smtp-out.google.com (smtp-out.google.com [216.239.44.51])\n\tby theia.denx.de (Postfix) with ESMTPS id 0A37C28189\n\tfor <u-boot@lists.denx.de>; Tue, 14 Jun 2011 01:14:00 +0200 (CEST)", "from hpaq12.eem.corp.google.com (hpaq12.eem.corp.google.com\n\t[172.25.149.12]) by smtp-out.google.com with ESMTP id p5DNDeZu031196; \n\tMon, 13 Jun 2011 16:13:41 -0700", "from sglass.mtv.corp.google.com (sglass.mtv.corp.google.com\n\t[172.22.72.144])\n\tby hpaq12.eem.corp.google.com with ESMTP id p5DNDbos027925;\n\tMon, 13 Jun 2011 16:13:38 -0700", "by sglass.mtv.corp.google.com (Postfix, from userid 121222)\n\tid 2F5C6140B1F; Mon, 13 Jun 2011 16:13:37 -0700 (PDT)" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Simon Glass <sjg@chromium.org>", "To": "U-Boot Mailing List <u-boot@lists.denx.de>", "Date": "Mon, 13 Jun 2011 16:13:09 -0700", "Message-Id": "<1308006792-22544-2-git-send-email-sjg@chromium.org>", "X-Mailer": "git-send-email 1.7.3.1", "In-Reply-To": "<1308006792-22544-1-git-send-email-sjg@chromium.org>", "References": "<1308006792-22544-1-git-send-email-sjg@chromium.org>", "MIME-Version": "1.0", "X-System-Of-Record": "true", "Cc": "Andy Fleming <afleming@gmail.com>", "Subject": "[U-Boot] [PATCH v8 1/4] Add support for SMSC95XX USB 2.0 10/100MBit\n\tEthernet Adapter", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.9", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "The SMSC95XX is a USB hub with a built-in Ethernet adapter. This adds support\nfor this, using the USB host network framework.\n\nChanges for v2:\n- Coding style cleanup\n- Changed some comments as suggested\n\nChanges for v3:\n- Change turbo_mode to #define\n\nChanges for v4:\n- Dropped Tegra2 specific bit\n- Fixed a few broken bits in SMSC from my testing\n\nChanges for v5:\n- Code style clean-ups in SMSC\n- Cleaned up debugging of errors in SMSC driver\n\nChanges for v6:\n- Set NET_IP_ALIGN to 0 always\n\nChanges for v8:\n- Add setup of SMSC write_hwaddr function\n\nSigned-off-by: Simon Glass <sjg@chromium.org>\nTested-by: Eric Bénard <eric@eukrea.com>\n---\n drivers/usb/eth/Makefile | 1 +\n drivers/usb/eth/smsc95xx.c | 879 +++++++++++++++++++++++++++++++++++++++++++\n drivers/usb/eth/usb_ether.c | 7 +\n include/usb_ether.h | 13 +\n 4 files changed, 900 insertions(+), 0 deletions(-)\n create mode 100644 drivers/usb/eth/smsc95xx.c", "diff": "diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile\nindex 6a5f25a..e28793d 100644\n--- a/drivers/usb/eth/Makefile\n+++ b/drivers/usb/eth/Makefile\n@@ -28,6 +28,7 @@ COBJS-$(CONFIG_USB_HOST_ETHER) += usb_ether.o\n ifdef CONFIG_USB_ETHER_ASIX\n COBJS-y += asix.o\n endif\n+COBJS-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o\n \n COBJS\t:= $(COBJS-y)\n SRCS\t:= $(COBJS:.o=.c)\ndiff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c\nnew file mode 100644\nindex 0000000..97f2729\n--- /dev/null\n+++ b/drivers/usb/eth/smsc95xx.c\n@@ -0,0 +1,879 @@\n+/*\n+ * Copyright (c) 2011 The Chromium OS Authors.\n+ * Copyright (C) 2009 NVIDIA, Corporation\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n+ * MA 02111-1307 USA\n+ */\n+\n+#include <common.h>\n+#include <usb.h>\n+#include <linux/mii.h>\n+#include \"usb_ether.h\"\n+\n+/* SMSC LAN95xx based USB 2.0 Ethernet Devices */\n+\n+/* Tx command words */\n+#define TX_CMD_A_FIRST_SEG_\t\t0x00002000\n+#define TX_CMD_A_LAST_SEG_\t\t0x00001000\n+\n+/* Rx status word */\n+#define RX_STS_FL_\t\t\t0x3FFF0000\t/* Frame Length */\n+#define RX_STS_ES_\t\t\t0x00008000\t/* Error Summary */\n+\n+/* SCSRs */\n+#define ID_REV\t\t\t\t0x00\n+\n+#define INT_STS\t\t\t\t0x08\n+\n+#define TX_CFG\t\t\t\t0x10\n+#define TX_CFG_ON_\t\t\t0x00000004\n+\n+#define HW_CFG\t\t\t\t0x14\n+#define HW_CFG_BIR_\t\t\t0x00001000\n+#define HW_CFG_RXDOFF_\t\t\t0x00000600\n+#define HW_CFG_MEF_\t\t\t0x00000020\n+#define HW_CFG_BCE_\t\t\t0x00000002\n+#define HW_CFG_LRST_\t\t\t0x00000008\n+\n+#define PM_CTRL\t\t\t\t0x20\n+#define PM_CTL_PHY_RST_\t\t\t0x00000010\n+\n+#define AFC_CFG\t\t\t\t0x2C\n+\n+/*\n+ * Hi watermark = 15.5Kb (~10 mtu pkts)\n+ * low watermark = 3k (~2 mtu pkts)\n+ * backpressure duration = ~ 350us\n+ * Apply FC on any frame.\n+ */\n+#define AFC_CFG_DEFAULT\t\t\t0x00F830A1\n+\n+#define E2P_CMD\t\t\t\t0x30\n+#define E2P_CMD_BUSY_\t\t\t0x80000000\n+#define E2P_CMD_READ_\t\t\t0x00000000\n+#define E2P_CMD_TIMEOUT_\t\t0x00000400\n+#define E2P_CMD_LOADED_\t\t\t0x00000200\n+#define E2P_CMD_ADDR_\t\t\t0x000001FF\n+\n+#define E2P_DATA\t\t\t0x34\n+\n+#define BURST_CAP\t\t\t0x38\n+\n+#define INT_EP_CTL\t\t\t0x68\n+#define INT_EP_CTL_PHY_INT_\t\t0x00008000\n+\n+#define BULK_IN_DLY\t\t\t0x6C\n+\n+/* MAC CSRs */\n+#define MAC_CR\t\t\t\t0x100\n+#define MAC_CR_MCPAS_\t\t\t0x00080000\n+#define MAC_CR_PRMS_\t\t\t0x00040000\n+#define MAC_CR_HPFILT_\t\t\t0x00002000\n+#define MAC_CR_TXEN_\t\t\t0x00000008\n+#define MAC_CR_RXEN_\t\t\t0x00000004\n+\n+#define ADDRH\t\t\t\t0x104\n+\n+#define ADDRL\t\t\t\t0x108\n+\n+#define MII_ADDR\t\t\t0x114\n+#define MII_WRITE_\t\t\t0x02\n+#define MII_BUSY_\t\t\t0x01\n+#define MII_READ_\t\t\t0x00 /* ~of MII Write bit */\n+\n+#define MII_DATA\t\t\t0x118\n+\n+#define FLOW\t\t\t\t0x11C\n+\n+#define VLAN1\t\t\t\t0x120\n+\n+#define COE_CR\t\t\t\t0x130\n+#define Tx_COE_EN_\t\t\t0x00010000\n+#define Rx_COE_EN_\t\t\t0x00000001\n+\n+/* Vendor-specific PHY Definitions */\n+#define PHY_INT_SRC\t\t\t29\n+\n+#define PHY_INT_MASK\t\t\t30\n+#define PHY_INT_MASK_ANEG_COMP_\t\t((u16)0x0040)\n+#define PHY_INT_MASK_LINK_DOWN_\t\t((u16)0x0010)\n+#define PHY_INT_MASK_DEFAULT_\t\t(PHY_INT_MASK_ANEG_COMP_ | \\\n+\t\t\t\t\t PHY_INT_MASK_LINK_DOWN_)\n+\n+/* USB Vendor Requests */\n+#define USB_VENDOR_REQUEST_WRITE_REGISTER\t0xA0\n+#define USB_VENDOR_REQUEST_READ_REGISTER\t0xA1\n+\n+/* Some extra defines */\n+#define HS_USB_PKT_SIZE\t\t\t512\n+#define FS_USB_PKT_SIZE\t\t\t64\n+#define DEFAULT_HS_BURST_CAP_SIZE\t(16 * 1024 + 5 * HS_USB_PKT_SIZE)\n+#define DEFAULT_FS_BURST_CAP_SIZE\t(6 * 1024 + 33 * FS_USB_PKT_SIZE)\n+#define DEFAULT_BULK_IN_DELAY\t\t0x00002000\n+#define MAX_SINGLE_PACKET_SIZE\t\t2048\n+#define EEPROM_MAC_OFFSET\t\t0x01\n+#define SMSC95XX_INTERNAL_PHY_ID\t1\n+#define ETH_P_8021Q\t0x8100 /* 802.1Q VLAN Extended Header */\n+\n+/* local defines */\n+#define SMSC95XX_BASE_NAME \"sms\"\n+#define USB_CTRL_SET_TIMEOUT 5000\n+#define USB_CTRL_GET_TIMEOUT 5000\n+#define USB_BULK_SEND_TIMEOUT 5000\n+#define USB_BULK_RECV_TIMEOUT 5000\n+\n+#define AX_RX_URB_SIZE 2048\n+#define PHY_CONNECT_TIMEOUT 5000\n+\n+#define TURBO_MODE\n+\n+/* local vars */\n+static int curr_eth_dev; /* index for name of next device detected */\n+\n+\n+/*\n+ * Smsc95xx infrastructure commands\n+ */\n+static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data)\n+{\n+\tint len;\n+\n+\tcpu_to_le32s(&data);\n+\n+\tlen = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0),\n+\t\tUSB_VENDOR_REQUEST_WRITE_REGISTER,\n+\t\tUSB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,\n+\t\t00, index, &data, sizeof(data), USB_CTRL_SET_TIMEOUT);\n+\tif (len != sizeof(data)) {\n+\t\tdebug(\"smsc95xx_write_reg failed: index=%d, data=%d, len=%d\",\n+\t\t index, data, len);\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data)\n+{\n+\tint len;\n+\n+\tlen = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0),\n+\t\tUSB_VENDOR_REQUEST_READ_REGISTER,\n+\t\tUSB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,\n+\t\t00, index, data, sizeof(data), USB_CTRL_GET_TIMEOUT);\n+\tif (len != sizeof(data)) {\n+\t\tdebug(\"smsc95xx_read_reg failed: index=%d, len=%d\",\n+\t\t index, len);\n+\t\treturn -1;\n+\t}\n+\n+\tle32_to_cpus(data);\n+\treturn 0;\n+}\n+\n+/* Loop until the read is completed with timeout */\n+static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev)\n+{\n+\tunsigned long start_time = get_timer(0);\n+\tu32 val;\n+\n+\tdo {\n+\t\tsmsc95xx_read_reg(dev, MII_ADDR, &val);\n+\t\tif (!(val & MII_BUSY_))\n+\t\t\treturn 0;\n+\t} while (get_timer(start_time) < 1 * 1000 * 1000);\n+\n+\treturn -1;\n+}\n+\n+static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx)\n+{\n+\tu32 val, addr;\n+\n+\t/* confirm MII not busy */\n+\tif (smsc95xx_phy_wait_not_busy(dev)) {\n+\t\tdebug(\"MII is busy in smsc95xx_mdio_read\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* set the address, index & direction (read from PHY) */\n+\taddr = (phy_id << 11) | (idx << 6) | MII_READ_;\n+\tsmsc95xx_write_reg(dev, MII_ADDR, addr);\n+\n+\tif (smsc95xx_phy_wait_not_busy(dev)) {\n+\t\tdebug(\"Timed out reading MII reg %02X\\n\", idx);\n+\t\treturn -1;\n+\t}\n+\n+\tsmsc95xx_read_reg(dev, MII_DATA, &val);\n+\n+\treturn (u16)(val & 0xFFFF);\n+}\n+\n+static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx,\n+\t\t\t\tint regval)\n+{\n+\tu32 val, addr;\n+\n+\t/* confirm MII not busy */\n+\tif (smsc95xx_phy_wait_not_busy(dev)) {\n+\t\tdebug(\"MII is busy in smsc95xx_mdio_write\\n\");\n+\t\treturn;\n+\t}\n+\n+\tval = regval;\n+\tsmsc95xx_write_reg(dev, MII_DATA, val);\n+\n+\t/* set the address, index & direction (write to PHY) */\n+\taddr = (phy_id << 11) | (idx << 6) | MII_WRITE_;\n+\tsmsc95xx_write_reg(dev, MII_ADDR, addr);\n+\n+\tif (smsc95xx_phy_wait_not_busy(dev))\n+\t\tdebug(\"Timed out writing MII reg %02X\\n\", idx);\n+}\n+\n+static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev)\n+{\n+\tunsigned long start_time = get_timer(0);\n+\tu32 val;\n+\n+\tdo {\n+\t\tsmsc95xx_read_reg(dev, E2P_CMD, &val);\n+\t\tif (!(val & E2P_CMD_LOADED_)) {\n+\t\t\tdebug(\"No EEPROM present\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif (!(val & E2P_CMD_BUSY_))\n+\t\t\treturn 0;\n+\t\tudelay(40);\n+\t} while (get_timer(start_time) < 1 * 1000 * 1000);\n+\n+\tdebug(\"EEPROM is busy\\n\");\n+\treturn -1;\n+}\n+\n+static int smsc95xx_wait_eeprom(struct ueth_data *dev)\n+{\n+\tunsigned long start_time = get_timer(0);\n+\tu32 val;\n+\n+\tdo {\n+\t\tsmsc95xx_read_reg(dev, E2P_CMD, &val);\n+\t\tif (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))\n+\t\t\tbreak;\n+\t\tudelay(40);\n+\t} while (get_timer(start_time) < 1 * 1000 * 1000);\n+\n+\tif (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {\n+\t\tdebug(\"EEPROM read operation timeout\\n\");\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length,\n+\t\t\t\tu8 *data)\n+{\n+\tu32 val;\n+\tint i, ret;\n+\n+\tret = smsc95xx_eeprom_confirm_not_busy(dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0; i < length; i++) {\n+\t\tval = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);\n+\t\tsmsc95xx_write_reg(dev, E2P_CMD, val);\n+\n+\t\tret = smsc95xx_wait_eeprom(dev);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tsmsc95xx_read_reg(dev, E2P_DATA, &val);\n+\t\tdata[i] = val & 0xFF;\n+\t\toffset++;\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * mii_nway_restart - restart NWay (autonegotiation) for this interface\n+ *\n+ * Returns 0 on success, negative on error.\n+ */\n+static int mii_nway_restart(struct ueth_data *dev)\n+{\n+\tint bmcr;\n+\tint r = -1;\n+\n+\t/* if autoneg is off, it's an error */\n+\tbmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR);\n+\n+\tif (bmcr & BMCR_ANENABLE) {\n+\t\tbmcr |= BMCR_ANRESTART;\n+\t\tsmsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);\n+\t\tr = 0;\n+\t}\n+\treturn r;\n+}\n+\n+static int smsc95xx_phy_initialize(struct ueth_data *dev)\n+{\n+\tsmsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);\n+\tsmsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE,\n+\t\tADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |\n+\t\tADVERTISE_PAUSE_ASYM);\n+\n+\t/* read to clear */\n+\tsmsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC);\n+\n+\tsmsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK,\n+\t\tPHY_INT_MASK_DEFAULT_);\n+\tmii_nway_restart(dev);\n+\n+\tdebug(\"phy initialised succesfully\\n\");\n+\treturn 0;\n+}\n+\n+static int smsc95xx_init_mac_address(struct eth_device *eth,\n+\t\tstruct ueth_data *dev)\n+{\n+\t/* try reading mac address from EEPROM */\n+\tif (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,\n+\t\t\teth->enetaddr) == 0) {\n+\t\tif (is_valid_ether_addr(eth->enetaddr)) {\n+\t\t\t/* eeprom values are valid so use them */\n+\t\t\tdebug(\"MAC address read from EEPROM\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\t/*\n+\t * No eeprom, or eeprom values are invalid. Generating a random MAC\n+\t * address is not safe. Just return an error.\n+\t */\n+\treturn -1;\n+}\n+\n+static int smsc95xx_write_hwaddr(struct eth_device *eth)\n+{\n+\tstruct ueth_data *dev = (struct ueth_data *)eth->priv;\n+\tu32 addr_lo, addr_hi;\n+\tint ret;\n+\n+\t/* set hardware address */\n+\tdebug(\"** %s()\\n\", __func__);\n+\taddr_lo = cpu_to_le32(*((u32 *)eth->enetaddr));\n+\taddr_hi = cpu_to_le16(*((u16 *)(eth->enetaddr + 4)));\n+\tret = smsc95xx_write_reg(dev, ADDRL, addr_lo);\n+\tif (ret < 0) {\n+\t\tdebug(\"Failed to write ADDRL: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = smsc95xx_write_reg(dev, ADDRH, addr_hi);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tdebug(\"MAC %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n+\t\teth->enetaddr[0], eth->enetaddr[1],\n+\t\teth->enetaddr[2], eth->enetaddr[3],\n+\t\teth->enetaddr[4], eth->enetaddr[5]);\n+\tdev->have_hwaddr = 1;\n+\treturn 0;\n+}\n+\n+/* Enable or disable Tx & Rx checksum offload engines */\n+static int smsc95xx_set_csums(struct ueth_data *dev,\n+\t\tint use_tx_csum, int use_rx_csum)\n+{\n+\tu32 read_buf;\n+\tint ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (use_tx_csum)\n+\t\tread_buf |= Tx_COE_EN_;\n+\telse\n+\t\tread_buf &= ~Tx_COE_EN_;\n+\n+\tif (use_rx_csum)\n+\t\tread_buf |= Rx_COE_EN_;\n+\telse\n+\t\tread_buf &= ~Rx_COE_EN_;\n+\n+\tret = smsc95xx_write_reg(dev, COE_CR, read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tdebug(\"COE_CR = 0x%08x\\n\", read_buf);\n+\treturn 0;\n+}\n+\n+static void smsc95xx_set_multicast(struct ueth_data *dev)\n+{\n+\t/* No multicast in u-boot */\n+\tdev->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);\n+}\n+\n+/* starts the TX path */\n+static void smsc95xx_start_tx_path(struct ueth_data *dev)\n+{\n+\tu32 reg_val;\n+\n+\t/* Enable Tx at MAC */\n+\tdev->mac_cr |= MAC_CR_TXEN_;\n+\n+\tsmsc95xx_write_reg(dev, MAC_CR, dev->mac_cr);\n+\n+\t/* Enable Tx at SCSRs */\n+\treg_val = TX_CFG_ON_;\n+\tsmsc95xx_write_reg(dev, TX_CFG, reg_val);\n+}\n+\n+/* Starts the Receive path */\n+static void smsc95xx_start_rx_path(struct ueth_data *dev)\n+{\n+\tdev->mac_cr |= MAC_CR_RXEN_;\n+\tsmsc95xx_write_reg(dev, MAC_CR, dev->mac_cr);\n+}\n+\n+/*\n+ * Smsc95xx callbacks\n+ */\n+static int smsc95xx_init(struct eth_device *eth, bd_t *bd)\n+{\n+\tint ret;\n+\tu32 write_buf;\n+\tu32 read_buf;\n+\tu32 burst_cap;\n+\tint timeout;\n+\tstruct ueth_data *dev = (struct ueth_data *)eth->priv;\n+#define TIMEOUT_RESOLUTION 50\t/* ms */\n+\tint link_detected;\n+\n+\tdebug(\"** %s()\\n\", __func__);\n+\tdev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */\n+\n+\twrite_buf = HW_CFG_LRST_;\n+\tret = smsc95xx_write_reg(dev, HW_CFG, write_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\ttimeout = 0;\n+\tdo {\n+\t\tret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\tudelay(10 * 1000);\n+\t\ttimeout++;\n+\t} while ((read_buf & HW_CFG_LRST_) && (timeout < 100));\n+\n+\tif (timeout >= 100) {\n+\t\tdebug(\"timeout waiting for completion of Lite Reset\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\twrite_buf = PM_CTL_PHY_RST_;\n+\tret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\ttimeout = 0;\n+\tdo {\n+\t\tret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\tudelay(10 * 1000);\n+\t\ttimeout++;\n+\t} while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));\n+\tif (timeout >= 100) {\n+\t\tdebug(\"timeout waiting for PHY Reset\\n\");\n+\t\treturn -1;\n+\t}\n+\tif (!dev->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0)\n+\t\tdev->have_hwaddr = 1;\n+\tif (!dev->have_hwaddr) {\n+\t\tputs(\"Error: SMSC95xx: No MAC address set - set usbethaddr\\n\");\n+\t\treturn -1;\n+\t}\n+\tif (smsc95xx_write_hwaddr(eth) < 0)\n+\t\treturn -1;\n+\n+\tret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tdebug(\"Read Value from HW_CFG : 0x%08x\\n\", read_buf);\n+\n+\tread_buf |= HW_CFG_BIR_;\n+\tret = smsc95xx_write_reg(dev, HW_CFG, read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tdebug(\"Read Value from HW_CFG after writing \"\n+\t\t\"HW_CFG_BIR_: 0x%08x\\n\", read_buf);\n+\n+#ifdef TURBO_MODE\n+\tif (dev->pusb_dev->speed == USB_SPEED_HIGH) {\n+\t\tburst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;\n+\t\tdev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;\n+\t} else {\n+\t\tburst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;\n+\t\tdev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;\n+\t}\n+#else\n+\tburst_cap = 0;\n+\tdev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;\n+#endif\n+\tdebug(\"rx_urb_size=%ld\\n\", (ulong)dev->rx_urb_size);\n+\n+\tret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tdebug(\"Read Value from BURST_CAP after writing: 0x%08x\\n\", read_buf);\n+\n+\tread_buf = DEFAULT_BULK_IN_DELAY;\n+\tret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tdebug(\"Read Value from BULK_IN_DLY after writing: \"\n+\t\t\t\"0x%08x\\n\", read_buf);\n+\n+\tret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tdebug(\"Read Value from HW_CFG: 0x%08x\\n\", read_buf);\n+\n+#ifdef TURBO_MODE\n+\tread_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);\n+#endif\n+\tread_buf &= ~HW_CFG_RXDOFF_;\n+\n+#define NET_IP_ALIGN 0\n+\tread_buf |= NET_IP_ALIGN << 9;\n+\n+\tret = smsc95xx_write_reg(dev, HW_CFG, read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tdebug(\"Read Value from HW_CFG after writing: 0x%08x\\n\", read_buf);\n+\n+\twrite_buf = 0xFFFFFFFF;\n+\tret = smsc95xx_write_reg(dev, INT_STS, write_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = smsc95xx_read_reg(dev, ID_REV, &read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tdebug(\"ID_REV = 0x%08x\\n\", read_buf);\n+\n+\t/* Init Tx */\n+\twrite_buf = 0;\n+\tret = smsc95xx_write_reg(dev, FLOW, write_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tread_buf = AFC_CFG_DEFAULT;\n+\tret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = smsc95xx_read_reg(dev, MAC_CR, &dev->mac_cr);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* Init Rx. Set Vlan */\n+\twrite_buf = (u32)ETH_P_8021Q;\n+\tret = smsc95xx_write_reg(dev, VLAN1, write_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* Disable checksum offload engines */\n+\tret = smsc95xx_set_csums(dev, 0, 0);\n+\tif (ret < 0) {\n+\t\tdebug(\"Failed to set csum offload: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tsmsc95xx_set_multicast(dev);\n+\n+\tif (smsc95xx_phy_initialize(dev) < 0)\n+\t\treturn -1;\n+\tret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* enable PHY interrupts */\n+\tread_buf |= INT_EP_CTL_PHY_INT_;\n+\n+\tret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tsmsc95xx_start_tx_path(dev);\n+\tsmsc95xx_start_rx_path(dev);\n+\n+\ttimeout = 0;\n+\tdo {\n+\t\tlink_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR)\n+\t\t\t& BMSR_LSTATUS;\n+\t\tif (!link_detected) {\n+\t\t\tif (timeout == 0)\n+\t\t\t\tprintf(\"Waiting for Ethernet connection... \");\n+\t\t\tudelay(TIMEOUT_RESOLUTION * 1000);\n+\t\t\ttimeout += TIMEOUT_RESOLUTION;\n+\t\t}\n+\t} while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);\n+\tif (link_detected) {\n+\t\tif (timeout != 0)\n+\t\t\tprintf(\"done.\\n\");\n+\t} else {\n+\t\tprintf(\"unable to connect.\\n\");\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+static int smsc95xx_send(struct eth_device *eth, volatile void* packet,\n+\t\t\t int length)\n+{\n+\tstruct ueth_data *dev = (struct ueth_data *)eth->priv;\n+\tint err;\n+\tint actual_len;\n+\tu32 tx_cmd_a;\n+\tu32 tx_cmd_b;\n+\tunsigned char msg[PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)];\n+\n+\tdebug(\"** %s(), len %d, buf %#x\\n\", __func__, length, (int)msg);\n+\tif (length > PKTSIZE)\n+\t\treturn -1;\n+\n+\ttx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;\n+\ttx_cmd_b = (u32)length;\n+\tcpu_to_le32s(&tx_cmd_a);\n+\tcpu_to_le32s(&tx_cmd_b);\n+\n+\t/* prepend cmd_a and cmd_b */\n+\tmemcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));\n+\tmemcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));\n+\tmemcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,\n+\t length);\n+\terr = usb_bulk_msg(dev->pusb_dev,\n+\t\t\t\tusb_sndbulkpipe(dev->pusb_dev, dev->ep_out),\n+\t\t\t\t(void *)msg,\n+\t\t\t\tlength + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),\n+\t\t\t\t&actual_len,\n+\t\t\t\tUSB_BULK_SEND_TIMEOUT);\n+\tdebug(\"Tx: len = %u, actual = %u, err = %d\\n\",\n+\t length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),\n+\t actual_len, err);\n+\treturn err;\n+}\n+\n+static int smsc95xx_recv(struct eth_device *eth)\n+{\n+\tstruct ueth_data *dev = (struct ueth_data *)eth->priv;\n+\tstatic unsigned char recv_buf[AX_RX_URB_SIZE];\n+\tunsigned char *buf_ptr;\n+\tint err;\n+\tint actual_len;\n+\tu32 packet_len;\n+\tint cur_buf_align;\n+\n+\tdebug(\"** %s()\\n\", __func__);\n+\terr = usb_bulk_msg(dev->pusb_dev,\n+\t\t\t\tusb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),\n+\t\t\t\t(void *)recv_buf,\n+\t\t\t\tAX_RX_URB_SIZE,\n+\t\t\t\t&actual_len,\n+\t\t\t\tUSB_BULK_RECV_TIMEOUT);\n+\tdebug(\"Rx: len = %u, actual = %u, err = %d\\n\", AX_RX_URB_SIZE,\n+\t actual_len, err);\n+\tif (err != 0) {\n+\t\tdebug(\"Rx: failed to receive\\n\");\n+\t\treturn -1;\n+\t}\n+\tif (actual_len > AX_RX_URB_SIZE) {\n+\t\tdebug(\"Rx: received too many bytes %d\\n\", actual_len);\n+\t\treturn -1;\n+\t}\n+\n+\tbuf_ptr = recv_buf;\n+\twhile (actual_len > 0) {\n+\t\t/*\n+\t\t * 1st 4 bytes contain the length of the actual data plus error\n+\t\t * info. Extract data length.\n+\t\t */\n+\t\tif (actual_len < sizeof(packet_len)) {\n+\t\t\tdebug(\"Rx: incomplete packet length\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tmemcpy(&packet_len, buf_ptr, sizeof(packet_len));\n+\t\tle32_to_cpus(&packet_len);\n+\t\tif (packet_len & RX_STS_ES_) {\n+\t\t\tdebug(\"Rx: Error header=%#x\", packet_len);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tpacket_len = ((packet_len & RX_STS_FL_) >> 16);\n+\n+\t\tif (packet_len > actual_len - sizeof(packet_len)) {\n+\t\t\tdebug(\"Rx: too large packet: %d\\n\", packet_len);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\t/* Notify net stack */\n+\t\tNetReceive(buf_ptr + sizeof(packet_len), packet_len - 4);\n+\n+\t\t/* Adjust for next iteration */\n+\t\tactual_len -= sizeof(packet_len) + packet_len;\n+\t\tbuf_ptr += sizeof(packet_len) + packet_len;\n+\t\tcur_buf_align = (int)buf_ptr - (int)recv_buf;\n+\n+\t\tif (cur_buf_align & 0x03) {\n+\t\t\tint align = 4 - (cur_buf_align & 0x03);\n+\n+\t\t\tactual_len -= align;\n+\t\t\tbuf_ptr += align;\n+\t\t}\n+\t}\n+\treturn err;\n+}\n+\n+static void smsc95xx_halt(struct eth_device *eth)\n+{\n+\tdebug(\"** %s()\\n\", __func__);\n+}\n+\n+/*\n+ * SMSC probing functions\n+ */\n+void smsc95xx_eth_before_probe(void)\n+{\n+\tcurr_eth_dev = 0;\n+}\n+\n+struct smsc95xx_dongle {\n+\tunsigned short vendor;\n+\tunsigned short product;\n+};\n+\n+static const struct smsc95xx_dongle smsc95xx_dongles[] = {\n+\t{ 0x0424, 0xec00 },\t/* LAN9512/LAN9514 Ethernet */\n+\t{ 0x0424, 0x9500 },\t/* LAN9500 Ethernet */\n+\t{ 0x0000, 0x0000 }\t/* END - Do not remove */\n+};\n+\n+/* Probe to see if a new device is actually an SMSC device */\n+int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,\n+\t\t struct ueth_data *ss)\n+{\n+\tstruct usb_interface *iface;\n+\tstruct usb_interface_descriptor *iface_desc;\n+\tint i;\n+\n+\t/* let's examine the device now */\n+\tiface = &dev->config.if_desc[ifnum];\n+\tiface_desc = &dev->config.if_desc[ifnum].desc;\n+\n+\tfor (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {\n+\t\tif (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&\n+\t\t dev->descriptor.idProduct == smsc95xx_dongles[i].product)\n+\t\t\t/* Found a supported dongle */\n+\t\t\tbreak;\n+\t}\n+\tif (smsc95xx_dongles[i].vendor == 0)\n+\t\treturn 0;\n+\n+\t/* At this point, we know we've got a live one */\n+\tdebug(\"\\n\\nUSB Ethernet device detected\\n\");\n+\tmemset(ss, '\\0', sizeof(struct ueth_data));\n+\n+\t/* Initialize the ueth_data structure with some useful info */\n+\tss->ifnum = ifnum;\n+\tss->pusb_dev = dev;\n+\tss->subclass = iface_desc->bInterfaceSubClass;\n+\tss->protocol = iface_desc->bInterfaceProtocol;\n+\n+\t/*\n+\t * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.\n+\t * We will ignore any others.\n+\t */\n+\tfor (i = 0; i < iface_desc->bNumEndpoints; i++) {\n+\t\t/* is it an BULK endpoint? */\n+\t\tif ((iface->ep_desc[i].bmAttributes &\n+\t\t USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {\n+\t\t\tif (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)\n+\t\t\t\tss->ep_in =\n+\t\t\t\t\tiface->ep_desc[i].bEndpointAddress &\n+\t\t\t\t\tUSB_ENDPOINT_NUMBER_MASK;\n+\t\t\telse\n+\t\t\t\tss->ep_out =\n+\t\t\t\t\tiface->ep_desc[i].bEndpointAddress &\n+\t\t\t\t\tUSB_ENDPOINT_NUMBER_MASK;\n+\t\t}\n+\n+\t\t/* is it an interrupt endpoint? */\n+\t\tif ((iface->ep_desc[i].bmAttributes &\n+\t\t USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {\n+\t\t\tss->ep_int = iface->ep_desc[i].bEndpointAddress &\n+\t\t\t\tUSB_ENDPOINT_NUMBER_MASK;\n+\t\t\tss->irqinterval = iface->ep_desc[i].bInterval;\n+\t\t}\n+\t}\n+\tdebug(\"Endpoints In %d Out %d Int %d\\n\",\n+\t\t ss->ep_in, ss->ep_out, ss->ep_int);\n+\n+\t/* Do some basic sanity checks, and bail if we find a problem */\n+\tif (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||\n+\t !ss->ep_in || !ss->ep_out || !ss->ep_int) {\n+\t\tdebug(\"Problems with device\\n\");\n+\t\treturn 0;\n+\t}\n+\tdev->privptr = (void *)ss;\n+\treturn 1;\n+}\n+\n+int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,\n+\t\t\t\tstruct eth_device *eth)\n+{\n+\tdebug(\"** %s()\\n\", __func__);\n+\tif (!eth) {\n+\t\tdebug(\"%s: missing parameter.\\n\", __func__);\n+\t\treturn 0;\n+\t}\n+\tsprintf(eth->name, \"%s%d\", SMSC95XX_BASE_NAME, curr_eth_dev++);\n+\teth->init = smsc95xx_init;\n+\teth->send = smsc95xx_send;\n+\teth->recv = smsc95xx_recv;\n+\teth->halt = smsc95xx_halt;\n+\teth->write_hwaddr = smsc95xx_write_hwaddr;\n+\teth->priv = ss;\n+\treturn 1;\n+}\ndiff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c\nindex 68a0883..7b55da3 100644\n--- a/drivers/usb/eth/usb_ether.c\n+++ b/drivers/usb/eth/usb_ether.c\n@@ -45,6 +45,13 @@ static const struct usb_eth_prob_dev prob_dev[] = {\n \t\t.get_info = asix_eth_get_info,\n \t},\n #endif\n+#ifdef CONFIG_USB_ETHER_SMSC95XX\n+\t{\n+\t\t.before_probe = smsc95xx_eth_before_probe,\n+\t\t.probe = smsc95xx_eth_probe,\n+\t\t.get_info = smsc95xx_eth_get_info,\n+\t},\n+#endif\n \t{ },\t\t/* END */\n };\n \ndiff --git a/include/usb_ether.h b/include/usb_ether.h\nindex 825c275..a7fb26b 100644\n--- a/include/usb_ether.h\n+++ b/include/usb_ether.h\n@@ -51,6 +51,11 @@ struct ueth_data {\n \tunsigned char\tirqinterval;\t/* Intervall for IRQ Pipe */\n \n \t/* private fields for each driver can go here if needed */\n+#ifdef CONFIG_USB_ETHER_SMSC95XX\n+\tsize_t rx_urb_size; /* maximum USB URB size */\n+\tu32 mac_cr; /* MAC control register value */\n+\tint have_hwaddr; /* 1 if we have a hardware MAC address */\n+#endif\n };\n \n /*\n@@ -65,4 +70,12 @@ int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,\n \t\t struct eth_device *eth);\n #endif\n \n+#ifdef CONFIG_USB_ETHER_SMSC95XX\n+void smsc95xx_eth_before_probe(void);\n+int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,\n+\t\t\tstruct ueth_data *ss);\n+int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,\n+\t\t\tstruct eth_device *eth);\n+#endif\n+\n #endif /* __USB_ETHER_H__ */\n", "prefixes": [ "U-Boot", "v8", "1/4" ] }