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{ "id": 953992, "url": "http://patchwork.ozlabs.org/api/covers/953992/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T16:59:27", "name": "[v7,00/80] Add nanoMIPS support to QEMU", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/953992/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kkTk53Gmz9ryt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:02:18 +1000 (AEST)", "from localhost ([::1]:35163 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmitb-000235-OV\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:02:15 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52003)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmit3-00021K-Nc\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:01:43 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmit1-0003v3-2q\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:01:41 -0400", "from mx2.rt-rk.com ([89.216.37.149]:41365 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmit0-0003Y5-Ma\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:01:39 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 659BE1A2123;\n\tMon, 6 Aug 2018 19:01:14 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 2F1E01A211D;\n\tMon, 6 Aug 2018 19:01:14 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 18:59:27 +0200", "Message-Id": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 00/80] Add nanoMIPS support to QEMU", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Aleksandar Markovic <amarkovic@wavecomp.com>\n\nv6->v7:\n\n - found better place for MIPS_ARCH in elf.h\n - improved patch for LLWP and SCWP\n - fixed missing availability control, alignment, usage\n of extract32() in DSP patches\n - added disassembler support for microMIPS and nanoMIPS\n - removed unnecessary addition of one empty line in the\n patch on WR bit\n - improved statx() syscall translation\n - improved nanoMIPS items in binfmt script\n - amended pre-nanoMIPS items in qemu-doc.texi\n - added nanoMIPS items in qemu-doc.texi\n - changed slightly patch order to be logicaly more\n comprehensive \n - rebased to the latest code\n - NOTE: there will be some sheckpatch.pl errors and warning\n for this series; however, we think those are flase positives\n in these particular circumstances - therefore we will not\n change any patch related to these checkpatch.pl messages\n\nv5->v6:\n\n - used names offset and imm instead of rd and rs when\n appropriate\n - used gen_op_addr_addi when appropriate in one more place\n - avoided usage of tcg_temp_local_new\n - avoided unnecesary sign extension related to addr_add\n - fixed unprotected storing to cpu_gpr[0]\n - removed some unnecesary testing for ISA_NANOMIPS\n - updated patch for LLWP and SCWP\n - extract32 inserted instead of shift/mask in DSP patches\n - removed useless casts from DSP patches\n - reorganized functions to eliminated duplicated loading of\n gpr values into tcg variables in DSP patches\n - check Config1.WR bit for Watch registers only when using\n in runtime\n - removed duplicated check for bad address in PC register\n - added support for statx system call\n - updated script qemu-binfmt-conf.sh for nanoMIPS\n - rebased to the latest code\n\nv4->v5:\n\n - merged series \"Mips maintenance and misc fixes and improvements\"\n and this one for easier handling (there are build dependencies)\n - eliminated shadow variables from translate.c\n - replaced shift/mask combination with extract32()\n - added new function gen_op_addr_addi()\n - added patch for LLWP and SCWP\n - added \"fall through\" comments at appropriate places\n - eliminated micromips flag from I7200 definition\n - numerous other enhancements originating from reviewer's\n comments\n - some of the patches split into two or more for easier\n handling and review\n - rebased to the latest code\n\nv3->v4:\n\n - added support for nanoMIPS user mode functionality and\n configuration\n - DSP patch split into three for easier review and handling\n - corrected indentation in all decoding engine patches\n - shift/mask replaced with equivalent extract32() in some\n patches\n - added missing default cases in some patches\n - refactored invocation logic aroung decode_nanomips_opc()\n - improved comments before decode_gpr_XXX() utilities\n - all four decode_gpr_XXX() are now in a single patch\n - two patches on updating BadInstr and related registers\n are now merged, and execution logic improved\n - minor formatting corrections\n - rebased to the latest code\n\nv2->v3:\n\n - added support for nanoMIPS-specifics in ELF headers\n - added support for CP0 Config0.WR bit\n - updated I7200 definition\n - improved indentation of some switch statements\n - slight reorganization of patches (splitting, order)\n - rebased to the latest code\n\nv1->v2:\n\n - added DSP ASE support\n - added MT ASE support\n - added GDB XML support\n - order of patches changed\n - commit messages and patch title improved accross the board\n - obsolete email addresses for authors and cosigners replaced\n with the right ones\n - some functions renamed to reflect better the documentation\n - some macros renamed to reflect better their nanoMIPS nature\n - streamlined formatting\n - some of other reviewer's comments addressed, but the majority\n was not; this is because the focus of this version was on\n completing the functionality as much as possible; remaining\n comments will be addressed in the subsequent versions of this\n series\n\nThis series of patches implements recently announced nanoMIPS on QEMU.\nnanoMIPS is a variable length ISA containing 16, 32 and 48-bit wide\ninstructions. It is designed to be portable at assembly level with\nother MIPS and microMIPS code, but contains a number of changes that\nenhance code density and efficiency. The largest portion of patches\nis nanoMIPS decoding engine.\n\nFor more information, please refer to the following link:\n\nhttps://www.mips.com/products/architectures/nanomips/\n\nAleksandar Markovic (16):\n MAINTAINERS: Update target/mips maintainer's email addresses\n target/mips: Avoid case statements formulated by ranges\n target/mips: Mark switch fallthroughs with interpretable comments\n target/mips: Fix two instances of shadow variables\n target/mips: Update some CP0 registers bit definitions\n elf: Remove duplicate preprocessor constant definition\n elf: Add ELF flags for MIPS machine variants\n linux-user: Update MIPS syscall numbers up to kernel 4.18 headers\n target/mips: Add preprocessor constants for nanoMIPS\n target/mips: Add placeholder and invocation of decode_nanomips_opc()\n target/mips: Add nanoMIPS decoding and extraction utilities\n elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too\n elf: Don't check FCR31_NAN2008 bit for nanoMIPS\n linux-user: Update syscall_defs.h header for nanoMIPS\n qemu-doc: Amend MIPS-related items\n qemu-doc: Add nanoMIPS-related items\n\nAleksandar Rikalo (13):\n linux-user: Add preprocessor availability control to some syscalls\n target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair\n elf: Add nanoMIPS specific variations in ELF header fields\n linux-user: Add syscall numbers for nanoMIPS\n linux-user: Add target_signal.h header for nanoMIPS\n linux-user: Add termbits.h header for nanoMIPS\n linux-user: Add target_fcntl.h header for nanoMIPS\n linux-user: Add sockbits.h header for nanoMIPS\n linux-user: Add target_syscall.h header for nanoMIPS\n linux-user: Add support for nanoMIPS signal trampoline\n linux-user: Amend support for sigaction() syscall for nanoMIPS\n linux-user: Add support for statx() syscall for all platforms\n linux-user: Add nanoMIPS support in scripts/qemu-binfmt-conf.sh\n\nDimitrije Nikolic (5):\n linux-user: Add target_cpu.h header for nanoMIPS\n linux-user: Add target_structs.h header for nanoMIPS\n linux-user: Add target_elf.h header for nanoMIPS\n linux-user: Add signal.c for nanoMIPS\n linux-user: Add cpu_loop.c for nanoMIPS\n\nJames Hogan (5):\n target/mips: Implement emulation of nanoMIPS EXTW instruction\n target/mips: Adjust exception_resume_pc() for nanoMIPS\n target/mips: Adjust set_hflags_for_handler() for nanoMIPS\n target/mips: Adjust set_pc() for nanoMIPS\n gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub\n\nMatthew Fortune (5):\n target/mips: Add emulation of nanoMIPS 16-bit save and restore\n instructions\n target/mips: Implement emulation of nanoMIPS ROTX instruction\n disas: Add support for microMIPS and nanoMIPS\n target/mips: Add handling of branch delay slots for nanoMIPS\n mips_malta: Add basic nanoMIPS boot code for MIPS' Malta\n\nPaul Burton (1):\n mips_malta: Setup GT64120 BARs in nanoMIPS bootloader\n\nStefan Markovic (16):\n target/mips: Add CP0 BadInstrX register\n target/mips: Add gen_op_addr_addi()\n target/mips: Add nanoMIPS DSP ASE opcodes\n target/mips: Implement MT ASE support for nanoMIPS\n target/mips: Add emulation of DSP ASE for nanoMIPS - part 1\n target/mips: Add emulation of DSP ASE for nanoMIPS - part 2\n target/mips: Add emulation of DSP ASE for nanoMIPS - part 3\n target/mips: Add emulation of DSP ASE for nanoMIPS - part 4\n target/mips: Add emulation of DSP ASE for nanoMIPS - part 5\n target/mips: Add emulation of DSP ASE for nanoMIPS - part 6\n target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS\n target/mips: Implement CP0 Config1.WR bit functionality\n mips_malta: Fix semihosting argument passing for nanoMIPS bare metal\n gdbstub: Add XML support for GDB for nanoMIPS\n target/mips: Add definition of nanoMIPS I7200 CPU\n linux-user: Add nanoMIPS linux user mode configuration support\n\nYongbok Kim (19):\n target/mips: Don't update BadVAddr register in Debug Mode\n target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0\n target/mips: Add nanoMIPS base instruction set opcodes\n target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions\n target/mips: Add emulation of nanoMIPS 16-bit branch instructions\n target/mips: Add emulation of nanoMIPS 16-bit shift instructions\n target/mips: Add emulation of nanoMIPS 16-bit misc instructions\n target/mips: Add emulation of nanoMIPS 16-bit load and store\n instructions\n target/mips: Add emulation of nanoMIPS 16-bit logic instructions\n target/mips: Add emulation of some common nanoMIPS 32-bit instructions\n target/mips: Add emulation of nanoMIPS instructions MOVE.P and\n MOVE.PREV\n target/mips: Add emulation of nanoMIPS 48-bit instructions\n target/mips: Add emulation of nanoMIPS FP instructions\n target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)\n target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)\n target/mips: Add emulation of misc nanoMIPS instructions (p_lsx)\n target/mips: Add emulation of nanoMIPS 32-bit load and store\n instructions\n target/mips: Add emulation of nanoMIPS 32-bit branch instructions\n target/mips: Fix ERET/ERETNC behavior related to ADEL exception\n\n .mailmap | 7 +-\n MAINTAINERS | 12 +-\n configure | 13 +-\n default-configs/nanomips-linux-user.mak | 1 +\n disas/Makefile.objs | 1 +\n disas/mips.c | 358 +-\n disas/nanomips.cpp | 15752 ++++++++++++++++++++++++++++++\n disas/nanomips.h | 1208 +++\n gdb-xml/nanomips-cp0.xml | 13 +\n gdb-xml/nanomips-cpu.xml | 44 +\n gdb-xml/nanomips-dsp.xml | 20 +\n gdb-xml/nanomips-fpu.xml | 45 +\n gdb-xml/nanomips-linux.xml | 20 +\n hw/mips/mips_malta.c | 153 +-\n include/disas/bfd.h | 1 +\n include/elf.h | 44 +-\n linux-user/elfload.c | 2 +\n linux-user/mips/cpu_loop.c | 36 +-\n linux-user/mips/signal.c | 36 +-\n linux-user/mips/syscall_nr.h | 9 +\n linux-user/mips/termbits.h | 4 +\n linux-user/mips64/syscall_nr.h | 18 +\n linux-user/nanomips/cpu_loop.c | 1 +\n linux-user/nanomips/signal.c | 1 +\n linux-user/nanomips/sockbits.h | 1 +\n linux-user/nanomips/syscall_nr.h | 275 +\n linux-user/nanomips/target_cpu.h | 21 +\n linux-user/nanomips/target_elf.h | 14 +\n linux-user/nanomips/target_fcntl.h | 38 +\n linux-user/nanomips/target_signal.h | 22 +\n linux-user/nanomips/target_structs.h | 1 +\n linux-user/nanomips/target_syscall.h | 30 +\n linux-user/nanomips/termbits.h | 1 +\n linux-user/strace.c | 14 +-\n linux-user/syscall.c | 147 +-\n linux-user/syscall_defs.h | 95 +-\n qemu-doc.texi | 15 +-\n scripts/qemu-binfmt-conf.sh | 16 +-\n target/mips/cpu.c | 12 +-\n target/mips/cpu.h | 160 +-\n target/mips/gdbstub.c | 13 +-\n target/mips/helper.c | 35 +-\n target/mips/helper.h | 2 +\n target/mips/machine.c | 5 +-\n target/mips/mips-defs.h | 4 +\n target/mips/op_helper.c | 113 +-\n target/mips/translate.c | 5029 +++++++++-\n target/mips/translate_init.inc.c | 39 +\n 48 files changed, 23651 insertions(+), 250 deletions(-)\n create mode 100644 default-configs/nanomips-linux-user.mak\n create mode 100644 disas/nanomips.cpp\n create mode 100644 disas/nanomips.h\n create mode 100644 gdb-xml/nanomips-cp0.xml\n create mode 100644 gdb-xml/nanomips-cpu.xml\n create mode 100644 gdb-xml/nanomips-dsp.xml\n create mode 100644 gdb-xml/nanomips-fpu.xml\n create mode 100644 gdb-xml/nanomips-linux.xml\n create mode 100644 linux-user/nanomips/cpu_loop.c\n create mode 100644 linux-user/nanomips/signal.c\n create mode 100644 linux-user/nanomips/sockbits.h\n create mode 100644 linux-user/nanomips/syscall_nr.h\n create mode 100644 linux-user/nanomips/target_cpu.h\n create mode 100644 linux-user/nanomips/target_elf.h\n create mode 100644 linux-user/nanomips/target_fcntl.h\n create mode 100644 linux-user/nanomips/target_signal.h\n create mode 100644 linux-user/nanomips/target_structs.h\n create mode 100644 linux-user/nanomips/target_syscall.h\n create mode 100644 linux-user/nanomips/termbits.h" }