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{ "id": 819488, "url": "http://patchwork.ozlabs.org/api/covers/819488/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/cover/20170928095628.21966-1-thierry.reding@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170928095628.21966-1-thierry.reding@gmail.com>", "list_archive_url": null, "date": "2017-09-28T09:56:12", "name": "[v2,00/16] gpio: Tight IRQ chip integration and banked infrastructure", "submitter": { "id": 26234, "url": "http://patchwork.ozlabs.org/api/people/26234/?format=api", "name": "Thierry Reding", "email": "thierry.reding@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/cover/20170928095628.21966-1-thierry.reding@gmail.com/mbox/", "series": [ { "id": 5529, "url": "http://patchwork.ozlabs.org/api/series/5529/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=5529", "date": "2017-09-28T09:56:12", "name": "gpio: Tight IRQ chip integration and banked infrastructure", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/5529/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/819488/comments/", "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"FX9NjlhD\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2qpY6632z9t5Y\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 28 Sep 2017 19:56:37 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752448AbdI1J4f (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 28 Sep 2017 05:56:35 -0400", "from mail-qk0-f193.google.com ([209.85.220.193]:35870 \"EHLO\n\tmail-qk0-f193.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751082AbdI1J4e (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Thu, 28 Sep 2017 05:56:34 -0400", "by mail-qk0-f193.google.com with SMTP id j5so103527qkd.3;\n\tThu, 28 Sep 2017 02:56:33 -0700 (PDT)", "from localhost\n\t(p200300E41BCC8100EA54DC343767CF80.dip0.t-ipconnect.de.\n\t[2003:e4:1bcc:8100:ea54:dc34:3767:cf80])\n\tby smtp.gmail.com with ESMTPSA id\n\tm203sm735539qke.21.2017.09.28.02.56.32\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 28 Sep 2017 02:56:32 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id;\n\tbh=37wziiYh/zZnlfNQxHGKUKntP3yDPBvVCCxsXKN8xHk=;\n\tb=FX9NjlhDDWPzBeY11SzqDvIpjzyawdkXBwnPt2b65yONBAI2fwAR/RlotfaNu7OO6J\n\tdLRyh6+D723S8SJQUNB0wDWkWgvyfECA1Rf3Z6U6hqWQxrxOgkkTOPQgOJSPvToK6ctV\n\tfauD2wGWjQXMyVK5w2LWEgwxV4hrthQRlZUpXaSEI/GLAOHQ9AbWI7uqfkkF+cCKCJdw\n\t0aYlEl3BVAuFvxZ67Ro5pLqmKtk15LGPlKTpN3W4k3Oco6N2q6CpkLtf9KlkBQeMFacs\n\tP4IAQBH0jyEkWcexJ5UPGSplRI87OC0wn79Kw/SSzAYzJh8Eajm8owZ7Q68uGv65DNgm\n\tIJTw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=37wziiYh/zZnlfNQxHGKUKntP3yDPBvVCCxsXKN8xHk=;\n\tb=q9bkfAn1t/LMqN5pwlc/1kGlQP2YvRj62dfF5JbKXM8t4E+fom9pEJiHTKlCwoD57X\n\tT1PmAa1Yr5cWDyj9EAc/Vx9t6TND04lf0aminbygxpnGetfV4cVMwaM24itJ+efdWb/F\n\tTjBF/PRYTW2MJ5iUDcZOKBZkaHARysFxB/JhJNiokvC1zBO4jyXgs5lWebZFj9qmxEMm\n\t9XTZoKPzXYr5kEnyUFwuPfZaVgplsXqeORi9P0IceCa7N60Q3uBQpycIonhCqqANLpeP\n\t7nEwIaKVPLiEuxIpt7h77rfNUK1u5GAjQhNW+DSfCGrsZoRQweiYv6tLuK9QMvLj4AKB\n\tPm/g==", "X-Gm-Message-State": "AMCzsaWavEzbS9OysS9XUs11j94Q0mgDnjR8Y8OSaIzH6hR7B8is0lIj\n\td0oXT3Yq9zvNSAvx8gwmWPA=", "X-Google-Smtp-Source": "AOwi7QA0mvfqIZ+Y/HaX0Xpi65RWU47T5fG4AjafWBuN6v86OqT7jePR31ZqLAD96hjd1Pkv6illaA==", "X-Received": "by 10.233.237.77 with SMTP id c74mr6231891qkg.256.1506592593287; \n\tThu, 28 Sep 2017 02:56:33 -0700 (PDT)", "From": "Thierry Reding <thierry.reding@gmail.com>", "To": "Linus Walleij <linus.walleij@linaro.org>", "Cc": "Jonathan Hunter <jonathanh@nvidia.com>, linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org", "Subject": "[PATCH v2 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure", "Date": "Thu, 28 Sep 2017 11:56:12 +0200", "Message-Id": "<20170928095628.21966-1-thierry.reding@gmail.com>", "X-Mailer": "git-send-email 2.14.1", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nHi Linus,\n\nhere's the latest series of patches that implement the tighter IRQ chip\nintegration as well as the banked GPIO infrastructure that we had\ndiscussed a couple of weeks/months back.\n\nThe first couple of patches are mostly preparatory work in order to\nconsolidate all IRQ chip related fields in a new structure and create\nthe base functionality for adding IRQ chips.\n\nAfter that, I've added the Tegra186 GPIO support patch that makes use of\nthe new tight integration.\n\nTo round things off the new banked GPIO infrastructure is added (along\nwith some more preparatory work), followed by the conversion of the two\nTegra GPIO drivers to the new infrastructure.\n\nChanges in v2:\n- rename pins to lines for consistent terminology\n- rename gpio_irq_chip_banked_handler() to\n gpio_irq_chip_banked_chained_handler()\n\nThierry\n\nThierry Reding (16):\n gpio: Implement tighter IRQ chip integration\n gpio: Move irqchip into struct gpio_irq_chip\n gpio: Move irqdomain into struct gpio_irq_chip\n gpio: Move irq_base to struct gpio_irq_chip\n gpio: Move irq_handler to struct gpio_irq_chip\n gpio: Move irq_default_type to struct gpio_irq_chip\n gpio: Move irq_chained_parent to struct gpio_irq_chip\n gpio: Move irq_nested into struct gpio_irq_chip\n gpio: Move irq_valid_mask into struct gpio_irq_chip\n gpio: Move lock_key into struct gpio_irq_chip\n gpio: Add Tegra186 support\n gpio: omap: Fix checkpatch warnings\n gpio: omap: Rename struct gpio_bank to struct omap_gpio_bank\n gpio: Add support for banked GPIO controllers\n gpio: tegra: Use banked GPIO infrastructure\n gpio: tegra186: Use banked GPIO infrastructure\n\n Documentation/gpio/driver.txt | 6 +-\n drivers/bcma/driver_gpio.c | 2 +-\n drivers/gpio/Kconfig | 10 +\n drivers/gpio/Makefile | 1 +\n drivers/gpio/gpio-104-dio-48e.c | 2 +-\n drivers/gpio/gpio-104-idi-48.c | 2 +-\n drivers/gpio/gpio-104-idio-16.c | 2 +-\n drivers/gpio/gpio-adnp.c | 2 +-\n drivers/gpio/gpio-altera.c | 4 +-\n drivers/gpio/gpio-aspeed.c | 6 +-\n drivers/gpio/gpio-ath79.c | 2 +-\n drivers/gpio/gpio-brcmstb.c | 2 +-\n drivers/gpio/gpio-crystalcove.c | 2 +-\n drivers/gpio/gpio-dln2.c | 2 +-\n drivers/gpio/gpio-ftgpio010.c | 2 +-\n drivers/gpio/gpio-ingenic.c | 2 +-\n drivers/gpio/gpio-intel-mid.c | 2 +-\n drivers/gpio/gpio-lynxpoint.c | 2 +-\n drivers/gpio/gpio-max732x.c | 2 +-\n drivers/gpio/gpio-merrifield.c | 2 +-\n drivers/gpio/gpio-omap.c | 222 ++++++-----\n drivers/gpio/gpio-pca953x.c | 2 +-\n drivers/gpio/gpio-pcf857x.c | 2 +-\n drivers/gpio/gpio-pci-idio-16.c | 2 +-\n drivers/gpio/gpio-pl061.c | 2 +-\n drivers/gpio/gpio-rcar.c | 2 +-\n drivers/gpio/gpio-reg.c | 4 +-\n drivers/gpio/gpio-stmpe.c | 6 +-\n drivers/gpio/gpio-tc3589x.c | 2 +-\n drivers/gpio/gpio-tegra.c | 203 +++++-----\n drivers/gpio/gpio-tegra186.c | 571 ++++++++++++++++++++++++++++\n drivers/gpio/gpio-vf610.c | 2 +-\n drivers/gpio/gpio-wcove.c | 2 +-\n drivers/gpio/gpio-ws16c48.c | 2 +-\n drivers/gpio/gpio-xgene-sb.c | 2 +-\n drivers/gpio/gpio-xlp.c | 2 +-\n drivers/gpio/gpio-zx.c | 2 +-\n drivers/gpio/gpio-zynq.c | 2 +-\n drivers/gpio/gpiolib-of.c | 101 +++++\n drivers/gpio/gpiolib.c | 320 ++++++++++++++--\n drivers/pinctrl/bcm/pinctrl-bcm2835.c | 5 +-\n drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 2 +-\n drivers/pinctrl/intel/pinctrl-baytrail.c | 6 +-\n drivers/pinctrl/intel/pinctrl-cherryview.c | 6 +-\n drivers/pinctrl/intel/pinctrl-intel.c | 2 +-\n drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 4 +-\n drivers/pinctrl/nomadik/pinctrl-nomadik.c | 4 +-\n drivers/pinctrl/pinctrl-amd.c | 2 +-\n drivers/pinctrl/pinctrl-at91.c | 2 +-\n drivers/pinctrl/pinctrl-coh901.c | 2 +-\n drivers/pinctrl/pinctrl-mcp23s08.c | 2 +-\n drivers/pinctrl/pinctrl-oxnas.c | 2 +-\n drivers/pinctrl/pinctrl-pic32.c | 2 +-\n drivers/pinctrl/pinctrl-pistachio.c | 2 +-\n drivers/pinctrl/pinctrl-st.c | 2 +-\n drivers/pinctrl/pinctrl-sx150x.c | 2 +-\n drivers/pinctrl/qcom/pinctrl-msm.c | 2 +-\n drivers/pinctrl/sirf/pinctrl-atlas7.c | 2 +-\n drivers/pinctrl/sirf/pinctrl-sirf.c | 2 +-\n drivers/pinctrl/spear/pinctrl-plgpio.c | 2 +-\n drivers/platform/x86/intel_int0002_vgpio.c | 6 +-\n include/linux/gpio/driver.h | 272 +++++++++++--\n include/linux/of_gpio.h | 10 +\n 63 files changed, 1505 insertions(+), 348 deletions(-)\n create mode 100644 drivers/gpio/gpio-tegra186.c" }