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{ "id": 818100, "url": "http://patchwork.ozlabs.org/api/covers/818100/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/cover/1506328815-23733-1-git-send-email-tien.fong.chee@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>", "list_archive_url": null, "date": "2017-09-25T08:39:56", "name": "[U-Boot,v2,00/19] Add FPGA, SDRAM, SPL loads U-boot & booting to console", "submitter": { "id": 70549, "url": "http://patchwork.ozlabs.org/api/people/70549/?format=api", "name": "Chee, Tien Fong", "email": "tien.fong.chee@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/cover/1506328815-23733-1-git-send-email-tien.fong.chee@intel.com/mbox/", "series": [ { "id": 4901, "url": "http://patchwork.ozlabs.org/api/series/4901/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4901", "date": "2017-09-25T08:39:56", "name": "Add FPGA, SDRAM, SPL loads U-boot & booting to console", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/4901/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/818100/comments/", "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0yGF2HgKz9tX3\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 25 Sep 2017 18:40:36 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 74AD5C21DA1; Mon, 25 Sep 2017 08:40:30 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 7659AC21C26;\n\tMon, 25 Sep 2017 08:40:26 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 12434C21D6A; Mon, 25 Sep 2017 08:40:25 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 1B3A0C21C26\n\tfor <u-boot@lists.denx.de>; Mon, 25 Sep 2017 08:40:21 +0000 (UTC)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Sep 2017 01:40:20 -0700", "from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.95])\n\tby fmsmga005.fm.intel.com with ESMTP; 25 Sep 2017 01:40:18 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.42,435,1500966000\"; d=\"scan'208\";a=\"155080056\"", "From": "tien.fong.chee@intel.com", "To": "u-boot@lists.denx.de", "Date": "Mon, 25 Sep 2017 16:39:56 +0800", "Message-Id": "<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>", "X-Mailer": "git-send-email 2.7.4", "Cc": "Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, \n\tChing Liang See <chin.liang.see@intel.com>,\n\tTien Fong <skywindctf@gmail.com>, \n\tWestergteen Dalon <dalon.westergreen@intel.com>", "Subject": "[U-Boot] [PATCH v2 00/19] Add FPGA, SDRAM,\n\tSPL loads U-boot & booting to console", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Tien Fong Chee <tien.fong.chee@intel.com>\n\nThis patchset adding FPGA and SDRAM drivers, enable fpga loadfs to program FPGA\n, SPL loading U-boot and booting to U-boot console. This version mainly resolved\ncomments from Marek in [v1].\nThis series is working on top of u-boot.git - http://git.denx.de/u-boot.git .\n\n[v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg261831.html\n\nTien Fong Chee (19):\n ARM: socfpga: add bindings doc for arria10 fpga manager\n doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA\n manager\n dts: Add FPGA bitstream properties to Arria 10 DTS\n arm: socfpga: Add Arria 10 SoCFPGA programming interface\n arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes\n dts: Enable fpga-mgr node build for Arria 10 SPL\n fdt: Add compatible strings for Arria 10\n fs: Enable generic filesystems interface support in SPL.\n arm: socfpga: Add drivers for programing FPGA from flash\n arm: socfpga: Rename the gen5 sdram driver to more specific name\n arm: socfpga: Add DRAM bank size initialization function\n arm: socfpga: Add DDR driver for Arria 10\n configs: Add DDR Kconfig support for Arria 10\n arm: socfpga: Enable build for DDR Arria 10\n arm: socfpga: Add support to memory allocation in SPL\n arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10\n arm: socfpga: Adding clock frequency info for U-boot\n arm: socfpga: Adding SoCFPGA info for both SPL and U-boot\n arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot\n\n arch/arm/dts/socfpga_arria10.dtsi | 4 +\n arch/arm/mach-socfpga/Kconfig | 1 +\n arch/arm/mach-socfpga/board.c | 16 +\n arch/arm/mach-socfpga/include/mach/boot0.h | 11 +-\n .../include/mach/fpga_manager_arria10.h | 27 +\n arch/arm/mach-socfpga/include/mach/sdram.h | 436 +-----------\n arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-\n .../include/mach/{sdram.h => sdram_gen5.h} | 6 +-\n arch/arm/mach-socfpga/misc_arria10.c | 5 -\n arch/arm/mach-socfpga/spl.c | 61 ++\n cmd/fpga.c | 2 +-\n common/spl/Kconfig | 8 +\n common/spl/spl_mmc.c | 2 +-\n configs/socfpga_arria10_defconfig | 57 +-\n doc/README.SPL | 1 +\n .../fpga/altera-socfpga-a10-fpga-mgr.txt | 30 +\n drivers/ddr/altera/Kconfig | 2 +-\n drivers/ddr/altera/Makefile | 3 +-\n drivers/ddr/altera/sdram_arria10.c | 735 +++++++++++++++++++++\n drivers/ddr/altera/{sdram.c => sdram_gen5.c} | 0\n drivers/fpga/altera.c | 39 +-\n drivers/fpga/fpga.c | 8 +\n drivers/fpga/socfpga.c | 14 +-\n drivers/fpga/socfpga_arria10.c | 391 ++++++++++-\n fs/Makefile | 1 +\n include/altera.h | 6 +\n include/configs/socfpga_common.h | 28 +-\n include/fdtdec.h | 2 +\n include/fpga.h | 2 +\n include/spl.h | 2 +\n lib/fdtdec.c | 2 +\n 31 files changed, 1535 insertions(+), 470 deletions(-)\n copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)\n create mode 100644 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n create mode 100644 drivers/ddr/altera/sdram_arria10.c\n rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)" }