Cover Letter Detail
Show a cover letter.
GET /api/covers/816112/?format=api
{ "id": 816112, "url": "http://patchwork.ozlabs.org/api/covers/816112/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/cover.1505890481.git.sean.wang@mediatek.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<cover.1505890481.git.sean.wang@mediatek.com>", "list_archive_url": null, "date": "2017-09-20T09:49:24", "name": "[0/4] add support of clock driver on MediaTek MT7622", "submitter": { "id": 69660, "url": "http://patchwork.ozlabs.org/api/people/69660/?format=api", "name": "Sean Wang", "email": "sean.wang@mediatek.com" }, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/cover.1505890481.git.sean.wang@mediatek.com/mbox/", "series": [ { "id": 4067, "url": "http://patchwork.ozlabs.org/api/series/4067/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4067", "date": "2017-09-20T09:49:24", "name": "add support of clock driver on MediaTek MT7622", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4067/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/816112/comments/", "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxw2B0YP4z9sPs\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tWed, 20 Sep 2017 19:49:38 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751609AbdITJtg (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tWed, 20 Sep 2017 05:49:36 -0400", "from mailgw01.mediatek.com ([210.61.82.183]:53625 \"EHLO\n\tmailgw01.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1751549AbdITJtf (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Wed, 20 Sep 2017 05:49:35 -0400", "from mtkexhb01.mediatek.inc [(172.21.101.102)] by\n\tmailgw01.mediatek.com (envelope-from <sean.wang@mediatek.com>)\n\t(mhqrelay.mediatek.com ESMTP with TLS)\n\twith ESMTP id 1591613516; Wed, 20 Sep 2017 17:49:28 +0800", "from mtkcas09.mediatek.inc (172.21.101.178) by\n\tmtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Wed, 20 Sep 2017 17:49:13 +0800", "from mtkswgap22.mediatek.inc (172.21.77.33) by\n\tmtkcas09.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Wed, 20 Sep 2017 17:49:46 +0800" ], "X-UUID": "f323327e812045e382b9d482b5ca24f5-20170920", "From": "<sean.wang@mediatek.com>", "To": "<sboyd@codeaurora.org>, <mturquette@baylibre.com>,\n\t<robh+dt@kernel.org>, <matthias.bgg@gmail.com>,\n\t<mark.rutland@arm.com>, <p.zabel@pengutronix.de>", "CC": "<devicetree@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,\n\t<linux-clk@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, \n\t<linux-kernel@vger.kernel.org>, Sean Wang <sean.wang@mediatek.com>", "Subject": "[PATCH 0/4] add support of clock driver on MediaTek MT7622", "Date": "Wed, 20 Sep 2017 17:49:24 +0800", "Message-ID": "<cover.1505890481.git.sean.wang@mediatek.com>", "X-Mailer": "git-send-email 1.7.9.5", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MTK": "N", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "From: Sean Wang <sean.wang@mediatek.com>\n\nAdd clock driver required by each function driver on MT7622 SoC with\nadding all clocks exported from every hardware subsystem such as topckgen,\napmixedsys, infracfg, pericfg , pciessys, ssusbsys, ethsys and audsys.\n\nChen Zhong (2):\n clk: mediatek: add the option for determining PLL source clock\n clk: mediatek: add clocks dt-bindings required header for MT7622 SoC\n\nSean Wang (2):\n dt-bindings: clock: mediatek: document clk bindings for MediaTek\n MT7622 SoC\n clk: mediatek: add clock support for MT7622 SoC\n\n .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +\n .../bindings/arm/mediatek/mediatek,audsys.txt | 22 +\n .../bindings/arm/mediatek/mediatek,ethsys.txt | 1 +\n .../bindings/arm/mediatek/mediatek,hifsys.txt | 1 +\n .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 +\n .../bindings/arm/mediatek/mediatek,pciesys.txt | 22 +\n .../bindings/arm/mediatek/mediatek,pericfg.txt | 1 +\n .../bindings/arm/mediatek/mediatek,sgmiisys.txt | 22 +\n .../bindings/arm/mediatek/mediatek,ssusbsys.txt | 22 +\n .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 +\n drivers/clk/mediatek/Kconfig | 30 +\n drivers/clk/mediatek/Makefile | 4 +\n drivers/clk/mediatek/clk-mt7622-aud.c | 195 ++++++\n drivers/clk/mediatek/clk-mt7622-eth.c | 156 +++++\n drivers/clk/mediatek/clk-mt7622-hif.c | 169 +++++\n drivers/clk/mediatek/clk-mt7622.c | 780 +++++++++++++++++++++\n drivers/clk/mediatek/clk-mtk.h | 1 +\n drivers/clk/mediatek/clk-pll.c | 5 +-\n include/dt-bindings/clock/mt7622-clk.h | 289 ++++++++\n 19 files changed, 1722 insertions(+), 1 deletion(-)\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt\n create mode 100644 drivers/clk/mediatek/clk-mt7622-aud.c\n create mode 100644 drivers/clk/mediatek/clk-mt7622-eth.c\n create mode 100644 drivers/clk/mediatek/clk-mt7622-hif.c\n create mode 100644 drivers/clk/mediatek/clk-mt7622.c\n create mode 100644 include/dt-bindings/clock/mt7622-clk.h" }