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{ "id": 815439, "url": "http://patchwork.ozlabs.org/api/covers/815439/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/20170919105605.18533-1-vigneshr@ti.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170919105605.18533-1-vigneshr@ti.com>", "list_archive_url": null, "date": "2017-09-19T10:56:00", "name": "[RESEND,v2,0/5] K2G: Add QSPI support", "submitter": { "id": 65039, "url": "http://patchwork.ozlabs.org/api/people/65039/?format=api", "name": "Raghavendra, Vignesh", "email": "vigneshr@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/20170919105605.18533-1-vigneshr@ti.com/mbox/", "series": [ { "id": 3840, "url": "http://patchwork.ozlabs.org/api/series/3840/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=3840", "date": "2017-09-19T10:56:01", "name": "K2G: Add QSPI support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/3840/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/815439/comments/", "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"LwCEBGaK\"; \n\tdkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxKc42ZQYz9s7m\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 20:58:28 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751815AbdISK6N (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 19 Sep 2017 06:58:13 -0400", "from fllnx209.ext.ti.com ([198.47.19.16]:27717 \"EHLO\n\tfllnx209.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751722AbdISK6L (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Tue, 19 Sep 2017 06:58:11 -0400", "from dflxv15.itg.ti.com ([128.247.5.124])\n\tby fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8JAuFsm002454; \n\tTue, 19 Sep 2017 05:56:15 -0500", "from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8JAuAjH008763;\n\tTue, 19 Sep 2017 05:56:10 -0500", "from DFLE108.ent.ti.com (10.64.6.29) by DFLE112.ent.ti.com\n\t(10.64.6.33) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tTue, 19 Sep 2017 05:56:10 -0500", "from dlep32.itg.ti.com (157.170.170.100) by DFLE108.ent.ti.com\n\t(10.64.6.29) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Tue, 19 Sep 2017 05:56:10 -0500", "from a0132425.india.ti.com (ileax41-snat.itg.ti.com\n\t[10.172.224.153])\n\tby dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8JAu6Rc022115;\n\tTue, 19 Sep 2017 05:56:07 -0500" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1505818575;\n\tbh=JCEDfu3UuNVqBKsXxCgYdwpoPTMR/d6wHDVKo0aMZIw=;\n\th=From:To:CC:Subject:Date;\n\tb=LwCEBGaKqpujzQDhmzZvdaBrZI8GqhJzXlj4r2tI0O4vDlhOf21r3FFHEIAQ9SotJ\n\tEmsD8zObKtSMNbkYRw2OpaaZcEPpGq8/o09C69RGRcRNyOQWeSASkSPlbx+DlmuaPK\n\tNnRMBdiL3Oo/AB/h0WoyKFDefWXxgw5cGu3iCr5I=", "From": "Vignesh R <vigneshr@ti.com>", "To": "Marek Vasut <marek.vasut@gmail.com>,\n\tCyrille Pitchen <cyrille.pitchen@wedev4u.fr>", "CC": "David Woodhouse <dwmw2@infradead.org>,\n\tBrian Norris <computersforpeace@gmail.com>,\n\tBoris Brezillon <boris.brezillon@free-electrons.com>,\n\tRob Herring <robh+dt@kernel.org>,\n\t<linux-mtd@lists.infradead.org>, <devicetree@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Vignesh R <vigneshr@ti.com>,\n\tlinux-arm-kernel <linux-arm-kernel@lists.infradead.org>", "Subject": "[RESEND PATCH v2 0/5] K2G: Add QSPI support", "Date": "Tue, 19 Sep 2017 16:26:00 +0530", "Message-ID": "<20170919105605.18533-1-vigneshr@ti.com>", "X-Mailer": "git-send-email 2.14.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.\nThe patches enhance the existing cadence-quadspi driver to support\nloopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.\n\nChange log:\n\nResend:\n* Rebase to latest linux-next.\n* Collect Acked-bys\n\nv2:\n* Drop DT patches. Will be sent as separate series as requested by\n maintainer.\n* Split binding docs into separate patches.\n* Address comments by Rob Herring.\n\n\nVignesh R (5):\n mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible\n mtd: spi-nor: cadence-quadspi: add a delay in write sequence\n mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back\n circuit\n mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock\n circuit\n mtd: spi-nor: cadence-quadspi: Add runtime PM support\n\n .../devicetree/bindings/mtd/cadence-quadspi.txt | 7 +++-\n drivers/mtd/spi-nor/cadence-quadspi.c | 46 ++++++++++++++++++++--\n 2 files changed, 49 insertions(+), 4 deletions(-)" }