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{ "id": 815125, "url": "http://patchwork.ozlabs.org/api/covers/815125/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/1505762601-27143-1-git-send-email-sundeep.lkml@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505762601-27143-1-git-send-email-sundeep.lkml@gmail.com>", "list_archive_url": null, "date": "2017-09-18T19:23:16", "name": "[Qemu,devel,v10,0/5] Add support for Smartfusion2 SoC", "submitter": { "id": 64324, "url": "http://patchwork.ozlabs.org/api/people/64324/?format=api", "name": "sundeep subbaraya", "email": "sundeep.lkml@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/1505762601-27143-1-git-send-email-sundeep.lkml@gmail.com/mbox/", "series": [ { "id": 3717, "url": "http://patchwork.ozlabs.org/api/series/3717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3717", "date": "2017-09-18T19:23:16", "name": "Add support for Smartfusion2 SoC", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/3717/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/815125/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"JP76xzMr\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwwtG5lZFz9s7G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 05:24:22 +1000 (AEST)", "from localhost ([::1]:38496 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1du1eW-0004VB-BI\n\tfor incoming@patchwork.ozlabs.org; Mon, 18 Sep 2017 15:24:20 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:54594)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <sundeep.lkml@gmail.com>) id 1du1dr-0004Uc-1p\n\tfor qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:23:40 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <sundeep.lkml@gmail.com>) id 1du1dm-00023l-9G\n\tfor qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:23:39 -0400", "from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:37448)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <sundeep.lkml@gmail.com>)\n\tid 1du1dm-00023O-2w; Mon, 18 Sep 2017 15:23:34 -0400", "by mail-pg0-x243.google.com with SMTP id v5so728181pgn.4;\n\tMon, 18 Sep 2017 12:23:33 -0700 (PDT)", "from localhost.localdomain ([124.123.70.3])\n\tby smtp.gmail.com with ESMTPSA id\n\tw12sm169701pfk.83.2017.09.18.12.23.30\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tMon, 18 Sep 2017 12:23:32 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id;\n\tbh=nCTgyvYqB/u+xu6qca9t9ux5vSZFO7sI1NtvTW4OPc4=;\n\tb=JP76xzMrgW5l5emvRM2gY2Eh4OYJ+L+DNnW9tv21axt+0YIbsG+xrbMoNEnwZbgn37\n\tnelj05c0SOXmm+v+USih7X9OoDPCSFp6IKwTGZreDW/XifiUNGJMx4uf37QTpSejtcR9\n\tpBdgX3Kl4zejB9Lx3ag722yoYmBzTL4Kt5FQzvksQ53Vm9qUuOTVq+UmS+a+Kyqlnflv\n\tEnwPV9ALG8Cfvign24kCFLa+YVVBhYTx5dRZtRYCFTvOZ5GRJDiGehYuTTaO24UEkwY8\n\tTSnq3kFhns8vpwgTUu7QH6yS0lKi64xkfbPVpt6N3mzMlyGNFASQVOLuYMXof7dNgpBU\n\tOnTw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=nCTgyvYqB/u+xu6qca9t9ux5vSZFO7sI1NtvTW4OPc4=;\n\tb=qglnEYwNeMJf+Tu9nbH4Of/krHx051pGYWjapZXS8ueRr5SZqk/7dltweVpkBtzPgm\n\tGfUvmewddTTrk1vNbGb88c7RNVWHLdaninyD5HuRwP08CJ0NicVQBinLUkbHh+o0d3Bz\n\tCTptCcmHdzsQVswApkTibXfghzxux3IqyOp41s+919X16K1KYZrmyE2Jq2pThqXIHFtk\n\tyar7YBsbWavk0ZWc2bhZsGA5hsi0TstTCEr1jpOa/s601Ry1vLRSwWMUw0VwjlYArjqC\n\tG6cycFMW9EW73smrWNeqs1XlXpuDJGNgLvcQNt5gWshfdDV4KmFLu4Ia2KAuO4YbjIvU\n\tSNgA==", "X-Gm-Message-State": "AHPjjUghCd2i9hIX7UKq7f5hbFuTdmBnmdChuYnSeEdsyDrxBYUM0WGR\n\tB1/B7K1nOOdH3QVr", "X-Google-Smtp-Source": "AOwi7QBhNtnEgSiDOjvbMpvPSPgxSKOSoGR0oVVBb5weQYd9NIpuIhtCgsh1iFiIS/ZmRNGbEolZ0Q==", "X-Received": "by 10.84.253.151 with SMTP id a23mr16176748plm.144.1505762612828;\n\tMon, 18 Sep 2017 12:23:32 -0700 (PDT)", "From": "Subbaraya Sundeep <sundeep.lkml@gmail.com>", "To": "qemu-devel@nongnu.org,\n\tqemu-arm@nongnu.org", "Date": "Tue, 19 Sep 2017 00:53:16 +0530", "Message-Id": "<1505762601-27143-1-git-send-email-sundeep.lkml@gmail.com>", "X-Mailer": "git-send-email 2.5.0", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::243", "Subject": "[Qemu-devel] [Qemu devel v10 PATCH 0/5] Add support for\n\tSmartfusion2 SoC", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Subbaraya Sundeep <sundeep.lkml@gmail.com>,\n\tf4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Hi Qemu-devel,\n\nI am trying to add Smartfusion2 SoC.\nSoC is from Microsemi and System on Module(SOM)\nboard is from Emcraft systems. Smartfusion2 has hardened\nMicrocontroller(Cortex-M3)based Sub System and FPGA fabric.\nAt the moment only system timer, sysreg and SPI\ncontroller are modelled.\n\nTesting:\n./arm-softmmu/qemu-system-arm -M emcraft-sf2 -serial mon:stdio \\\n-kernel u-boot.bin -display none -drive file=spi.bin,if=mtd,format=raw\n\nBinaries u-boot.bin and spi.bin are at:\nhttps://github.com/Subbaraya-Sundeep/qemu-test-binaries.git\n\nU-boot is from Emcraft with modified\n - SPI driver not to use PDMA.\n - ugly hack to pass dtb to kernel in r1.\n@\nhttps://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git\n\nLinux is 4.5 linux with Smartfusion2 SoC dts and clocksource\ndriver added by myself @\nhttps://github.com/Subbaraya-Sundeep/linux.git\n\nv10:\n\tAdded msf2_sysreg_realize in msf2-sysreg.c\n\tmodified unimplemented devices names:\n\t\tpdma->dma and hpdma->hs-dma\n\tused uint8_t for apb divisors properties\n\tsimplified msf2_divbits() using ctz32()\n\nv9:\n\tused trace instead of DB_PRINT in msf2-sysreg.c\n\tused LOG_UNIMP for non guest errors in msf2-sysreg.c\n\tadded unimplemented devices in msf2-soc.c\n\tremoved .alias suffix in alias memory region name for eNVM\n\tremoved mc->ignore_memory_transaction_failures in msf2-som.c\n\nv8:\n\tmemory_region_init_ram to memory_region_init_rom in soc\n\t%s/emcraft_sf2_init/emcraft_sf2_s2s010_init/g in som\n\tAdded mc->ignore_memory_transaction_failures = true in som\n\t\tas per latest commit.\n\tCode simplifications as suggested by Alistair in sysreg and ssi.\n\nv7:\n\tRemoved vmstate_register_ram_global as per latest commit\n\tMoved header files to C which are local to C source files\n\tRemoved abort() from msf2-sysreg.c\n\tAdded VMStateDescription in mss-timer.c\n\nv6:\n Moved some defines from header files to source files\n Added properties m3clk, apb0div, apb0div1 properties\n to soc.\n Added properties apb0divisor, apb1divisor to sysreg\n Update system_clock_source in msf2-soc.c\n Changed machine name smartfusion2-som->emcraft-sf2\n\nv5\n As per Philippe comments:\n Added abort in Sysreg if guest tries to remap memory\n other than default mapping.\n Use of CONFIG_MSF2 in Makefile for soc.c\n Fixed incorrect logic in timer model.\n Renamed msf2-timer.c -> mss-timer.c\n msf2-spi.c -> mss-spi.c also type names\n Renamed function msf2_init->emcraft_sf2_init in msf2-som.c\n Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1\n properties to soc.\n Pass soc part-name,memory size and clock rate properties from som.\nv4:\n Fixed build failure by using PRIx macros.\nv3:\n Added SoC file and board file as per Alistair comments.\nv2:\n Added SPI controller so that u-boot loads kernel from spi flash.\nv1:\n Initial patch set with timer and sysreg\n\nThanks,\nSundeep\n\n\nSubbaraya Sundeep (5):\n msf2: Add Smartfusion2 System timer\n msf2: Microsemi Smartfusion2 System Register block\n msf2: Add Smartfusion2 SPI controller\n msf2: Add Smartfusion2 SoC\n msf2: Add Emcraft's Smartfusion2 SOM kit\n\n default-configs/arm-softmmu.mak | 1 +\n hw/arm/Makefile.objs | 1 +\n hw/arm/msf2-soc.c | 232 +++++++++++++++++++++++\n hw/arm/msf2-som.c | 94 ++++++++++\n hw/misc/Makefile.objs | 1 +\n hw/misc/msf2-sysreg.c | 160 ++++++++++++++++\n hw/misc/trace-events | 5 +\n hw/ssi/Makefile.objs | 1 +\n hw/ssi/mss-spi.c | 404 ++++++++++++++++++++++++++++++++++++++++\n hw/timer/Makefile.objs | 1 +\n hw/timer/mss-timer.c | 289 ++++++++++++++++++++++++++++\n include/hw/arm/msf2-soc.h | 66 +++++++\n include/hw/misc/msf2-sysreg.h | 77 ++++++++\n include/hw/ssi/mss-spi.h | 58 ++++++\n include/hw/timer/mss-timer.h | 64 +++++++\n 15 files changed, 1454 insertions(+)\n create mode 100644 hw/arm/msf2-soc.c\n create mode 100644 hw/arm/msf2-som.c\n create mode 100644 hw/misc/msf2-sysreg.c\n create mode 100644 hw/ssi/mss-spi.c\n create mode 100644 hw/timer/mss-timer.c\n create mode 100644 include/hw/arm/msf2-soc.h\n create mode 100644 include/hw/misc/msf2-sysreg.h\n create mode 100644 include/hw/ssi/mss-spi.h\n create mode 100644 include/hw/timer/mss-timer.h" }