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    "msgid": "<20170914184701.20338-1-jeremy.linton@arm.com>",
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    "date": "2017-09-14T18:46:48",
    "name": "[0/6] Support PPTT for ARM64",
    "submitter": {
        "id": 67035,
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        "name": "Jeremy Linton",
        "email": "jeremy.linton@arm.com"
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            "date": "2017-09-14T18:46:48",
            "name": "Support PPTT for ARM64",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/3147/mbox/"
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        "From": "Jeremy Linton <jeremy.linton@arm.com>",
        "To": "linux-acpi@vger.kernel.org",
        "Subject": "[PATCH 0/6] Support PPTT for ARM64",
        "Date": "Thu, 14 Sep 2017 13:46:48 -0500",
        "Message-Id": "<20170914184701.20338-1-jeremy.linton@arm.com>",
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        "Cc": "austinwc@codeaurora.org, jhugo@codeaurora.org, john.garry@huawei.com,\n\tJeremy Linton <jeremy.linton@arm.com>, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, wangxiongfeng2@huawei.com,\n\tlinux-arm-kernel@lists.infradead.org",
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    "content": "ACPI 6.2 adds the Processor Properties Topology Table (PPTT), which is\nused to describe the processor and cache topologies. Ideally it is\nused to extend/override information provided by the hardware, but\nright now ARM64 is entirely dependent on firmware provided tables.\n\nThis patch parses the table for the cache topology and CPU topology.\nFor the latter we also add an additional topology_cod_id() macro,\nand a package_id for arm64. Initially the physical id will match\nthe cluster id, but we update users of the cluster to utilize\nthe new macro. When we enable PPTT for the arm64 the cluster/socket\nstarts to differ. Because of this we also make some dynamic decisions\nabout mapping thread/core/cod/socket to the thread/socket used by the\nscheduler.\n\nFor example on juno:\n\n[root@mammon-juno-rh topology]# lstopo-no-graphics\nMachine (7048MB)\n  Package L#0\n    L2 L#0 (1024KB) + Core L#0\n      L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)\n      L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)\n      L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2)\n      L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3)\n    L2 L#1 (2048KB) + Core L#1\n      L1d L#4 (32KB) + L1i L#4 (48KB) + PU L#4 (P#4)\n      L1d L#5 (32KB) + L1i L#5 (48KB) + PU L#5 (P#5)\n  HostBridge L#0\n    PCIBridge\n      PCIBridge\n        PCIBridge\n          PCI 1095:3132\n            Block(Disk) L#0 \"sda\"\n        PCIBridge\n          PCI 1002:68f9\n            GPU L#1 \"renderD128\"\n            GPU L#2 \"card0\"\n            GPU L#3 \"controlD64\"\n        PCIBridge\n          PCI 11ab:4380\n            Net L#4 \"enp8s0\"\n\n\nJeremy Linton (6):\n  ACPI/PPTT: Add Processor Properties Topology Table parsing\n  ACPI: Enable PPTT support on ARM64\n  drivers: base: cacheinfo: arm64: Add support for ACPI based firmware\n    tables\n  Topology: Add cluster on die macros and arm64 decoding\n  arm64: Fixup users of topology_physical_package_id\n  arm64: topology: Enable ACPI/PPTT based CPU topology.\n\n arch/arm64/Kconfig                |   1 +\n arch/arm64/include/asm/topology.h |   4 +-\n arch/arm64/kernel/cacheinfo.c     |  23 +-\n arch/arm64/kernel/topology.c      |  76 +++++-\n drivers/acpi/Makefile             |   1 +\n drivers/acpi/arm64/Kconfig        |   3 +\n drivers/acpi/pptt.c               | 508 ++++++++++++++++++++++++++++++++++++++\n drivers/base/cacheinfo.c          |  17 +-\n drivers/clk/clk-mb86s7x.c         |   2 +-\n drivers/cpufreq/arm_big_little.c  |   2 +-\n drivers/firmware/psci_checker.c   |   2 +-\n include/linux/cacheinfo.h         |  10 +-\n include/linux/topology.h          |   5 +\n 13 files changed, 634 insertions(+), 20 deletions(-)\n create mode 100644 drivers/acpi/pptt.c"
}