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{ "id": 812988, "url": "http://patchwork.ozlabs.org/api/covers/812988/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/1505240046-11454-1-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:13:47", "name": "[00/19] ARMv8M: support security extn in the NVIC", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/1505240046-11454-1-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/812988/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCdP3Mn1z9s0g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:15:19 +1000 (AEST)", "from localhost ([::1]:37949 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drpiP-0004C2-HH\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:15:17 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43175)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drpgv-0003KK-5g\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:46 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drpgu-0006Lt-7L\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:45 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37276)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgr-0006IX-Pu; Tue, 12 Sep 2017 14:13:41 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgp-00012m-JJ; Tue, 12 Sep 2017 19:13:39 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:13:47 +0100", "Message-Id": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 00/19] ARMv8M: support security extn in the NVIC", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "This patchset is another lump of v8M support. It mostly\ncovers the NVIC, which has extensive changes to handle the\nfact that some exceptions are now banked. It sits on top of\nthe set of minor fixes that I sent out the other day.\n\n(I have a chunk of patches that follow on from this to add\nthe security extension support to exception entry and exit\ncode, thus using the API changes made for the acknowledge\nand complete functions in the last patch. They need a little\nbit more baking, though, and 19 patches is enough as it is.)\n\nTesting status: I'm pretty happy that these patches are the\nright shape, but they might have minor bugs in the details.\n(My uvisor test case won't currently run very far because\nit wants the SG instruction.)\nThey shouldn't break v7M code, though, and it seems better to\nme to move things into master and bugfix them later if necessary\nrather than hold onto an enormous stack of patches that's\nunreviewably large.\n\nthanks\n-- PMM\n\nPeter Maydell (19):\n target/arm: Implement MSR/MRS access to NS banked registers\n nvic: Add banked exception states\n nvic: Add cached vectpending_is_s_banked state\n nvic: Add cached vectpending_prio state\n nvic: Implement AIRCR changes for v8M\n nvic: Make ICSR.RETTOBASE handle banked exceptions\n nvic: Implement NVIC_ITNS<n> registers\n nvic: Handle banked exceptions in nvic_recompute_state()\n nvic: Make set_pending and clear_pending take a secure parameter\n nvic: Make SHPR registers banked\n nvic: Compare group priority for escalation to HF\n nvic: In escalation to HardFault, support HF not being priority -1\n nvic: Implement v8M changes to fixed priority exceptions\n nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear\n nvic: Handle v8M changes in nvic_exec_prio()\n target/arm: Handle banking in negative-execution-priority check in\n cpu_mmu_index()\n nvic: Make ICSR banked for v8M\n nvic: Make SHCSR banked for v8M\n nvic: Support banked exceptions in acknowledge and complete\n\n include/hw/intc/armv7m_nvic.h | 33 +-\n target/arm/cpu.h | 62 ++-\n hw/intc/armv7m_nvic.c | 909 +++++++++++++++++++++++++++++++++++-------\n target/arm/cpu.c | 7 +\n target/arm/helper.c | 142 ++++++-\n hw/intc/trace-events | 13 +-\n 6 files changed, 996 insertions(+), 170 deletions(-)" }