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{ "id": 809970, "url": "http://patchwork.ozlabs.org/api/covers/809970/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/1504595552-9209-1-git-send-email-hean.loong.ong@intel.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504595552-9209-1-git-send-email-hean.loong.ong@intel.com>", "list_archive_url": null, "date": "2017-09-05T07:12:29", "name": "[PATCHv7,0/3] Intel FPGA Video and Image Processing Suite", "submitter": { "id": 70399, "url": "http://patchwork.ozlabs.org/api/people/70399/?format=api", "name": "Hean-Loong, Ong", "email": "hean.loong.ong@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/1504595552-9209-1-git-send-email-hean.loong.ong@intel.com/mbox/", "series": [ { "id": 1498, "url": "http://patchwork.ozlabs.org/api/series/1498/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=1498", "date": "2017-09-05T07:12:30", "name": "Intel FPGA Video and Image Processing Suite", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1498/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/809970/comments/", "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmdPy5CNBz9sPk\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tTue, 5 Sep 2017 17:19:34 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752037AbdIEHMk (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 5 Sep 2017 03:12:40 -0400", "from mga04.intel.com ([192.55.52.120]:63357 \"EHLO mga04.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752024AbdIEHMh (ORCPT <rfc822;devicetree@vger.kernel.org>);\n\tTue, 5 Sep 2017 03:12:37 -0400", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t05 Sep 2017 00:12:37 -0700", "from helong-vb.png.intel.com ([10.226.242.102])\n\tby fmsmga002.fm.intel.com with ESMTP; 05 Sep 2017 00:12:34 -0700" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.41,479,1498546800\"; d=\"scan'208\";\n\ta=\"1214795473\"", "From": "\"Hean-Loong, Ong\" <hean.loong.ong@intel.com>", "To": "Rob Herring <robh+dt@kernel.org>, Dinh Nguyen <dinguyen@kernel.org>,\n\tDaniel Vetter <daniel.vetter@intel.com>,\n\tLaurent Pinchart <laurent.pinchart@ideasonboard.com>,\n\tRandy Dunlap <rdunlap@infradead.org>", "Cc": "devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdri-devel@lists.freedesktop.org, hean.loong.ong@intel.com", "Subject": "[PATCHv7 0/3] Intel FPGA Video and Image Processing Suite", "Date": "Tue, 5 Sep 2017 15:12:29 +0800", "Message-Id": "<1504595552-9209-1-git-send-email-hean.loong.ong@intel.com>", "X-Mailer": "git-send-email 2.7.4", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "From: Ong Hean Loong <hean.loong.ong@intel.com>\n\nThe FPGA FrameBuffer Soft IP could be seen as the GPU and\nthe DRM driver patch here is allocating memory for\ninformation to be streamed from the ARM/Linux to the display port.\nBasically the driver just wraps the information such as the pixels to\nbe drawn by the FPGA FrameBuffer 2.\n\nThe piece of hardware in discussion is the SoC FPGA where Linux runs\non the ARM chip and the FGPA is driven by its NIOS soft core with its\nown proprietary firmware.\n\nFor example the application from the ARM Linux would have to write\ninformation on the /dev/fb0 with the information stored in the SDRAM\nto be fetched by the FPGA framebuffer IP and displayed on the Display\nPort Monitor.\n\nOng Hean Loong (3):\n ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite\n ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite\n ARM:drm ivip Intel FPGA Video and Image Processing Suite\n\n .../devicetree/bindings/display/altr,vip-fb2.txt | 84 +++++----\n arch/arm/configs/socfpga_defconfig | 6 +\n drivers/gpu/drm/Kconfig | 2 +\n drivers/gpu/drm/Makefile | 1 +\n drivers/gpu/drm/ivip/Kconfig | 14 ++\n drivers/gpu/drm/ivip/Makefile | 9 +\n drivers/gpu/drm/ivip/intel_vip_conn.c | 96 ++++++++++\n drivers/gpu/drm/ivip/intel_vip_core.c | 162 +++++++++++++++++\n drivers/gpu/drm/ivip/intel_vip_drv.h | 52 ++++++\n drivers/gpu/drm/ivip/intel_vip_of.c | 194 +++++++++++++++++++++\n 10 files changed, 587 insertions(+), 33 deletions(-)\n create mode 100644 drivers/gpu/drm/ivip/Kconfig\n create mode 100644 drivers/gpu/drm/ivip/Makefile\n create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c\n create mode 100644 drivers/gpu/drm/ivip/intel_vip_core.c\n create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h\n create mode 100644 drivers/gpu/drm/ivip/intel_vip_of.c" }
