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{
    "id": 808774,
    "url": "http://patchwork.ozlabs.org/api/covers/808774/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/1504281966-6199-1-git-send-email-oleksandrs@mellanox.com/",
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        "name": "Devicetree Bindings",
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    "msgid": "<1504281966-6199-1-git-send-email-oleksandrs@mellanox.com>",
    "list_archive_url": null,
    "date": "2017-09-01T16:06:02",
    "name": "[v7,0/4] JTAG driver introduction",
    "submitter": {
        "id": 72099,
        "url": "http://patchwork.ozlabs.org/api/people/72099/?format=api",
        "name": "Oleksandr Shamray",
        "email": "oleksandrs@mellanox.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/1504281966-6199-1-git-send-email-oleksandrs@mellanox.com/mbox/",
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            "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=1059",
            "date": "2017-09-01T16:06:02",
            "name": "JTAG driver introduction",
            "version": 7,
            "mbox": "http://patchwork.ozlabs.org/series/1059/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/covers/808774/comments/",
    "headers": {
        "Return-Path": "<devicetree-owner@vger.kernel.org>",
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            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkPHq5Plpz9t3P\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tSat,  2 Sep 2017 02:06:31 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752062AbdIAQGa (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tFri, 1 Sep 2017 12:06:30 -0400",
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            "from Internal Mail-Server by MTLPINE1 (envelope-from\n\toleksandrs@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 1 Sep 2017 19:06:26 +0300",
            "from r-vnc16.mtr.labs.mlnx (r-vnc16.mtr.labs.mlnx [10.208.0.16])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v81G6P6O002351;\n\tFri, 1 Sep 2017 19:06:25 +0300"
        ],
        "From": "Oleksandr Shamray <oleksandrs@mellanox.com>",
        "To": "gregkh@linuxfoundation.org, arnd@arndb.de",
        "Cc": "linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, openbmc@lists.ozlabs.org,\n\tjoel@jms.id.au, jiri@resnulli.us, tklauser@distanz.ch,\n\tlinux-serial@vger.kernel.org, mec@shout.net, vadimp@maellanox.com,\n\tsystem-sw-low-level@mellanox.com, robh+dt@kernel.org,\n\topenocd-devel-owner@lists.sourceforge.net,\n\tlinux-api@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org,\n\tOleksandr Shamray <oleksandrs@mellanox.com>",
        "Subject": "[patch v7 0/4] JTAG driver introduction",
        "Date": "Fri,  1 Sep 2017 19:06:02 +0300",
        "Message-Id": "<1504281966-6199-1-git-send-email-oleksandrs@mellanox.com>",
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        "Sender": "devicetree-owner@vger.kernel.org",
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        "List-ID": "<devicetree.vger.kernel.org>",
        "X-Mailing-List": "devicetree@vger.kernel.org"
    },
    "content": "When a need raise up to use JTAG interface for system's devices\nprogramming or CPU debugging, usually the user layer\napplication implements jtag protocol by bit-bang or using a \nproprietary connection to vendor hardware.\nThis method can be slow and not generic.\n \nWe propose to implement general JTAG interface and infrastructure\nto communicate with user layer application. In such way, we can\nhave the standard JTAG interface core part and separation from\nspecific HW implementation.\nThis allow new capability to debug the CPU or program system's \ndevice via BMC without additional devices nor cost. \n\nThis patch purpose is to add JTAG master core infrastructure by \ndefining new JTAG class and provide generic JTAG interface\nto allow hardware specific drivers to connect this interface.\nThis will enable all JTAG drivers to use the common interface\npart and will have separate for hardware implementation.\n\nThe JTAG (Joint Test Action Group) core driver provides minimal generic\nJTAG interface, which can be used by hardware specific JTAG master\ncontrollers. By providing common interface for the JTAG controllers,\nuser space device programing is hardware independent.\n \nModern SoC which in use for embedded system' equipped with\ninternal JTAG master interface.\nThis interface is used for programming and debugging system's\nhardware components, like CPLD, FPGA, CPU, voltage and\nindustrial controllers.\nFirmware for such devices can be upgraded through JTAG interface during\nRuntime. The JTAG standard support for multiple devices programming,\nis in case their lines are daisy-chained together.\n\nFor example, systems which equipped with host CPU, BMC SoC or/and \nnumber of programmable devices are capable to connect a pin and\nselect system components dynamically for programming and debugging,\nThis is using by the BMC which is equipped with internal SoC master\ncontroller.\nFor example:\n\nBMC JTAG master --> pin selected to CPLDs chain for programming (filed\nupgrade, production) \nBMC JTAG master --> pin selected to voltage monitors for programming \n(field upgrade, production) \nBMC JTAG master --> pin selected to host CPU (on-site debugging \nand developers debugging)\n\nFor example, we can have application in user space which using calls\nto JTAG driver executes CPLD programming directly from SVF file\n \nThe JTAG standard (IEEE 1149.1) defines the next connector pins:\n- TDI (Test Data In);\n- TDO (Test Data Out);\n- TCK (Test Clock);\n- TMS (Test Mode Select);\n- TRST (Test Reset) (Optional);\n\nThe SoC equipped with JTAG master controller, performs\ndevice programming on command or vector level. For example\na file in a standard SVF (Serial Vector Format) that contains\nboundary scan vectors, can be used by sending each vector\nto the JTAG interface and the JTAG controller will execute\nthe programming.\n\nInitial version provides the system calls set for:\n- SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);\n- SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);\n- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified\n  number of clocks.\n\nSoC which are not equipped with JTAG master interface, can be built\non top of JTAG core driver infrastructure, by applying bit-banging of\nTDI, TDO, TCK and TMS pins within the hardware specific driver.\n\nOleksandr Shamray (4):\n  drivers: jtag: Add JTAG core driver\n  drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master\n    driver\n  Documentation: jtag: Add bindings for Aspeed SoC 24xx and 25xx\n    families     JTAG master driver\n  Documentation: jtag: Add ABI documentation\n\n Documentation/ABI/testing/jatg-cdev                |   27 +\n .../devicetree/bindings/jtag/aspeed-jtag.txt       |   18 +\n Documentation/ioctl/ioctl-number.txt               |    2 +\n MAINTAINERS                                        |   10 +\n drivers/Kconfig                                    |    2 +\n drivers/Makefile                                   |    1 +\n drivers/jtag/Kconfig                               |   29 +\n drivers/jtag/Makefile                              |    2 +\n drivers/jtag/jtag-aspeed.c                         |  773 ++++++++++++++++++++\n drivers/jtag/jtag.c                                |  312 ++++++++\n include/linux/jtag.h                               |   48 ++\n include/uapi/linux/jtag.h                          |  111 +++\n 12 files changed, 1335 insertions(+), 0 deletions(-)\n create mode 100644 Documentation/ABI/testing/jatg-cdev\n create mode 100644 Documentation/devicetree/bindings/jtag/aspeed-jtag.txt\n create mode 100644 drivers/jtag/Kconfig\n create mode 100644 drivers/jtag/Makefile\n create mode 100644 drivers/jtag/jtag-aspeed.c\n create mode 100644 drivers/jtag/jtag.c\n create mode 100644 include/linux/jtag.h\n create mode 100644 include/uapi/linux/jtag.h\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at  http://vger.kernel.org/majordomo-info.html"
}