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{
    "id": 807960,
    "url": "http://patchwork.ozlabs.org/api/covers/807960/?format=api",
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    "msgid": "<20170830225225.27925-1-f4bug@amsat.org>",
    "list_archive_url": null,
    "date": "2017-08-30T22:52:18",
    "name": "[v2,0/7] QOMify MIPS cpu",
    "submitter": {
        "id": 70924,
        "url": "http://patchwork.ozlabs.org/api/people/70924/?format=api",
        "name": "Philippe Mathieu-Daudé",
        "email": "f4bug@amsat.org"
    },
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20170830225225.27925-1-f4bug@amsat.org/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/covers/807960/comments/",
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        "X-Received": "by 10.200.37.110 with SMTP id 43mr4657720qtn.10.1504133556086;\n\tWed, 30 Aug 2017 15:52:36 -0700 (PDT)",
        "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>",
        "To": "Igor Mammedov <imammedo@redhat.com>,\n\tEduardo Habkost <ehabkost@redhat.com>, \n\tMarcel Apfelbaum <marcel@redhat.com>",
        "Date": "Wed, 30 Aug 2017 19:52:18 -0300",
        "Message-Id": "<20170830225225.27925-1-f4bug@amsat.org>",
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        "X-Received-From": "2607:f8b0:400d:c0d::22f",
        "Subject": "[Qemu-devel] [PATCH v2 0/7] QOMify MIPS cpu",
        "X-BeenThere": "qemu-devel@nongnu.org",
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        "Cc": "Peter Maydell <peter.maydell@linaro.org>, Thomas Huth <thuth@redhat.com>,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>,\n\tqemu-devel@nongnu.org",
        "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org",
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    },
    "content": "Hi,\n\nThis series is based on Igor's \"complete cpu QOMification\" [1] but only modify\nthe MIPS part. Igor posted an updated series [2], both series should apply\nseparately.\n\nIgor suggested on IRC this series could enter via the Machine core tree, so\nI added Eduardo and Marcel.\n\nRegards,\n\nPhil.\n\n[1]: http://lists.nongnu.org/archive/html/qemu-devel/2017-07/msg04414.html\n[2]: http://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg03364.html\n\nv2: \n- added Igor and James Tested-by\n- squashed \"!fixup mips: now than MIPSCPU is QOMified, mark it abstract\"\n\nPS: code movement somehow triggers a \"binary vs unary operators\" confusion\n    in checkpatch: \"ERROR: space prohibited after that '&' (ctx:WxW)\"\n\nIgor Mammedov (2):\n  mips: MIPSCPU model subclasses\n  mips: replace cpu_mips_init() with cpu_generic_init()\n\nPhilippe Mathieu-Daudé (5):\n  mips: move hw/mips/cputimer.c to target/mips/\n  mips: introduce internal.h and cleanup cpu.h\n  mips: split cpu_mips_realize_env() out of cpu_mips_init()\n  mips: call cpu_mips_realize_env() from mips_cpu_realizefn()\n  mips: update mips_cpu_list() to use object_class_get_list()\n\n target/mips/cpu-qom.h                         |   1 +\n target/mips/cpu.h                             | 357 +---------------------\n target/mips/internal.h                        | 422 ++++++++++++++++++++++++++\n hw/mips/cps.c                                 |   2 +-\n hw/mips/mips_fulong2e.c                       |   2 +-\n hw/mips/mips_jazz.c                           |   2 +-\n hw/mips/mips_malta.c                          |   2 +-\n hw/mips/mips_mipssim.c                        |   2 +-\n hw/mips/mips_r4k.c                            |   2 +-\n hw/mips/cputimer.c => target/mips/cp0_timer.c |   2 +-\n target/mips/cpu.c                             |  57 +++-\n target/mips/gdbstub.c                         |   1 +\n target/mips/helper.c                          |  47 +++\n target/mips/kvm.c                             |   1 +\n target/mips/machine.c                         |   1 +\n target/mips/msa_helper.c                      |   1 +\n target/mips/op_helper.c                       |   1 +\n target/mips/translate.c                       |  23 +-\n target/mips/translate_init.c                  |  68 +----\n hw/mips/Makefile.objs                         |   2 +-\n target/mips/Makefile.objs                     |   2 +-\n 21 files changed, 549 insertions(+), 449 deletions(-)\n create mode 100644 target/mips/internal.h\n rename hw/mips/cputimer.c => target/mips/cp0_timer.c (99%)"
}