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{ "id": 807392, "url": "http://patchwork.ozlabs.org/api/covers/807392/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/cover/1504066360-30128-1-git-send-email-paulus@ozlabs.org/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504066360-30128-1-git-send-email-paulus@ozlabs.org>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504066360-30128-1-git-send-email-paulus@ozlabs.org/", "date": "2017-08-30T04:12:23", "name": "[v3,00/17] powerpc: Do alignment fixups using analyse_instr etc.", "submitter": { "id": 67079, "url": "http://patchwork.ozlabs.org/api/people/67079/?format=api", "name": "Paul Mackerras", "email": "paulus@ozlabs.org" }, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/cover/1504066360-30128-1-git-send-email-paulus@ozlabs.org/mbox/", "series": [ { "id": 522, "url": "http://patchwork.ozlabs.org/api/series/522/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=522", "date": "2017-08-30T04:12:25", "name": "powerpc: Do alignment fixups using analyse_instr etc.", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/522/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/807392/comments/", "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhsgK1gHfz9sNc\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 14:18:05 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhsgK0TDzzDqHj\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 14:18:05 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhsYF3d8RzDqGG\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 30 Aug 2017 14:12:49 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xhsYF2g5Vz9sP5; Wed, 30 Aug 2017 14:12:49 +1000 (AEST)", "from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3xhsYF1J2hz9sNc\n\tfor <linuxppc-dev@ozlabs.org>; Wed, 30 Aug 2017 14:12:49 +1000 (AEST)" ], "Authentication-Results": [ "ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"RgHcvhNA\";\n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"RgHcvhNA\";\n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"RgHcvhNA\"; \n\tdkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1504066369; bh=18QEJTWm6nvrkiyYnXtqRTE3anIW6hsGKTsyIuirMTg=;\n\th=From:To:Subject:Date:From;\n\tb=RgHcvhNAMS3cC5S4iCMo4YEUy6aIB+J7OJHZ5X0TeFw4V0pz3BIMs07SSb+F9fVF/\n\ts8Rva4miF+gGVUFdq6is5wpxC9FxAYpQRCLTaQ5FizqR8QjDeh4OCet/MsR0G+1ebq\n\tJkw0pDN4mf2yviim/dLFMgeGRf0GOTrqZ/Vpg9HkQzvVFzLWQWRlsLBNj8+SpvsYJm\n\tRO8vuvekNeFEU9wuVT1NJJ6YXK2E69H2t9cEl5jMuEsYlfVehfFIuJyTtqai9tO55t\n\tOad1LaW/ajn5k0VQmjvxhwlMXI0WgvRnkNlQvqbNMwRFs2vF6ZWzVcnzVaDOk9LEYO\n\tPOssBgCIqnAYQ==", "From": "Paul Mackerras <paulus@ozlabs.org>", "To": "linuxppc-dev@ozlabs.org", "Subject": "[PATCH v3 00/17] powerpc: Do alignment fixups using analyse_instr\n\tetc.", "Date": "Wed, 30 Aug 2017 14:12:23 +1000", "Message-Id": "<1504066360-30128-1-git-send-email-paulus@ozlabs.org>", "X-Mailer": "git-send-email 2.7.4", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "This series extends the instruction emulation infrastructure in\narch/powerpc/lib/sstep.c and uses it for emulating instructions when\nwe get an alignment interrupt. The advantage of this is that we only\nhave to add the new POWER9 instructions in one place, and it fixes\nseveral bugs in alignment interrupt handling that have been identified\nrecently.\n\nWith this, analyse_instr() and emulate_step() handle almost all load\nand store instructions in Power ISA v3.00 -- all except the atomic\nmemory operations (lwat, stwat, etc.). We now always use the largest\npossible aligned memory accesses (up to 8 bytes) to emulate unaligned\naccesses. If we get a fault, the faulting address is accurately\nrecorded in regs->dar. We also can now access FP/VMX/VSX registers\ndirectly if they are live, without having to spill them all to the\nthread_struct and the reload them all later. There are also various\nother fixes in the series.\n\nThis version is based on the current powerpc next branch.\n\nPaul.\n\n arch/powerpc/Kconfig | 4 -\n arch/powerpc/include/asm/ppc-opcode.h | 10 +-\n arch/powerpc/include/asm/sstep.h | 90 +-\n arch/powerpc/kernel/align.c | 774 +-----------\n arch/powerpc/lib/Makefile | 3 +-\n arch/powerpc/lib/ldstfp.S | 307 ++---\n arch/powerpc/lib/quad.S | 62 +\n arch/powerpc/lib/sstep.c | 2139 +++++++++++++++++++++++----------\n 8 files changed, 1802 insertions(+), 1587 deletions(-)" }