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{ "id": 807032, "url": "http://patchwork.ozlabs.org/api/covers/807032/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/cover/1504003561-6290-1-git-send-email-tien.fong.chee@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "list_archive_url": null, "date": "2017-08-29T10:45:42", "name": "[U-Boot,00/19] Add FPGA, SDRAM drivers and booting to U-boot", "submitter": { "id": 70549, "url": "http://patchwork.ozlabs.org/api/people/70549/?format=api", "name": "Chee, Tien Fong", "email": "tien.fong.chee@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/cover/1504003561-6290-1-git-send-email-tien.fong.chee@intel.com/mbox/", "series": [ { "id": 345, "url": "http://patchwork.ozlabs.org/api/series/345/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=345", "date": "2017-08-29T10:45:42", "name": "Add FPGA, SDRAM drivers and booting to U-boot", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/345/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/807032/comments/", "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhQMX3W32z9t6l\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 20:47:02 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 0E382C21F2D; Tue, 29 Aug 2017 10:46:16 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4DDF7C21D95;\n\tTue, 29 Aug 2017 10:46:13 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 30521C21EF7; Tue, 29 Aug 2017 10:46:09 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id E5B30C21DAD\n\tfor <u-boot@lists.denx.de>; Tue, 29 Aug 2017 10:46:07 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Aug 2017 03:46:06 -0700", "from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.65])\n\tby orsmga005.jf.intel.com with ESMTP; 29 Aug 2017 03:46:03 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.41,444,1498546800\"; d=\"scan'208\";a=\"143176539\"", "From": "tien.fong.chee@intel.com", "To": "u-boot@lists.denx.de", "Date": "Tue, 29 Aug 2017 18:45:42 +0800", "Message-Id": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "X-Mailer": "git-send-email 2.7.4", "Cc": "Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, \n\tChing Liang See <chin.liang.see@intel.com>,\n\tTien Fong <skywindctf@gmail.com>, \n\tWestergteen Dalon <dalon.westergreen@intel.com>", "Subject": "[U-Boot] [PATCH 00/19] Add FPGA, SDRAM drivers and booting to U-boot", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Tien Fong Chee <tien.fong.chee@intel.com>\n\nThis patchset adding FPGA and SDRAM drivers, enable fpga loadfs and booting\nto U-boot console.\n\nThis series is working on top of u-boot.git - http://git.denx.de/u-boot.git\n\nTien Fong Chee (19):\n configs: Add FPGA loadfs config for Arria 10\n configs: Add FAT fs support for SPL\n arm: socfpga: Add driver for flash to program FPGA\n arm: socfpga: Add FPGA loadfs command support\n arm: socfpga: Enhance FPGA program support with at least 4 byte data\n arm: socfpga: Rename the gen5 sdram driver to more specific name\n arm: socfpga: Add DRAM bank size initialization function\n arm: socfpga: Add COMPAT macro for Network on Chip(NoC)\n arm: socfpga: Add DDR driver for Arria 10\n configs: Add DDR Kconfig support for Arria 10\n arm: socfpga: Enable build for DDR Arria 10\n doc: dtbinding: Add Intel Arria 10 SoCFPGA chosen binding\n dts: Add the FPGA design file name to DTS\n dts: Add device storage and partition to DTS\n arm: socfpga: Add support to memory allocation in SPL\n arm: socfpga: Enhance Intel SoCFPGA program header to support Arria\n 10\n arm: socfpga: Adding clock frequency info for U-boot\n arm: socfpga: Adding SoCFPGA info for both SPL and U-boot\n arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot\n\n .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 5 +-\n arch/arm/mach-socfpga/Kconfig | 1 +\n arch/arm/mach-socfpga/board.c | 21 +\n arch/arm/mach-socfpga/include/mach/boot0.h | 9 +-\n .../include/mach/fpga_manager_arria10.h | 27 +\n arch/arm/mach-socfpga/include/mach/sdram.h | 438 +------------\n arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 +++-\n .../include/mach/{sdram.h => sdram_gen5.h} | 6 +-\n arch/arm/mach-socfpga/misc_arria10.c | 5 -\n arch/arm/mach-socfpga/spl.c | 93 +++\n cmd/fpga.c | 2 +-\n common/spl/spl_mmc.c | 2 +-\n configs/socfpga_arria10_defconfig | 49 ++-\n disk/part.c | 2 +\n doc/device-tree-bindings/chosen.txt | 45 ++\n drivers/ddr/altera/Kconfig | 2 +-\n drivers/ddr/altera/Makefile | 3 +-\n drivers/ddr/altera/sdram_arria10.c | 735 ++++++++++++++++++++\n drivers/ddr/altera/{sdram.c => sdram_gen5.c} | 0\n drivers/fpga/altera.c | 38 +-\n drivers/fpga/fpga.c | 8 +\n drivers/fpga/socfpga.c | 14 +-\n drivers/fpga/socfpga_arria10.c | 386 ++++++++++-\n include/altera.h | 6 +\n include/configs/socfpga_common.h | 28 +-\n include/fdtdec.h | 1 +\n include/fpga.h | 2 +\n include/spl.h | 2 +\n lib/fdtdec.c | 1 +\n 29 files changed, 1569 insertions(+), 465 deletions(-)\n copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)\n create mode 100644 drivers/ddr/altera/sdram_arria10.c\n rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)" }