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{ "id": 806952, "url": "http://patchwork.ozlabs.org/api/covers/806952/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/cover/1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com/", "date": "2017-08-29T06:23:30", "name": "[v8,00/10] Enable VAS", "submitter": { "id": 984, "url": "http://patchwork.ozlabs.org/api/people/984/?format=api", "name": "Sukadev Bhattiprolu", "email": "sukadev@linux.vnet.ibm.com" }, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/cover/1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com/mbox/", "series": [ { "id": 310, "url": "http://patchwork.ozlabs.org/api/series/310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=310", "date": "2017-08-29T06:23:30", "name": "Enable VAS", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/310/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/806952/comments/", "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJY55l0cz9sP5\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 29 Aug 2017 16:25:45 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhJY54jTbzDqZB\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 29 Aug 2017 16:25:45 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhJW063D3zDqR9\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 29 Aug 2017 16:23:56 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xhJW04YdBz8vLq\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 29 Aug 2017 16:23:56 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xhJW03V6mz9t3R; Tue, 29 Aug 2017 16:23:56 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJVz6hMBz9t3P\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 16:23:55 +1000 (AEST)", "from pps.filterd (m0098417.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7T6KD1d119832\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 02:23:53 -0400", "from e14.ny.us.ibm.com (e14.ny.us.ibm.com [129.33.205.204])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cn0dtak2j-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 02:23:53 -0400", "from localhost\n\tby e14.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tTue, 29 Aug 2017 02:23:48 -0400", "from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com\n\t[9.57.199.110])\n\tby b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid v7T6NlQj23396448; Tue, 29 Aug 2017 06:23:47 GMT", "from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 94D54AE043;\n\tTue, 29 Aug 2017 02:24:11 -0400 (EDT)", "from suka-w540.usor.ibm.com (unknown [9.70.94.25])\n\tby b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id BA5F1AE034;\n\tTue, 29 Aug 2017 02:24:10 -0400 (EDT)" ], "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=sukadev@linux.vnet.ibm.com; receiver=<UNKNOWN>)", "From": "Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>", "To": "Michael Ellerman <mpe@ellerman.id.au>", "Subject": "[PATCH v8 00/10] Enable VAS", "Date": "Mon, 28 Aug 2017 23:23:30 -0700", "X-Mailer": "git-send-email 2.7.4", "X-TM-AS-GCONF": "00", "x-cbid": "17082906-0052-0000-0000-000002575396", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007631; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00909146; UDB=6.00455922;\n\tIPR=6.00689402; \n\tBA=6.00005559; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016912;\n\tXFM=3.00000015; UTC=2017-08-29 06:23:50", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082906-0053-0000-0000-000051D27DDF", "Message-Id": "<1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-29_01:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708290094", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "stewart@linux.vnet.ibm.com, mikey@neuling.org, linuxppc-dev@ozlabs.org, \n\tlinux-kernel@vger.kernel.org, apopple@au1.ibm.com, oohall@gmail.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Power9 introduces a hardware subsystem referred to as the Virtual\nAccelerator Switchboard (VAS). VAS allows kernel subsystems and user\nspace processes to directly access the Nest Accelerator (NX) engines\nwhich implement compression and encryption algorithms in the hardware.\n\nNX has been in Power processors since Power7+, but access to the NX\nengines was through the 'icswx' instruction which is only available\nto the kernel/hypervisor. Starting with Power9, access to the NX\nengines is provided to both kernel and user space processes through\nVAS.\n\nThe switchboard (i.e VAS) multiplexes accesses between \"receivers\" and\n\"senders\", where the \"receivers\" are typically the NX engines and\n\"senders\" are the kernel subsystems and user processors that wish to\naccess the receivers (NX engines). Once a sender is \"connected\" to\na receiver through the switchboard, the senders can submit compression/\nencryption requests to the hardware using the new (PowerISA 3.0)\n\"copy\" and \"paste\" instructions.\n\nIn the initial OPAL and PowerNV kernel patchsets, the \"senders\" can\nonly be kernel subsystems (eg NX-842 driver) and receivers can only\nbe the NX-842 engine. Follow-on patch sets will allow senders/receivers\nto be user-space processes and receivers to be NX-GZIP engines.\n\nProvides:\n\n\tThis kernel patch set configures the VAS subsystems and provides\n\tkernel interfaces to drivers like NX-842 to open receive and send\n\twindows in VAS and to submit compression requests to the NX engine.\n\nRequires:\n\n\tThis patch set needs corresponding VAS/NX skiboot patches which\n\twere merged into skiboot tree. i.e skiboot must include:\n\tcommit b503dcf (\"vas: Set mmio enable bits in DD2\")\n\nTests:\n In-kernel compression requests were tested on DD1 and DD2 POWER9\n\thardware using compression self-test module and the following\n\tNX-842 patch set from Haren Myneni:\n\n https://lists.ozlabs.org/pipermail/linuxppc-dev/2017-July/160620.html\n\n\tand by dropping the last parameters to both vas_copy_crb() and\n\tvas_paste_crb() calls in drivers/crypto/nx/nx-842-powernv.c.\n\tSee also PATCH 10/10.\n\nGit Tree:\n\n https://github.com/sukadev/linux/ \n\tBranch: vas-kern-v8\n\nThanks to input from Ben Herrenschmidt, Michael Neuling, Michael Ellerman\nand Haren Myneni.\n\nChangelog[v8]:\n\t- [Michael Ellerman] Use kernel int types (u64, u32 etc); make VAS\n\t a built-in rather than a module; drop unnecessary fields from\n\t struct vas_instance; Update ISA references; use 0 or 1 with\n\t SET_FIELD macros instead of bool; skip writing to SPARE registers;\n\t minor cleanup of debug/error messages; retry if ida_get_new()\n\t fails with EAGAIN; fix couple of leaks in ids in error handling;\n\t drop vas_initialized() check; drop vas_win_id() and vas_paste_addr()\n\t interfaces as they are not yet used; Set task_state() and fix\n\t parameter to schedule_timeout(); Reuse existing copy/paste macros\n\t drop unnecessary parameters and add cr0 to clobbers list\n\nChangelog[v7]:\n\t- Drop support for user space send/receive FTW windows (will be\n\t posted separately) Simplifies the rx-win-open interface a bit.\n\t- [Michael Ellerman] Move GET_FIELD/SET_FIELD macros from \n\t uapi/asm/vas.h to asm/vas.h.\n\nChangelog[v6]\n\t- Add support for user space send/receive FTW windows\n\t- Add a new, NX-FTW driver which provides the FTW user interface\n\nChangelog[v5]\n\t- [Ben Herrenschmidt] Make VAS a platform device in the device tree\n\t and use the core platform functions to parse the VAS properties.\n\t Map the VAS MMIO regions as non-cachable and paste regions as\n\t cachable. Use CONFIG_PPC_VAS rather than CONFIG_VAS; Don't assume\n\t VAS ids are sequential.\n\t- Copy the FIFO address as is into LFIFO_BAR (don't shift it).\n\nChangelog[v4]\n\tComments from Michael Neuling:\n\t- Move VAS code from drivers/misc/vas to arch/powerpc/platforms/powernv\n\t since VAS only provides interfaces to other drivers like NX-842.\n\t- Drop vas-internal.h and use vas.h in separate dirs for VAS\n\t internal, kernel API and user API\n\t- Rather than create 6 separate device tree properties windows\n\t and window context, combine them into 6 \"reg\" properties.\n\t- Drop vas_window_reset() since windows are reset/cleared before\n\t being assigned to kernel/users.\n\t- Use ilog2() and radix_enabled() helpers\n\nChangelog[v3]\n\t- Rebase to v4.11-rc1\n\t- Add interfaces to initialize send/receive window attributes to\n\t defaults that drivers can use (see arch/powerpc/include/asm/vas.h)\n\t- Modify interface vas_paste() to return 0 or error code\n\t- Fix a bug in setting Translation Control Mode (0b11 not 0x11)\n\t- Enable send-window-credit checking \n\t- Reorg code in vas_win_close()\n\t- Minor reorgs and tweaks to register field settings to make it\n\t easier to add support for user space windows.\n\t- Skip writing to read-only registers\n\t- Start window indexing from 0 rather than 1\n\nChangelog[v2]\n\t- Use vas-id, HVWC, UWC and paste address, entries from device tree\n\t rather than defining/computing them in kernel and reorg code.\n\n\nSukadev Bhattiprolu (10):\n powerpc/vas: Define macros, register fields and structures\n Move GET_FIELD/SET_FIELD to vas.h\n powerpc/vas: Define vas_init() and vas_exit()\n powerpc/vas: Define helpers to access MMIO regions\n powerpc/vas: Define helpers to init window context\n powerpc/vas: Define helpers to alloc/free windows\n powerpc/vas: Define vas_rx_win_open() interface\n powerpc/vas: Define vas_win_close() interface\n powerpc/vas: Define vas_tx_win_open()\n powerpc/vas: Define copy/paste interfaces\n\n .../devicetree/bindings/powerpc/ibm,vas.txt | 23 +\n MAINTAINERS | 9 +\n arch/powerpc/include/asm/ppc-opcode.h | 2 +\n arch/powerpc/include/asm/vas.h | 160 +++\n arch/powerpc/platforms/powernv/Kconfig | 14 +\n arch/powerpc/platforms/powernv/Makefile | 1 +\n arch/powerpc/platforms/powernv/copy-paste.h | 46 +\n arch/powerpc/platforms/powernv/vas-window.c | 1134 ++++++++++++++++++++\n arch/powerpc/platforms/powernv/vas.c | 151 +++\n arch/powerpc/platforms/powernv/vas.h | 467 ++++++++\n drivers/crypto/nx/nx-842-powernv.c | 7 +-\n drivers/crypto/nx/nx-842.h | 5 -\n 12 files changed, 2011 insertions(+), 8 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/powerpc/ibm,vas.txt\n create mode 100644 arch/powerpc/include/asm/vas.h\n create mode 100644 arch/powerpc/platforms/powernv/copy-paste.h\n create mode 100644 arch/powerpc/platforms/powernv/vas-window.c\n create mode 100644 arch/powerpc/platforms/powernv/vas.c\n create mode 100644 arch/powerpc/platforms/powernv/vas.h" }