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{ "id": 806701, "url": "http://patchwork.ozlabs.org/api/covers/806701/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/20170828180437.2646-1-ard.biesheuvel@linaro.org/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170828180437.2646-1-ard.biesheuvel@linaro.org>", "list_archive_url": null, "date": "2017-08-28T18:04:35", "name": "[v3,0/2] pci: add support for firmware initialized designware RCs", "submitter": { "id": 26857, "url": "http://patchwork.ozlabs.org/api/people/26857/?format=api", "name": "Ard Biesheuvel", "email": "ard.biesheuvel@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/20170828180437.2646-1-ard.biesheuvel@linaro.org/mbox/", "series": [ { "id": 229, "url": "http://patchwork.ozlabs.org/api/series/229/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=229", "date": "2017-08-28T18:04:35", "name": "pci: add support for firmware initialized designware RCs", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/229/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/806701/comments/", "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"aNG8TsBD\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xh0695PW1z9sRm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 04:04:49 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751263AbdH1SEr (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tMon, 28 Aug 2017 14:04:47 -0400", "from mail-wm0-f48.google.com ([74.125.82.48]:38759 \"EHLO\n\tmail-wm0-f48.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751203AbdH1SEq (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Mon, 28 Aug 2017 14:04:46 -0400", "by mail-wm0-f48.google.com with SMTP id t201so8343861wmt.1\n\tfor <linux-pci@vger.kernel.org>; Mon, 28 Aug 2017 11:04:46 -0700 (PDT)", "from localhost.localdomain ([105.133.189.215])\n\tby smtp.gmail.com with ESMTPSA id\n\ti22sm1335922wrf.18.2017.08.28.11.04.42\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 28 Aug 2017 11:04:44 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id;\n\tbh=Xca2PJMusoDEEGzg9Li5WtKxLZJSdXRPGQOuH9t4uhE=;\n\tb=aNG8TsBDom+W2UbKYPUGxAAiMvAsC8hVwsL3HiqFNMoYFOkh5D1Qc3SiUg13dRiDIZ\n\tr5ozJe360oXBSbdzvx5GuF+c5O/TpVqJojVMWcysD/RDUm4VTSdx7SMdJj1Veo7UKEb1\n\tffTkCJtDlNz6Q//w7aKpKGGI/Amp58+a3qp3s=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=Xca2PJMusoDEEGzg9Li5WtKxLZJSdXRPGQOuH9t4uhE=;\n\tb=QA1Ve/0hHd8Eq2B+DPm5cmR/ktT/8wV71O2/x7enPEMT/J90LsMGTfet36cPbSct62\n\tkTyZNpTtrlfkXwjrolfVxkEj799c1sX/gPxY/YUsMOtHkUYfn87OPA90d612BnKpXbQB\n\tu7VRsk1Mdy6DCFUHKNaE/CrEGSfXp1Kh5OPReg3Yv/f3v9bXz/iT6mKku8sTRbBjAmqO\n\t4bSFonm6ZHQ46PEUYZKT0jF3zlSPtkuB8fE14KqH1q3pV0sTHMD2GkgAOoD3TXau+ECQ\n\tVTYdsvTZsMmTOTEvBAZ/xiqrwEItm1870mvkQK2EXaoIvxdqi5+mBL4+Wf89FfzB2qX+\n\tAK2A==", "X-Gm-Message-State": "AHYfb5hmHrVGh7BHgbOC5PpzWxwTCTQwXxEp7R6wJAj1PDe/vnDHfBlD\n\t1hv/hKXkOjcVWMz/ouTsgQ==", "X-Received": "by 10.28.20.67 with SMTP id 64mr925707wmu.100.1503943485035;\n\tMon, 28 Aug 2017 11:04:45 -0700 (PDT)", "From": "Ard Biesheuvel <ard.biesheuvel@linaro.org>", "To": "linux-pci@vger.kernel.org", "Cc": "devicetree@vger.kernel.org, mw@semihalf.com,\n\tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\tLeif Lindholm <leif.lindholm@linaro.org>,\n\tGraeme Gregory <graeme.gregory@linaro.org>,\n\tBjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>,\n\tJoao Pinto <Joao.Pinto@synopsys.com>, Rob Herring <robh@kernel.org>", "Subject": "[PATCH v3 0/2] pci: add support for firmware initialized designware\n\tRCs", "Date": "Mon, 28 Aug 2017 19:04:35 +0100", "Message-Id": "<20170828180437.2646-1-ard.biesheuvel@linaro.org>", "X-Mailer": "git-send-email 2.11.0", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "UEFI based systems incorporating a Synopsys Designware PCIe controller\nin RC mode will typically configure it before entering the OS. If this\nconfiguration is fully static and ECAM compliant, there is no need to\nexpose particulars of the device to the OS, and we can simply describe\nit as \"pci-host-ecam-generic\".\n\nHowever, the Synopsys IP may be synthesized in a way where a quirk is\nneeded for config space accesses to the first bus. It makes little sense\nto instantiate yet another pcie-designware driver that contains all the\nlow level setup code, but it is also not justified to add quirks handling\nto the generic ECAM driver.\n\nSo instead, create a variant of the generic ECAM driver that filters config\nspace accesses directed at device #1 and up on the first bus.\n\nv3: - use SoC specific compatible strings\n - drop MSI patch [for now], since it turns out we may not need it\n\nv2: - use dev->fwnode directly\n - replace an instance of pr_err with dev_err, and clarify the error message\n - fix Kconfig/Makefile dependency errors reported by kbuild\n\nCc: Leif Lindholm <leif.lindholm@linaro.org>\nCc: Graeme Gregory <graeme.gregory@linaro.org>\nCc: Bjorn Helgaas <bhelgaas@google.com>\nCc: Jingoo Han <jingoohan1@gmail.com>\nCc: Joao Pinto <Joao.Pinto@synopsys.com>\nCc: Rob Herring <robh@kernel.org>\n\nArd Biesheuvel (2):\n pci: designware: add driver for DWC controller in ECAM shift mode\n dt-bindings: designware: add binding for Designware PCIe in ECAM mode\n\n Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt | 42 +++++++++++\n drivers/pci/dwc/Kconfig | 11 +++\n drivers/pci/dwc/Makefile | 1 +\n drivers/pci/dwc/pcie-designware-ecam.c | 77 ++++++++++++++++++++\n 4 files changed, 131 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt\n create mode 100644 drivers/pci/dwc/pcie-designware-ecam.c" }