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{ "id": 2228708, "url": "http://patchwork.ozlabs.org/api/covers/2228708/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260427084055.2246089-1-steven_lee@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260427084055.2246089-1-steven_lee@aspeedtech.com>", "list_archive_url": null, "date": "2026-04-27T08:40:53", "name": "[RFC,v1,0/1] hw/arm: aspeed: PoC integration for Caliptra Root of Trust", "submitter": { "id": 81516, "url": "http://patchwork.ozlabs.org/api/people/81516/?format=api", "name": "Steven Lee", "email": "steven_lee@aspeedtech.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260427084055.2246089-1-steven_lee@aspeedtech.com/mbox/", "series": [ { "id": 501606, "url": "http://patchwork.ozlabs.org/api/series/501606/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501606", "date": "2026-04-27T08:40:53", "name": "hw/arm: aspeed: PoC integration for Caliptra Root of Trust", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501606/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2228708/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3xyN2ZbSz1yJX\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 18:47:06 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHHbZ-0005oD-T2; Mon, 27 Apr 2026 04:46:14 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <steven_lee@aspeedtech.com>)\n id 1wHHbX-0005ns-J9; Mon, 27 Apr 2026 04:46:11 -0400", "from mail.aspeedtech.com ([211.20.114.72]\n helo=twmbx01.aspeedtech.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <steven_lee@aspeedtech.com>)\n id 1wHHbV-0001C8-6z; Mon, 27 Apr 2026 04:46:11 -0400", "from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 27 Apr\n 2026 16:40:55 +0800", "from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend\n Transport; Mon, 27 Apr 2026 16:40:55 +0800" ], "To": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>, Troy Lee <leetroy@gmail.com>,\n Jamin Lin <jamin_lin@aspeedtech.com>, Kane Chen <kane_chen@aspeedtech.com>,\n \"Andrew Jeffery\" <andrew@codeconstruct.com.au>,\n Joel Stanley <joel@jms.id.au>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n \"open list:ASPEED BMCs\" <qemu-arm@nongnu.org>", "CC": "<troy_lee@aspeedtech.com>, <longzl2@lenovo.com>,\n <yunlin.tang@aspeedtech.com>, <steven_lee@aspeedtech.com>", "Subject": "[RFC PATCH v1 0/1] hw/arm: aspeed: PoC integration for Caliptra Root\n of Trust", "Date": "Mon, 27 Apr 2026 16:40:53 +0800", "Message-ID": "<20260427084055.2246089-1-steven_lee@aspeedtech.com>", "X-Mailer": "git-send-email 2.43.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "Received-SPF": "pass client-ip=211.20.114.72;\n envelope-from=steven_lee@aspeedtech.com; helo=twmbx01.aspeedtech.com", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Reply-to": "Steven Lee <steven_lee@aspeedtech.com>", "From": "Steven Lee via qemu development <qemu-devel@nongnu.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Hi all,\n\nThe ASPEED AST2700fc SoC integrates the Caliptra Root of Trust\n(Caliptra 1.2 core). Moving forward, we expect more SoCs to adopt\nCaliptra cores (e.g., Caliptra 2.x). Currently, QEMU does not have\na native Caliptra emulator.\n\nThis RFC explores possible approaches for supporting Caliptra in QEMU.\nThe included patch provides a Proof of Concept (PoC) integration using\nthe external `caliptra-sw` C-binding emulator to enable booting the\nAST2700fc machine.\n\nThis RFC does not propose merging the current PoC design as-is.\nInstead, it is intended to gather early feedback on architecture and\nintegration strategy.\n\nIn this PoC, the `caliptra-sw` emulator is used as a reference model\nto enable early bring-up and validation of the AST2700fc secure boot\nflow, rather than as a final implementation choice. The integration is\nbased on the `caliptra-1.2` branch of the official repository:\nhttps://github.com/chipsalliance/caliptra-sw/tree/caliptra-1.2\n\nTo avoid making normal ASPEED/AArch64 builds depend on a local external\ncheckout, the c-binding backend is compiled only when this PoC detects\nthe generated `caliptra-sw` c-binding header and static library in an\nexpected sibling source tree. A mergeable version would need an\nexplicit configure option and a proper dependency integration.\n\nSince QEMU currently lacks a `bootmcu` model and the associated mailbox\ninteractions with Caliptra, the PoC simplifies the boot flow by using\na background thread and the `caliptra_model_boot_default` C-binding to\nsimulate early boot stages.\n\nTo approximate the hardware behavior where the Cortex-A35 CPUs remain\nin reset until secure boot is completed, the PoC uses\n`vm_stop_force_state()` as a temporary approximation.\n\nThis approach is intentionally simplified and not intended to reflect\nthe final QEMU design. In particular, the use of a background thread\nand global VM control APIs may not align with QEMU device model\nexpectations.\n\nSupport for the `bootmcu` model and a more accurate secure boot flow\nis planned for future work.\n\nDiscussion points:\n\n1. Emulator strategy:\n For early enablement, is it acceptable to rely on an external\n reference model such as `caliptra-sw`, or would the community\n prefer focusing directly on a native QEMU QOM device model?\n\n2. Build system integration:\n If using the external `caliptra-sw` library is acceptable, what is\n the preferred integration method (e.g., git submodule, meson\n subproject, or system-installed library via pkg-config)?\n\n3. Boot synchronization:\n In real hardware, CPUs are held in reset until the secure boot\n flow completes. What is the recommended way in QEMU to model such\n dependencies between devices and CPU startup?\n\nFeedback and suggestions are highly appreciated.\n\nThanks,\nSteven\n\nSteven Lee (1):\n hw/arm: aspeed: Add PoC integration for Caliptra Root of Trust\n\n MAINTAINERS | 2 +\n docs/system/arm/aspeed.rst | 20 +++\n include/hw/arm/aspeed_caliptra_emu.h | 17 ++\n hw/arm/aspeed_ast27x0-fc.c | 60 +++++++\n hw/arm/aspeed_caliptra_emu.c | 259 +++++++++++++++++++++++++++\n hw/arm/meson.build | 31 +++-\n 6 files changed, 388 insertions(+), 1 deletion(-)\n create mode 100644 include/hw/arm/aspeed_caliptra_emu.h\n create mode 100644 hw/arm/aspeed_caliptra_emu.c" }