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{ "id": 2228003, "url": "http://patchwork.ozlabs.org/api/covers/2228003/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260424191129.1494381-1-daniel.barboza@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260424191129.1494381-1-daniel.barboza@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-24T19:11:25", "name": "[v5,0/4] hw/riscv: Server Platform Reference Board", "submitter": { "id": 92288, "url": "http://patchwork.ozlabs.org/api/people/92288/?format=api", "name": "Daniel Henrique Barboza", "email": "daniel.barboza@oss.qualcomm.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260424191129.1494381-1-daniel.barboza@oss.qualcomm.com/mbox/", "series": [ { "id": 501400, "url": "http://patchwork.ozlabs.org/api/series/501400/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501400", "date": "2026-04-24T19:11:25", "name": "hw/riscv: Server Platform Reference Board", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501400/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2228003/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=JXMn1yJc;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com 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6kmP+1Xkh2kyCVjM7nKACXAptDcIDL/3I4FPHgzH8j+G7+nhu1fmvOm24uksf/5OE3IK1z78=", "X-Received": [ "by 2002:a05:620a:4456:b0:8ef:6b87:5c5b with SMTP id\n af79cd13be357-8ef6b96ab05mr2013379585a.9.1777057894535;\n Fri, 24 Apr 2026 12:11:34 -0700 (PDT)", "by 2002:a05:620a:4456:b0:8ef:6b87:5c5b with SMTP id\n af79cd13be357-8ef6b96ab05mr2013371185a.9.1777057893963;\n Fri, 24 Apr 2026 12:11:33 -0700 (PDT)" ], "From": "Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com,\n zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,\n leif.lindholm@oss.qualcomm.com,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>", "Subject": "[PATCH v5 0/4] hw/riscv: Server Platform Reference Board", "Date": "Fri, 24 Apr 2026 16:11:25 -0300", "Message-ID": "<20260424191129.1494381-1-daniel.barboza@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.43.0", "MIME-Version": "1.0", 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a=p0WdMEafAAAA:8\n a=VwQbUJbxAAAA:8 a=bDdBU3oEAAAA:8 a=pGLkceISAAAA:8 a=WhSmBARFAgjbNTCObPUA:9\n a=PEH46H7Ffwr30OY-TuGO:22 a=DN7SgORnOiO7RqxRx1GC:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-24_02,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n bulkscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 spamscore=0\n priorityscore=1501 clxscore=1015 impostorscore=0 adultscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604240186", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=daniel.barboza@oss.qualcomm.com;\n helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Greetings,\n\nIn this new version the main change is that now we're no longer claiming\nan 'experimental' support, like we did in v4, because at this moment\n(well, when sdext [1] is upstreamed) we have all extensions required to\nsupport this reference board.\n\nAnother major change is the rename of the CPU and the board: we're\nnaming both 'riscv-server-ref' instead of 'rvsp-ref'. We're keeping the\n\"-ref\" suffix to match what ARM does with its reference board\n(sbsa-ref), but adding a longer name to be clearer about what the board\nis.\n\nPatches patches are based on alistair/riscv-to-apply.next @56bbd4f25c,\nplus Chao Liu's series \"[PATCH v6 0/7] riscv: add initial sdext support\"\n[1]. For convenience this series is available at this branch:\n\nhttps://gitlab.com/danielhb/qemu/-/tree/riscv-server-ref_v5\n\n\nChanges from v4:\n- removed 'experimental' qualifier from the board description;\n- changed CPU name from \"rvsp-ref\" to \"riscv-server-ref\"\n- changed board name from \"rvsp-ref\" to \"riscv-server-ref\"\n- former patch 4 (\"hw/riscv/server_platform_ref.c: add riscv-iommu-sys\"):\n - squashed into patch 3\n- v4 link: https://lore.kernel.org/qemu-devel/20251111182944.2895892-1-dbarboza@ventanamicro.com/\n\n[1] https://lore.kernel.org/qemu-devel/cover.1775959096.git.chao.liu.zevorn@gmail.com/\n\n\nDaniel Henrique Barboza (2):\n target/riscv/cpu.c: remove 'bare' condition for .profile\n docs: add riscv-server-ref.rst\n\nFei Wu (2):\n target/riscv: Add server platform reference cpu\n hw/riscv: server platform reference machine\n\n configs/devices/riscv64-softmmu/default.mak | 1 +\n docs/system/riscv/riscv-server-ref.rst | 31 +\n docs/system/target-riscv.rst | 1 +\n hw/riscv/Kconfig | 15 +\n hw/riscv/meson.build | 1 +\n hw/riscv/server_platform_ref.c | 1371 +++++++++++++++++++\n target/riscv/cpu-qom.h | 1 +\n target/riscv/cpu.c | 12 +-\n 8 files changed, 1432 insertions(+), 1 deletion(-)\n create mode 100644 docs/system/riscv/riscv-server-ref.rst\n create mode 100644 hw/riscv/server_platform_ref.c" }