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{
    "id": 2227809,
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    "project": {
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        "name": "Linux PCI development",
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    "msgid": "<20260424094913.522123-1-mahesh.vaidya@altera.com>",
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    "date": "2026-04-24T09:49:10",
    "name": "[0/3] PCI: altera: Add Agilex 5 PCIe Root Port support",
    "submitter": {
        "id": 92067,
        "url": "http://patchwork.ozlabs.org/api/people/92067/?format=api",
        "name": "Mahesh Vaidya",
        "email": "mahesh.vaidya@altera.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260424094913.522123-1-mahesh.vaidya@altera.com/mbox/",
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            "date": "2026-04-24T09:49:10",
            "name": "PCI: altera: Add Agilex 5 PCIe Root Port support",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/501332/mbox/"
        }
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        "From": "Mahesh Vaidya <mahesh.vaidya@altera.com>",
        "To": "joyce.ooi@intel.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\trobh@kernel.org,\n\tbhelgaas@google.com,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org",
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        "Subject": "[PATCH 0/3] PCI: altera: Add Agilex 5 PCIe Root Port support",
        "Date": "Fri, 24 Apr 2026 02:49:10 -0700",
        "Message-Id": "<20260424094913.522123-1-mahesh.vaidya@altera.com>",
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    "content": "This series adds PCIe Root Port controller support for the Intel\nAgilex 5 family of SoC FPGAs to the existing pcie-altera driver.\n\nThe Agilex 5 PCIe Hard IP reuses the same config-space access path\nas Agilex 7 (V3). Root port and endpoint configuration reads/writes\nuse direct MMIO to the HIP and CRA regions.\n\nThe difference is in the HIP port-level registers (IRQ status and IRQ\nenable). On V3 these are directly mapped through the Hip MMIO window.\nOn V4 these registers are only reachable through an indirect access\nmailbox (CFG REG IA CTRL) in the PCIe Subsystem AXI-Lite interface,\ndocumented in the GTS AXI Streaming IP for PCIe User Guide.\n\nThe indirect access sequence writes the target address and control\nbits to the mailbox registers, polls for completion, then reads the\nresult. Since the chained IRQ handler runs in hardirq context,\nreadl_poll_timeout_atomic is used with a 1ms timeout.\n\nTested on an Agilex 5 E-series Premium Development Kit with an\nNVMe endpoint. Verified:\n  - PCIe link-up at the expected width and speed\n  - NVMe endpoint enumeration and binding to the nvme driver\n  - NVMe read/write I/O via fio with no errors or timeouts\n  - MSI interrupt delivery observed via /proc/interrupts during I/O\n\nPatch 1 adds the DT binding compatible string for Agilex 5.\nPatch 2 fixes pre-existing resource leaks in the probe error path,\n        which the Agilex 5 support patch depends on.\nPatch 3 adds the V4 driver support: indirect register access helpers,\n        the chained IRQ handler, and the platform data.\n\nMahesh Vaidya (3):\n  dt-bindings: PCI: altera: add binding for Agilex 5\n  PCI: altera: fix resource leaks on probe failure\n  PCI: altera: add Agilex 5 support\n\n .../bindings/pci/altr,pcie-root-port.yaml     |  37 ++--\n drivers/pci/controller/pcie-altera.c          | 173 +++++++++++++++++-\n 2 files changed, 190 insertions(+), 20 deletions(-)\n\n\nbase-commit: 4224e91fea5695a89843b4c38283016616946307"
}