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{ "id": 2227666, "url": "http://patchwork.ozlabs.org/api/covers/2227666/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260424043014.46305-1-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260424043014.46305-1-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-24T04:29:34", "name": "[v2,00/40] target/arm: Implement FEAT_FP8", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260424043014.46305-1-richard.henderson@linaro.org/mbox/", "series": [ { "id": 501300, "url": "http://patchwork.ozlabs.org/api/series/501300/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300", "date": "2026-04-24T04:29:37", "name": "target/arm: Implement FEAT_FP8", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501300/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2227666/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=TXfntDMP;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20Rr1dQVz1yDD\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 24 Apr 2026 14:32:24 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wG8Bl-0005jn-T8; Fri, 24 Apr 2026 00:30:49 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wG8BV-0005bX-7N\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:30:36 -0400", "from mail-oa1-x31.google.com ([2001:4860:4864:20::31])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wG8BR-0002UD-1r\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:30:32 -0400", "by mail-oa1-x31.google.com with SMTP id\n 586e51a60fabf-404254ffe8aso5224827fac.0\n for <qemu-devel@nongnu.org>; Thu, 23 Apr 2026 21:30:27 -0700 (PDT)", "from stoup.. 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Once again I wish TF-A\nwould filter the reported ID registers to match the features for which\nit is configured.\n\nPierrick, are you happy to continue hosting these images, or should we\nnominate a Linaro host for these?\n\n\nr~\n\n\nCc: pierrick.bouvier@oss.qualcomm.com\nCc: alex.bennee@linaro.org\n\n\nRichard Henderson (40):\n target/arm: Implement ID_AA64ISAR3\n target/arm: Implement FEAT_FAMINMAX for AdvSIMD\n target/arm: Implement FEAT_FAMINMAX for SME\n target/arm: Implement FEAT_FAMINMAX for SVE\n target/arm: Enable FEAT_FAMINMAX for -cpu max\n target/arm: Update SCR bits for Arm ARM M.a.a\n target/arm: Update HCRX bits for Arm ARM M.a.a\n target/arm: Introduce FPMR\n target/arm: Update SCTLR bits for FEAT_FPMR\n target/arm: Enable EnFPM bits for FEAT_FPMR\n target/arm: Clear FPMR on ResetSVEState\n target/arm: Add FPMR_EL to TBFLAGS\n target/arm: Trap direct acceses to FPMR\n target/arm: Enable FEAT_FPMR for -cpu max\n target/arm: Implement ID_AA64FPFR0\n target/arm: Add isar_feature_aa64_f8cvt\n target/arm: Implement FSCALE for AdvSIMD\n target/arm: Implement FSCALE for SME\n fpu: Add scalbn argument to fp8 conversion routines\n fpu: Add conversions between float16 and float8 formats\n target/arm: Split vector-type.h from cpu.h\n target/arm: Move vectors_overlap to vec_internal.h\n target/arm: Implement BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 for AdvSIMD\n target/arm: Implement BF1CVT, BF1CVTLT, BF2CVT, BF2CVTLT for SVE\n target/arm: Rename SME BFCVT patterns to BFCVT_hs\n target/arm: Implement BF1CVT, BF1CVTL, BF2CVT, BF2CVTL for SME\n target/arm: Implement F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 for AdvSIMD\n target/arm: Implement F1CVT, F1CVTLT, F2CVT, F2CVTLT for SVE\n target/arm: Implement F1CVT, F1CVTL, F2CVT, F2CVTL for SME\n target/arm: Implement BFCVTN for SVE\n target/arm: Implement FCVTN (16- to 8-bit fp) for AdvSIMD\n target/arm: Implement FCVTN, FCVTN2 (32- to 8-bit fp) for AdvSIMD\n target/arm: Implement FCVTN (16- to 8-bit fp) for SVE\n target/arm: Implement FCVTNB, FCVTNT for SVE\n target/arm: Implement FCVT (FP16 to FP8) for SME\n target/arm: Implement FCVT, FCVTN (FP32 to FP8) for SME\n target/arm: Implement LUTI2, LUTI4 for AdvSIMD\n target/arm: Implement LUTI2, LUTI4 for SVE\n target/arm: Enable FEAT_LUT for -cpu max\n target/arm: Enable FEAT_FP8 for -cpu max\n\n include/fpu/softfloat.h | 22 +-\n target/arm/cpregs.h | 5 +\n target/arm/cpu-features.h | 66 +++\n target/arm/cpu.h | 52 +--\n target/arm/helper-fp8.h | 14 +\n target/arm/internals.h | 13 +-\n target/arm/tcg/helper-a64-defs.h | 11 +\n target/arm/tcg/helper-defs.h | 5 +\n target/arm/tcg/helper-fp8-defs.h | 25 ++\n target/arm/tcg/helper-sme-defs.h | 2 +-\n target/arm/tcg/helper-sve-defs.h | 14 +\n target/arm/tcg/translate-a64.h | 1 +\n target/arm/tcg/translate.h | 10 +\n target/arm/tcg/vec_internal.h | 19 +\n target/arm/vector-type.h | 44 ++\n fpu/softfloat.c | 73 ++-\n target/arm/helper.c | 43 +-\n target/arm/machine.c | 20 +\n target/arm/tcg/cpu64.c | 13 +\n target/arm/tcg/fp8_helper.c | 742 +++++++++++++++++++++++++++++++\n target/arm/tcg/hflags.c | 41 ++\n target/arm/tcg/sme_helper.c | 8 +-\n target/arm/tcg/sve_helper.c | 8 +\n target/arm/tcg/translate-a64.c | 133 ++++++\n target/arm/tcg/translate-sme.c | 85 +++-\n target/arm/tcg/translate-sve.c | 111 +++++\n target/arm/tcg/vec_helper.c | 52 +++\n target/arm/tcg/vec_helper64.c | 51 +++\n docs/system/arm/emulation.rst | 4 +\n target/arm/cpu-sysregs.h.inc | 2 +\n target/arm/tcg/a64.decode | 23 +\n target/arm/tcg/meson.build | 1 +\n target/arm/tcg/sme.decode | 28 +-\n target/arm/tcg/sve.decode | 29 +-\n 34 files changed, 1691 insertions(+), 79 deletions(-)\n create mode 100644 target/arm/helper-fp8.h\n create mode 100644 target/arm/tcg/helper-fp8-defs.h\n create mode 100644 target/arm/vector-type.h\n create mode 100644 target/arm/tcg/fp8_helper.c" }