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{ "id": 2227086, "url": "http://patchwork.ozlabs.org/api/covers/2227086/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/cover/20260423083644.1168-1-dongxuyang@eswincomputing.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260423083644.1168-1-dongxuyang@eswincomputing.com>", "list_archive_url": null, "date": "2026-04-23T08:36:44", "name": "[v5,0/2] Update designware pwm driver", "submitter": { "id": 90849, "url": "http://patchwork.ozlabs.org/api/people/90849/?format=api", "name": "Xuyang Dong", "email": "dongxuyang@eswincomputing.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/cover/20260423083644.1168-1-dongxuyang@eswincomputing.com/mbox/", "series": [ { "id": 501161, "url": "http://patchwork.ozlabs.org/api/series/501161/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=501161", "date": "2026-04-23T08:36:44", "name": "Update designware pwm driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501161/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2227086/comments/", "headers": { "Return-Path": "\n <linux-pwm+bounces-8676-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8676-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=4.193.249.245", "smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=eswincomputing.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=eswincomputing.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1TxT4BHvz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 18:37:49 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id E9FEE3002D0E\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 08:37:27 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id A825C3D6698;\n\tThu, 23 Apr 2026 08:37:25 +0000 (UTC)", "from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net\n [4.193.249.245])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 24EDD2F0C45;\n\tThu, 23 Apr 2026 08:37:20 +0000 (UTC)", "from E0005152DT.eswin.cn (unknown [10.12.96.41])\n\tby app1 (Coremail) with SMTP id TAJkCgCnPHEf2ulpgv8TAA--.10885S2;\n\tThu, 23 Apr 2026 16:36:48 +0800 (CST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776933445; cv=none;\n b=U7wVzW6xL/PA4nkBedicSSnLXh9UI2yBsbcROySJdzuTmFLMxu3tFZviv64zRp3jEGDRbZPkIhwohHxn2HjswrvfovGkANGn84f+uUy90dTk/vrU2EaZFgycHFyRtso5XOJzERStMe/FIHqW6lYwTU+Wj2yIKq/G+rH+sNSzahc=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776933445; c=relaxed/simple;\n\tbh=M6CLT/mzCDc5py6uLbMhru/2xAsohHfncxfGePIVnYo=;\n\th=From:To:Cc:Subject:Date:Message-Id:MIME-Version;\n b=QyKWjv2+Acgj7WKa1uk414F8ThLPStn1TRpwDG8QM9P7h/1GSR+CMcNXG04wEJRsIiOSvfOwGE/e8jGL9Ycg5Aefmwg/hoSd8kdVMCEG36dadmtEySaHUUm7aeNF8OlVxamIgYL7uqPqHUZ9Mq/9ATMs/x47C924EgdGmtE7Cf8=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=eswincomputing.com;\n spf=pass smtp.mailfrom=eswincomputing.com;\n arc=none smtp.client-ip=4.193.249.245", "From": "Xuyang Dong <dongxuyang@eswincomputing.com>", "To": "ukleinek@kernel.org,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tben-linux@fluff.org,\n\tben.dooks@codethink.co.uk,\n\tp.zabel@pengutronix.de,\n\tlinux-pwm@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org", "Cc": "ningyu@eswincomputing.com,\n\tlinmin@eswincomputing.com,\n\txuxiang@eswincomputing.com,\n\twangguosheng@eswincomputing.com,\n\tpinkesh.vaghela@einfochips.com,\n\tXuyang Dong <dongxuyang@eswincomputing.com>", "Subject": "[PATCH v5 0/2] Update designware pwm driver", "Date": "Thu, 23 Apr 2026 16:36:44 +0800", "Message-Id": "<20260423083644.1168-1-dongxuyang@eswincomputing.com>", "X-Mailer": "git-send-email 2.31.1.windows.1", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "TAJkCgCnPHEf2ulpgv8TAA--.10885S2", "X-Coremail-Antispam": "1UD129KBjvJXoWxKFyUArW8Ary5XFW8Ary7Jrb_yoW7WryrpF\n\tW8GryakrWkWryIgan7X3W8uFyYqa1fJF4UKwn5ta4UZwn0y3yUJrZY9F15tF9Fvr4kW34Y\n\tya4fG3W29a4YyaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDU0xBIdaVrnRJUUU9G14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n\trVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02\n\t1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U\n\tJVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc\n\tCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E\n\t2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV\n\tW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2\n\tY2ka0xkIwI1lc7CjxVAaw2AFwI0_Jw0_GFylc2xSY4AK6svPMxAIw28IcxkI7VAKI48JMx\n\tC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAF\n\twI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20x\n\tvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v2\n\t0xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxV\n\tW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VU13ku3UUUUU==", "X-CM-SenderInfo": "pgrqw5xx1d0w46hv4xpqfrz1xxwl0woofrz/" }, "content": "There is already a patch [1] for the DesignWare PWM driver,\nwhich is posted by Ben and still under review.\nBased on this patch, this series is a continuation of [1]\nto add support for IP versions 2.11a and later, which\nincludes support for \"Pulse Width Modulation with 0%\nand 100% Duty Cycle\".\n\nSupported chips:\nESWIN EIC7700 series SoC.\n\nTest:\nTested this patch on the Sifive HiFive Premier P550 (which uses the EIC7700\nSoC).\n\n[1] https://lore.kernel.org/lkml/20230907161242.67190-1-ben.dooks@codethink.co.uk/\n\nUpdates:\n Changes in v5:\n - YAML:\n - Add 'eswin,eic7700-pwm' compatible string.\n - Add the items description for the resets property and set minItems to 1.\n - Require resets property with exactly 1 reset for eswin,eic7700-pwm compatible.\n - Driver:\n - Add support for 'eswin,eic7700-pwm' compatible.\n - Add structure dwc_pwm_plat_data to manage the API for obtaining resets.\n\n - Link to v4: https://lore.kernel.org/all/20260415094908.1539-1-dongxuyang@eswincomputing.com/\n\n Changes in v4:\n - YAML:\n - Change maxItems from 1 to 2. As there is a corresponding reset signal\n for each clock domain, the effective maxItems of the resets property\n is set to 2.\n - Update the YAML commit message to describe the hardware.\n - Driver:\n - Replace devm_reset_control_get_optional_exclusive() with\n devm_reset_control_array_get_optional_exclusive(). Since the number\n of reset signals has increased from one to two, we need to use the\n array API to acquire them.\n\n - Link to v3: https://lore.kernel.org/all/20260402091718.1608-1-dongxuyang@eswincomputing.com/\n\n Changes in v3:\n - YAML:\n - Added a clear justification for the optional resets property. It is\n required to support proper controller initialization when no PWM\n channel is active at boot time, while allowing the driver to skip\n reset deassertion if any channel is already enabled.\n - Driver:\n - Update the boundary value check of tmp in __dwc_pwm_configure_timer()\n for DWC_TIM_CTRL_0N100PWM_EN.\n - Replace 'sizeof(struct dwc_pwm_drvdata)' with\n 'struct_size(data, chips, 1)'.\n - Drop devm_clk_get_enabled() in favor of devm_clk_get() with explicit\n clk_prepare_enable() and clk_disable_unprepare() allowing runtime PM\n to manage clock state.\n - Replace devm_reset_control_get_optional_exclusive_deasserted() with\n devm_reset_control_get_optional_exclusive() and issue a full reset via\n reset_control_reset() only when no PWM channel is active at probe time.\n - Detect bootloader-enabled PWM channels by reading the enable bit, and\n initialize runtime PM as active for those channels by calling\n pm_runtime_set_active() and pm_runtime_get_noresume().\n - Remove autosuspend as it is not required for this driver.\n - Use explicit pm_runtime_enable() and pm_runtime_disable() instead of\n the managed devm_pm_runtime_enable() variant to ensure correct cleanup.\n - On device removal, recheck the channel enable status. If any channel\n remains active, call pm_runtime_put_noidle() before disabling clocks\n via clk_disable_unprepare().\n Resume device before register access during removal if it is runtime\n suspended, and re-suspend it afterward.\n - If device is suspended, resume it before register access during system\n resume/suspend.\n - Use pm_ptr() instead of pm_sleep_ptr() for correct PM operation.\n\n - Link to v2: https://lore.kernel.org/all/20260306093000.2065-1-dongxuyang@eswincomputing.com/\n\n Changes in v2:\n - YAML:\n - Remove eswin,eic7700-pwm.yaml. Use snps,dw-apb-timers-pwm2.yaml.\n The description in snps,dw-apb-timers-pwm2.yaml is better.\n - Add the resets property as optional, as defined in the databook.\n - Remove snps,pwm-full-range-enable as no additional property is needed.\n - Driver:\n - Change the file from pwm-dwc-eic7700.c to pwm-dwc-of.c from [1].\n - Define DWC_TIM_VERSION_ID_2_11A 2.11a as the baseline version.\n - Enable the 0% and 100% duty cycle mode by setting dwc->feature if\n the version read from the TIMERS_COMP_VERSION register is later\n than or equal to DWC_TIM_VERSION_ID_2_11A.\n - Use the DIV_ROUND_UP_ULL() to calculate width in the .apply and\n .get_state.\n - Additionally, Power Management (PM) support has been added to the\n pwm-dwc-of.c driver.\n - Drop the headers that are not used.\n - Use devm_clk_get_enabled() instead of devm_clk_get().\n - Drop of_match_ptr.\n - Fix build error with 1ULL << 32.\n Reported-by: kernel test robot <lkp@intel.com>\n Closes: https://lore.kernel.org/oe-kbuild-all/202512061720.j31AsgM7-lkp@intel.com/\n\n - Link to v1: https://lore.kernel.org/all/20251205090411.1388-1-dongxuyang@eswincomputing.com/\n - Link to v9: https://lore.kernel.org/lkml/20230907161242.67190-1-ben.dooks@codethink.co.uk/\n\nXuyang Dong (2):\n dt-bindings: pwm: dwc: add optional reset\n pwm: dwc: add of/platform support\n\n .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 29 +-\n drivers/pwm/Kconfig | 10 +\n drivers/pwm/Makefile | 1 +\n drivers/pwm/pwm-dwc-core.c | 101 +++--\n drivers/pwm/pwm-dwc-of.c | 346 ++++++++++++++++++\n drivers/pwm/pwm-dwc.h | 25 +-\n 6 files changed, 479 insertions(+), 33 deletions(-)\n create mode 100644 drivers/pwm/pwm-dwc-of.c\n\n--\n2.34.1" }