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{ "id": 2226911, "url": "http://patchwork.ozlabs.org/api/covers/2226911/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260422214225.2242-1-mohamed@unpredictable.fr/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422214225.2242-1-mohamed@unpredictable.fr>", "list_archive_url": null, "date": "2026-04-22T21:41:48", "name": "[v3,00/37] WHPX x86 updates for QEMU 11.1", "submitter": { "id": 91318, "url": "http://patchwork.ozlabs.org/api/people/91318/?format=api", "name": "Mohamed Mediouni", "email": "mohamed@unpredictable.fr" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260422214225.2242-1-mohamed@unpredictable.fr/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/covers/2226911/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=djIUge33;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1CQy5xy1z1yDD\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 07:43:53 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wFfLH-0007sU-Fn; Wed, 22 Apr 2026 17:42:43 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wFfLF-0007qz-Jh\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:42:41 -0400", "from p-east2-cluster1-host2-snip4-7.eps.apple.com ([57.103.76.40]\n helo=outbound.st.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wFfLC-0006vM-Uj\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:42:41 -0400", "from outbound.st.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPS id\n 06D1218006E9; Wed, 22 Apr 2026 21:42:30 +0000 (UTC)", "from localhost.localdomain (unknown [17.42.251.67])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPSA id\n 2D6E91800216; Wed, 22 Apr 2026 21:42:28 +0000 (UTC)" ], "X-ICL-Out-Info": "\n HUtFAUMHWwJACUgBTUQeDx5WFlZNRAJCTQFIHV8DWRxBAUkdXw9LVxQEFVwFVgZXFHkNXR1FDlYZWgxSD1sOHBZLWFUJCgZdGFgVVgl3HlwASx1XBFQfUxJVHR0LRUtAEwRJAU1fDl4fBBdGGVUERx5dVkAZGQJRHFYNV0NUBF9QSQxBUGxaAEcXSB1dGVlvUF0cDhhZG0AVXRFQGVYJXhUXHkFNWgJWTQVKA18BWwZCC0oCWQVZB14LSgdfGlofHVYQUgBSD3IFVwhBCFMCUQRYGl8IGQ1AThkMSh1SVlEFSgxcAGgPXR1YEV0=", "Dkim-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776894154; x=1779486154;\n bh=wEThq2dfzqTlfZKnGhPwgL+9iHFZpwM3gQfdJLwsJ0M=;\n h=From:To:Subject:Date:Message-ID:Content-Type:MIME-Version:x-icloud-hme;\n b=djIUge33BiTJ7cNlHcSWJPuhgBSlV+ih9wAg64c8CafPkV5otElCNHd7jr7JZcWHQeS42tPSI4nKtFeTrQarkY0VGSxTYfEfMEhW2xFY3CUk+O19xn+wNG7gdoVFlkquZS1qK4uD7Jf0OIdfJAzQ7Q9AlrkDajXokZIdmASdPUPjyHjf7jv0TgDCUCyPG5m59ccU5GcB/zKaUMG+9p5Vux9G4x/j5sjJaH44APeYAo9JuHltIoG5ijxg/hp0iH2Ja6FP60FOik+dp+8CeS0wSM6ZZTKaryHX1L+h4unX8u5n2o498L4QnEzW+mN3r89BX+c+lFG7XNZoS/Mx6dYD7Q==", "mail-alias-created-date": "1752046281608", "From": "Mohamed Mediouni <mohamed@unpredictable.fr>", "To": "qemu-devel@nongnu.org", "Cc": "Pedro Barbuda <pbarbuda@microsoft.com>, qemu-arm@nongnu.org,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Mohamed Mediouni <mohamed@unpredictable.fr>,\n Roman Bolshakov <rbolshakov@ddn.com>,\n \"Michael S. Tsirkin\" <mst@redhat.com>, Wei Liu <wei.liu@kernel.org>,\n Phil Dennis-Jordan <phil@philjordan.eu>,\n Peter Maydell <peter.maydell@linaro.org>, Zhao Liu <zhao1.liu@intel.com>,\n Paolo Bonzini <pbonzini@redhat.com>", "Subject": "[PATCH v3 00/37] WHPX x86 updates for QEMU 11.1", "Date": "Wed, 22 Apr 2026 23:41:48 +0200", "Message-ID": "<20260422214225.2242-1-mohamed@unpredictable.fr>", "X-Mailer": "git-send-email 2.50.1", "Content-Type": "text/plain; charset=\"utf-8\"", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIyMDIxMSBTYWx0ZWRfX7rHVWG32ymTg\n 9OIR7WW2xoAV7jeRar3RAC3M6Q87NymVyc7mLTRcv9KEA4+UlUp/YCFqNY7n0RGdrsKk/SMiZ1e\n +cDKgrtaB0eUPI/8xN/ri7OI3+yMQYasQ84AQDuofHdyHfsBWopuPCzqfoGGGzx7nHTkJnjMyjr\n 75ApCFnovTf5c0rcNrQp70AyPpkY4svbfWcOzkiAI1+tRAEW/OKRpaMyDUxyQua1L2UYWxwR/IH\n bn1ZblgGx7pRTowQQIpwqC0n/fNL+w3oPwOCcyNPHj5BHtX0d9WMtq/U4VUuzOANzZ+3oSB2Y54\n o9XWSuo8YYkRGpAbk4L2M7TUOyYLz6dX3RLjPpOtfX0FY0+/JQIvxuBeqPZo28=", "X-Proofpoint-GUID": "by-g_CXpbxjrp2KOMlP7sy9SLb1HqVJJ", "X-Proofpoint-ORIG-GUID": "by-g_CXpbxjrp2KOMlP7sy9SLb1HqVJJ", "X-Authority-Info-Out": "v=2.4 cv=C4DkCAP+ c=1 sm=1 tr=0 ts=69e940c8\n cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117\n a=YrL12D//S6tul8v/L+6tKg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=NEAV23lmAAAA:8 a=bnQU8WpU6WbG6yeDcMYA:9\n a=QEXdDO2ut3YA:10", "Received-SPF": "pass client-ip=57.103.76.40;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This rolls over my previous series posted earlier in this mailing list.\n..and adds some more.\n\nGit tree: https://github.com/mediouni-m/qemu whpx-i386-202604-4\n\nSome highlights:\n1\n- user-mode x2APIC emulation (kernel-irqchip=off) for better\nperformance when it has to be used.\n- CPU model emulation on both Windows 10 and 11\n- configurable behavior for unknown MSRs and adding a way\nto trap on GPFs raised by Hyper-V on MSR acccess\n- when -M hyperv=off, report the hypervisor as VMware for\nguests to use either the VMware CPUID leaf or the vmport\ninterface to get the TSC and APIC frequencies.\n\nIf the vmware CPUID frequency leaf is disabled, then KVM\nis reported.\n- xsave save/restore support\n- Pause the VM to be able to inspect state on a fatal fault\ninstead of just exiting\n- adding emulation of an oddball idle MSR used by Windows\nwhen kernel-irqchip=off.\n- disable kernel-irqchip and Hyper-V enlightenments for\nisapc\n- for Windows 10, change the default to an emulated x2APIC\n(kernel-irqchip=off). The recommended way to use the Hyper-V\nLAPIC is not to use -M kernel-irqchip=on, but -M pic=off.\n\nAnd as the last commit, a documentation update.\n\nBug reports and patches are welcome.\n\nHowever, due to reasons, I'll probably step aside\nfrom this all for a bit so don't expect immediate replies.\n\nv1->v2:\n\n- Build fixup for macOS and OpenBSD\n- a bit of cleanup\n\nv2->v3:\n\nUnfortunately this rev has quite a bit of changes...\n\n- Some fixes here and there.\n- Merging in Windows 10 support into something less separate.\n- Move new x86-specific (at least for now) properties into a new\nwhpx_arch_accel_class_init method.\n- Add nested virt settings and separate security domain accelerator\nproperties.\n\nMagnus Kulke (1):\n target/i386: add de/compaction to xsave_helper\n\nMohamed Mediouni (36):\n target/i386: emulate: include name of unhandled instruction\n whpx: i386: x2apic emulation\n whpx: i386: wire up feature probing\n whpx: i386: disable TbFlushHypercalls for emulated LAPIC\n whpx: i386: enable x2apic by default for user-mode LAPIC\n whpx: i386: reintroduce enlightenments for Windows 10\n whpx: i386: introduce proper cpuid support\n whpx: i386: kernel-irqchip=off fixes\n whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off\n whpx: i386: disable kernel-irqchip on Windows 10 when PIC enabled\n whpx: i386: IO port fast path cleanup\n whpx: i386: disable enlightenments and LAPIC for isapc\n whpx: i386: interrupt priority support\n hw/intc: apic: disallow APIC reads when disabled\n whpx: i386: fix CPUID[1:EDX].APIC reporting\n whpx: i386: set apicbase value only on success\n whpx: i386: unknown MSR configurability\n whpx: i386: enable GuestIdleReg enlightenment\n whpx: i386: tighten APIC base validity check\n whpx: i386: ignore vpassist when kernel-irqchip=off\n target: i386: HLT type that ignores EFLAGS.IF\n whpx: i386: add HV_X64_MSR_GUEST_IDLE when !kernel-irqchip\n whpx: i386: some x2APIC awareness\n whpx: i386: set WHvX64RegisterInitialApicId\n whpx: i386: Pause VM on fatal exception to be able to inspect state\n target/i386: emulate: use exception_payload for fault address\n target/i386: make xsave_buf present unconditionally\n whpx: xsave support\n whpx: i386: set APIC ID only when APIC present\n whpx: i386: update migration blocker message\n whpx: i386: don't increment eip on MSR access raising GPF\n target/i386: emulate, hvf: rdmsr/wrmsr GPF handling\n whpx: i386: add feature to intercept #GP MSR accesses\n whpx: i386: nested virt settings\n whpx: i386: add SeparateSecurityDomain flag and make default\n whpx: i386: documentation update\n\n accel/whpx/whpx-common.c | 8 +\n docs/system/whpx.rst | 40 +-\n hw/intc/apic.c | 9 +\n include/system/whpx-all.h | 1 +\n include/system/whpx-common.h | 2 +-\n include/system/whpx-internal.h | 31 +\n target/arm/whpx/whpx-all.c | 5 +\n target/i386/cpu.c | 27 +-\n target/i386/cpu.h | 6 +-\n target/i386/emulate/x86_emu.c | 14 +-\n target/i386/emulate/x86_emu.h | 4 +-\n target/i386/emulate/x86_mmu.c | 3 +-\n target/i386/hvf/hvf-i386.h | 4 +-\n target/i386/hvf/hvf.c | 9 +-\n target/i386/whpx/meson.build | 1 +\n target/i386/whpx/whpx-all.c | 1489 +++++++++++++++++++++++-----\n target/i386/whpx/whpx-apic.c | 83 +-\n target/i386/whpx/whpx-cpu-legacy.c | 158 +++\n target/i386/whpx/whpx-i386.h | 12 +\n target/i386/xsave_helper.c | 256 +++++\n 20 files changed, 1875 insertions(+), 287 deletions(-)\n create mode 100644 target/i386/whpx/whpx-cpu-legacy.c\n create mode 100644 target/i386/whpx/whpx-i386.h" }